JPH05347412A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce a thermal resistance by a method wherein a contact hole reaches an insulating layer under a semiconductor layer and an electrode conductor film is brought into contact with the insulating layer in the contact hole. CONSTITUTION:A whole MOS-FET is covered with a silicon oxide film 15. The silicon oxide film 15, a high impurity concentration diffused layer 13 and an insulating layer 11 are partially removed at the parts of the contact holes 22 and electrode conductor films 16 such as W films are buried in the contact holes 22. The side surfaces and bottom surfaces of the electrode conductor films 16 are brought into contact with the insulating layer 11 and Al films 17 are connected to the top surfaces of the electrode conductor films 16 to provide interconnection. It is desirable to have the thickness of the insulating film 11 remaining under the bottom of the contact hole as small as possible but, taking the variation of the film thickness and etching into account, the thickness about 0.5 microns is recommended. In a semiconductor integrated circuit having an SOI structure, heat generated in a transistor region can be discharged easily into a silicon substrate 10 through the contact hole part. As the thickness of the insulating layer 11 under the contact hole is 1/4 of the film thickness of a conventional constitution, the thermal resistance can be also about 1/4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit which achieves both ultra high speed and ultra high integration.

[0002]

2. Description of the Related Art Semiconductor integrated circuits, especially CMOS-LSI
Has continued to increase in speed and degree of integration, and further improvement in these performances is required in the future.

Up to now, performance improvement has mainly been achieved by scaling. Since submicron scaling has been performed under a constant power supply voltage, a significant improvement in operating speed can be achieved. However, since the power supply voltage is unavoidably reduced after submicron, the tendency for improvement of the operating speed is beginning to be seen only by scaling.

Therefore, new technologies are being developed to overcome these obstacles. One of them is a so-called SOI structure in which a semiconductor layer in which a semiconductor element is formed is provided over an insulating layer.

FIG. 3 is a sectional view showing an example of a conventional semiconductor integrated circuit having an SOI structure. Silicon semiconductor substrate 1
0, an insulator layer 11 is provided, and a silicon semiconductor layer 12 is further provided thereon. The high-concentration diffusion layer 1 serving as the source and drain regions is formed on a part of the silicon semiconductor layer
3 is formed, and constitutes a MOSFET with the gate electrode 14 on the gate insulating film 20.

The entire MOSFET is covered with a silicon oxide film 15 as an insulating film, the oxide film in the portion of the contact hole 21 is removed and an electrode conductor film 20 of W (tungsten) or the like is buried, and an AL (aluminum) wiring film is formed. 17
Wiring is done with. The SOI structure is obtained by single-crystallizing a silicon layer on an insulator layer by various methods, or by implanting oxygen atoms into a silicon substrate to form an oxide film layer as an insulator layer inside. Be done.

It has been reported that in the MOSFET having the SOI structure, the capacitance of the diffusion layer can be made extremely small, and the on-current increases when the thickness of the silicon layer is 100 nanometers or less. Further, in the SOI structure, the active regions forming the individual transistors are completely separated by the insulator, so that there is no need for a well as in a normal bulk CMOS. Therefore, N-channel MOSFET
The P-channel MOSFET and the P-channel MOSFET can be arranged very close to each other, which is also advantageous in terms of integration.

[0008]

However, the above-mentioned integrated circuit having the SOI structure has the following problems.

In integrated circuits, heat is generated especially in the transistor area. This calorific value is considerable, and sometimes reaches tens of watts. Therefore, in the integrated circuit device, various heat dissipation measures are taken, but the temperature of the integrated circuit is several tens of degrees,
Sometimes it rises near Baidu. The temperature rise has many bad effects on the integrated circuit. The carrier mobility decreases, the on-current of the transistor decreases, and the resistance component of the metal wiring increases, so that the wiring delay increases. Since the threshold voltage of the MOSFET is lowered and the off-current is increased, the power consumption during standby is increased. Also, reliability is reduced in many respects.

In the conventional integrated circuit having no SOI structure, the heat generated in the transistor region mainly escapes through the semiconductor substrate to the package in contact with the back surface of the chip. Since the semiconductor substrate, for example, silicon is very easy to transfer heat, the generated heat can be quickly released to the package.

However, in the conventional SOI integrated circuit,
A thick (for example, several microns) insulating film or insulating layer exists between the transistor region and the semiconductor substrate. Since it is difficult for the insulating material, such as silicon oxide, to transfer heat, the generated heat cannot quickly escape to the package and the temperature rises sharply.

[0012]

A feature of the present invention is that an insulator layer provided on a semiconductor substrate, a semiconductor layer provided on the insulator layer to form a semiconductor element such as a transistor, and the semiconductor layer. An insulating film provided on a layer, a contact hole formed in the insulating film, and an electrode conductor film filling the contact hole and connected to a predetermined portion of the semiconductor element formed in the semiconductor layer In the semiconductor integrated circuit, the contact hole reaches the insulator layer below the semiconductor layer, and the electrode conductor film is in contact with the insulator layer in the semiconductor integrated circuit. It is preferable that the contact hole enter the inside of the insulator layer and the side surface and the bottom surface of the electrode conductor film are in contact with the insulator layer.

Further, in the invention, the contact hole penetrates the insulating layer and enters the inside of the semiconductor substrate,
The side surface of the electrode conductor film may contact the insulator layer and the semiconductor substrate, and the bottom surface may contact the semiconductor substrate. In this case, the semiconductor substrate has, for example, an impurity concentration of 1 ×.
It is preferably an N-type silicon substrate of 10 ¹⁷ cm ⁻³ or less, and the electrode conductor film forms a Schottky junction with the semiconductor substrate.

[0014]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view for explaining a first embodiment of the present invention.

An insulator layer 11 is formed on the silicon semiconductor substrate 10.
Is provided, and the silicon semiconductor layer 12 is further provided thereon. Source to a part of this silicon semiconductor layer,
A high-concentration diffusion layer 13 to be a drain region is formed, and constitutes a MOSFET, which is a semiconductor element, together with the gate electrode 14 on the gate insulating film 20. The entire MOSFET is covered with the silicon oxide film 15, and the silicon oxide film 15, the high-concentration diffusion layer 13, and a part of the insulator layer 11 in the contact hole 22 are removed to form an electrode conductor film 16 such as W (tungsten). The side surface and the bottom surface are buried and are in contact with the insulator layer 11, and the AL (aluminum) film 17 is connected to the upper surface of the electrode conductor film 16 to perform interconnection.

When the present embodiment is applied to a device having a gate length of about half micron, it is appropriate that the thickness of the silicon semiconductor layer 12 is 100 nm or less. The thickness of the insulator layer 11 is, for example, about 2.0 μm when oxygen atoms are ion-implanted into the silicon substrate 10. The thinner the remaining film of the insulating layer 11 in the contact hole portion is, the better. However, it is appropriate to set it to about 0.5 μm in consideration of the variation in film thickness and etching.

In the semiconductor integrated circuit having the SOI structure of the present invention, heat generated in the transistor region can be easily released to the silicon substrate through the contact hole portion. Compared with the conventional structure, the thickness of the insulating layer under the contact hole is ¼, so that the thermal resistance can also be made ¼.

FIG. 2 is a sectional view for explaining the second embodiment of the present invention. The contact hole 23 penetrates through the insulating layer 11 and reaches the silicon substrate 10. The side surface of the electrode conductor film 18 is in contact with the insulating layer 11 and the silicon substrate 10, and the bottom surface is in contact with the silicon substrate 10. If N-type silicon having an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or less is used as the silicon substrate, a good Schottky junction can be formed with the electrode conductor film 18. Therefore, if the silicon substrate 10 is set to the highest potential used in the integrated circuit, the conductor film 18 and the silicon substrate 10 can be electrically insulated. The silicon substrate 1
When P-type silicon is used for 0, it is set to the lowest potential used in the integrated circuit.

On the other hand, the electrode conductor film 18 and the silicon substrate 1
Since it is in direct contact with 0, the thermal resistance can be made extremely low. Some leakage current occurs at the Schottky junction, but this is not a problem unless it is used for low power consumption.

Since W (tungsten) reacts relatively easily with silicon, it is preferable to sandwich Ti (titanium) or TiN (titanium nitride) between the electrode conductor film 18 without using a single W (tungsten) layer. ..

The MOSFET of the above embodiment may be either N-channel type or P-channel type. The same applies to the case where an active element such as an NPN type or PNP type bipolar transistor or a passive element such as a resistor is formed as a semiconductor element.

[0022]

As described above, according to the present invention, the heat generated in the transistor region can be easily released to the semiconductor substrate through the contact, so that the thermal resistance substantially equal to that of the conventional integrated circuit having no SOI structure can be achieved. it can.

[Brief description of drawings]

FIG. 1 is a sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view for explaining a second embodiment of the present invention.

FIG. 3 is a sectional view for explaining a conventional integrated circuit having an SOI structure.

[Explanation of symbols]

 10 Silicon Substrate 11 Insulator Layer 12 Silicon Layer 13 High Concentration Diffusion Layer 14 Gate Electrode 15 Silicon Oxide Film 16, 18, 20 Electrode Conductor Film 17 AL Wiring Film 20 Gate Insulation Film 21, 22, 23 Contact Hole

Claims (5)

[Claims] 1. An insulator layer provided on a semiconductor substrate,
A semiconductor layer provided on the insulator layer to form a semiconductor element, an insulating film provided on the semiconductor layer, a contact hole formed in the insulating film, and the semiconductor layer filled in the contact hole. A semiconductor integrated circuit having an electrode conductor film connected to a predetermined portion of the semiconductor element, the contact hole reaching the insulator layer below the semiconductor layer, where the electrode conductor film is the insulator layer. A semiconductor integrated circuit characterized by being in contact with a semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the contact hole enters the inside of the insulator layer, and the side surface and the bottom surface of the electrode conductor film are in contact with the insulator layer. 3. The contact hole penetrates the insulating layer and enters the inside of the semiconductor substrate, the side surface of the electrode conductor film contacts the insulating layer and the semiconductor substrate, and the bottom surface contacts the semiconductor substrate. The semiconductor integrated circuit according to claim 1, further comprising: 4. The electrode conductor film forms a Schottky junction with the semiconductor substrate.
The semiconductor integrated circuit according to 1. 5. The semiconductor substrate has an impurity concentration of 1 × 10.
The semiconductor integrated circuit according to claim 4, wherein the semiconductor integrated circuit is an N-type silicon substrate of ¹⁷ cm ^-3 or less.