JP2509173B2 - Method of manufacturing semiconductor integrated circuit device having complementary MISFET - Google Patents
Method of manufacturing semiconductor integrated circuit device having complementary MISFETInfo
- Publication number
- JP2509173B2 JP2509173B2 JP60021673A JP2167385A JP2509173B2 JP 2509173 B2 JP2509173 B2 JP 2509173B2 JP 60021673 A JP60021673 A JP 60021673A JP 2167385 A JP2167385 A JP 2167385A JP 2509173 B2 JP2509173 B2 JP 2509173B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor region
- region
- semiconductor
- main surface
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Description
【発明の詳細な説明】 ［技術分野］ 本発明は、半導体集積回路装置に関するものであり、
特に、半導体領域と導電層との電気的な接続部を有する
半導体集積回路装置に適用して有効な技術に関するもの
である。TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit device,
In particular, the present invention relates to a technique effective when applied to a semiconductor integrated circuit device having an electrical connection portion between a semiconductor region and a conductive layer.
［背景技術］ MISFETのソース領域又はドレイン領域として使用され
る半導体領域は、チャネル形成領域側への拡散を抑制
し、短チャネル化を図るために、接合深さを浅くする傾
向にある。この半導体領域には、半導体集積回路装置の
動作速度の高速化を図るために、低抵抗値のアルミニウ
ム膜が接続されている。[Background Art] A semiconductor region used as a source region or a drain region of a MISFET tends to have a shallow junction depth in order to suppress diffusion toward the channel formation region side and shorten the channel. An aluminum film having a low resistance value is connected to this semiconductor region in order to increase the operating speed of the semiconductor integrated circuit device.
しかしながら、接合深さの浅い半導体領域は、オーミ
ック性を良くする熱処理工程のために、シリコン−アル
ミニウム合金の形成、所謂、アルミスパイクでpn接合部
が破壊され易い。However, in the semiconductor region having a shallow junction depth, the pn junction is easily destroyed by the formation of a silicon-aluminum alloy, so-called aluminum spike, due to the heat treatment process for improving the ohmic property.
そこで、前記半導体領域は、アルミニウム膜との接続
部分の接合深さを深くし、pn接合部にアルミスパイクが
到達しないように構成されている。ｐ型の半導体領域
は、その不純物の拡散速度がｎ型の不純物に比べて速い
ので、アルミスパイクによるpn接合部の破壊が極めて少
ない。このため、接合深さの深い部分を有する半導体領
域は、ｎ型の半導体領域に適用されている。Therefore, the semiconductor region is configured so that the junction depth of the connection portion with the aluminum film is deepened so that the aluminum spike does not reach the pn junction. In the p-type semiconductor region, the diffusion speed of the impurities is higher than that of the n-type impurities, so that the pn junction portion is extremely less broken by the aluminum spike. Therefore, the semiconductor region having the deep junction depth is applied to the n-type semiconductor region.
接合深さの深い部分を有するｎ型の半導体領域は、半
導体領域の上部の層間絶縁膜に形成される接続孔を通し
てｎ型の不純物が導入され、該不純物に引き伸し拡散を
施して形成されている。The n-type semiconductor region having a portion with a deep junction depth is formed by introducing an n-type impurity through a connection hole formed in an interlayer insulating film above the semiconductor region and stretching and diffusing the impurity. ing.
しかしながら、相補型のMISFETを構成する場合に、ｎ
型の不純物がその引き伸し拡散工程中に外部雰囲気中に
拡散し、該不純物が接続孔を通してｐ型の半導体領域の
主面部に拡散される。これによって、その不純物濃度が
低下するので、ｐ型の半導体領域とアルミニウム膜との
接続部分における抵抗値が400〜500［Ω／μm2］程度に
増大してしまう。このため、本発明者は、半導体集積回
路装置の動作速度の高速化を図ることができないという
問題点を見出した。However, when configuring a complementary MISFET, n
The type impurities diffuse into the external atmosphere during the stretching diffusion process, and the impurities diffuse into the main surface portion of the p-type semiconductor region through the contact holes. As a result, the impurity concentration is lowered, and the resistance value at the connecting portion between the p-type semiconductor region and the aluminum film is increased to about 400 to 500 [Ω / μm 2 ]. Therefore, the present inventor has found a problem that the operating speed of the semiconductor integrated circuit device cannot be increased.
なお、アルミスパイクを防止する技術は、例えば、日
経マグロウヒル社発行「日経エレクトロニクス別冊マイ
クロデバイセズ」1983年８月23日号、p122に記載されて
いる。The technique for preventing aluminum spikes is described, for example, in Nikkei McGraw-Hill's "Nikkei Electronics Separate Volume Micro Devices", August 23, 1983, p122.
［発明の目的］ 本発明の目的は、半導体領域と導電層の接続部におけ
る抵抗値を低減し、半導体集積回路装置の動作速度の高
速化を図ることが可能な技術を提供することにある。[Object of the Invention] An object of the present invention is to provide a technique capable of reducing the resistance value in the connection portion between the semiconductor region and the conductive layer and increasing the operating speed of the semiconductor integrated circuit device.
本発明の前記ならびにその他の目的と新規な特徴は、
本明細書の記述及び添付図面によって明らかになるであ
ろう。The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.
［発明の概要］ 本願において開示される発明のうち、代表的なものの
概要を簡単に説明すれば、下記のとおりである。[Outline of the Invention] The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.
すなわち、接合深さの深い部分を有する半導体領域と
導電層との接続部を有する半導体集積回路装置におい
て、前記接続部に拡散防止膜を形成し、接合深さの深い
部分を形成する不純物の拡散を防止する。That is, in a semiconductor integrated circuit device having a connecting portion between a semiconductor region having a deep junction depth and a conductive layer, a diffusion barrier film is formed at the connecting portion to diffuse impurities that form a deep junction depth. Prevent.
これによって、前記不純物が反対導電型の半導体領域
の主面部に拡散することを防止し、接続部における抵抗
値の増加を抑制することができるので、相補型MISFETを
有する半導体集積回路装置の動作速度の高速化を図るこ
とができる。As a result, it is possible to prevent the impurities from diffusing into the main surface portion of the semiconductor region of the opposite conductivity type and suppress an increase in the resistance value at the connection portion, so that the operating speed of the semiconductor integrated circuit device having the complementary MISFET is reduced. Can be speeded up.
以下、本発明の構成について、本発明を、相補型のMI
SFETを備えた半導体集積回路装置に適用した一実施例と
ともに説明する。The present invention will be described below with respect to the structure of the present invention by using a complementary MI.
An embodiment applied to a semiconductor integrated circuit device having an SFET will be described.
［実施例］ 第１図乃至第７図は、本発明の一実施例の製造方法を
説明するための各製造工程における半導体集積回路装置
の要部断面図である。[Embodiment] FIG. 1 to FIG. 7 are cross-sectional views of essential parts of a semiconductor integrated circuit device in respective manufacturing steps for explaining a manufacturing method of an embodiment of the present invention.
なお、実施例の全図において、同一機能を有するもの
は同一符号を付け、そのくり返しの説明は省略する。In all the drawings of the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.
まず、単結晶シリコンからなるp-型の半導体基板１を
用意する。この半導体基板１の所定の主面部にn-型のウ
エル領域２を形成する。First, a p − type semiconductor substrate 1 made of single crystal silicon is prepared. An n − type well region 2 is formed on a predetermined main surface portion of the semiconductor substrate 1.
そして、半導体素子形成領域以外の半導体基板１及び
ウエル領域２の主面上部に、シリコンの選択的な熱酸化
技術によって、フィールド絶縁膜３を形成する。該フィ
ールド絶縁膜３の形成と略同一製造工程によって、その
下部の半導体基板１の主面部に、ｐ型のチャネルストッ
パ領域４を形成する。前記フィールド絶縁膜３及びチャ
ネルストッパ領域４は、半導体素子間を電気的に分離す
るように構成される。Then, a field insulating film 3 is formed on the main surfaces of the semiconductor substrate 1 and the well region 2 other than the semiconductor element forming region by a selective thermal oxidation technique of silicon. The p-type channel stopper region 4 is formed in the main surface portion of the semiconductor substrate 1 thereunder by substantially the same manufacturing process as the formation of the field insulating film 3. The field insulating film 3 and the channel stopper region 4 are configured to electrically isolate the semiconductor elements.
この後、第１図に示すように、半導体素子形成領域の
半導体基板１及びウエル領域２の主面上部に、絶縁膜５
を形成する。該絶縁膜５は、主として、MISFETのゲート
絶縁膜を構成するようになっており、例えば、熱酸化技
術によって形成される酸化シリコン膜を用いる。After that, as shown in FIG. 1, the insulating film 5 is formed on the upper surfaces of the semiconductor substrate 1 and the well region 2 in the semiconductor element forming region.
To form. The insulating film 5 mainly constitutes the gate insulating film of the MISFET, and for example, a silicon oxide film formed by a thermal oxidation technique is used.
第１図に示す絶縁膜５を形成する工程の後に、絶縁膜
５の所定の上部に導電層６を形成する。該導電層６は、
主として、MISFETのゲート電極を構成するようになって
おり、例えば、CVD技術によって形成される多結晶シリ
コン膜を用いる。該導電層６は、製造工程における第１
層目の導電層形成工程によって形成される。After the step of forming the insulating film 5 shown in FIG. 1, a conductive layer 6 is formed on a predetermined upper portion of the insulating film 5. The conductive layer 6 is
The gate electrode of the MISFET is mainly configured, and for example, a polycrystalline silicon film formed by the CVD technique is used. The conductive layer 6 is the first in the manufacturing process.
It is formed by the conductive layer forming step of the second layer.
また、導電層６は、高融点金属膜（Mo,Ta,Ti,W）、シ
リサイド膜（MoSi2，TaSi2，WSi2）又はその組合せ膜に
よって形成してもよい。The conductive layer 6 may be formed of a refractory metal film (Mo, Ta, Ti, W), a silicide film (MoSi 2 , TaSi 2 , WSi 2 ) or a combination film thereof.
そして、第２図に示すように、導電層６の両側部の半
導体基板１の主面部にn+型の半導体領域７を形成し、導
電層６の両側部のウエル領域２の主面部に、p+型の半導
体領域８を形成する。半導体領域7,8は、主として、MIS
FETのソース領域又はドレイン領域を構成するようにな
っている。Then, as shown in FIG. 2, n + type semiconductor regions 7 are formed on the main surface portions of the semiconductor substrate 1 on both sides of the conductive layer 6, and on the main surface portions of the well regions 2 on both sides of the conductive layer 6, A p + type semiconductor region 8 is formed. The semiconductor regions 7 and 8 are mainly MIS
It constitutes the source region or drain region of the FET.
半導体領域7,8は、例えば、イオン打込み技術によっ
て所定の不純物を導入し、該導入された不純物に引き伸
し拡散を施して形成する。半導体領域７は、例えば、0.
2［μｍ］程度の接合深さで形成し、半導体領域８は、
例えば、0.4［μｍ］程度の接合深さで形成する。The semiconductor regions 7 and 8 are formed by, for example, introducing a predetermined impurity by an ion implantation technique and stretching and diffusing the introduced impurity. The semiconductor region 7 has, for example, 0.
The semiconductor region 8 is formed with a junction depth of about 2 [μm].
For example, the junction depth is about 0.4 [μm].
ｎチャンネルMISFETQnは、主として、半導体基板１、
絶縁膜５、導電層６及び一対の半導体領域７によって略
構成されている。The n-channel MISFETQn is mainly composed of the semiconductor substrate 1,
The insulating film 5, the conductive layer 6, and the pair of semiconductor regions 7 are substantially formed.
ｐチャネルMISFETQpは、主として、ウエル領域２、絶
縁膜５、導電層６及び一対の半導体領域８によって構成
されている。The p-channel MISFETQp is mainly composed of the well region 2, the insulating film 5, the conductive layer 6 and the pair of semiconductor regions 8.
第２図に示す半導体領域7,8を形成する工程の後に、
第３図に示すように、MISFETQn,Qp等の半導体素子を覆
うように絶縁膜９を形成する。After the step of forming the semiconductor regions 7 and 8 shown in FIG.
As shown in FIG. 3, an insulating film 9 is formed so as to cover semiconductor elements such as MISFETs Qn and Qp.
絶縁膜９は、主として、半導体素子とその上部に形成
される導電層との電気的な分離をするように構成されて
いる。絶縁膜９は、例えば、CVD技術で形成した酸化シ
リコン膜を用い、その膜厚を600［nm］程度に形成す
る。The insulating film 9 is mainly configured to electrically separate the semiconductor element and the conductive layer formed on the semiconductor element. As the insulating film 9, for example, a silicon oxide film formed by the CVD technique is used, and the film thickness is formed to about 600 [nm].
第３図に示す絶縁膜９を形成する工程の後に、半導体
領域7,8の所定の上部の絶縁膜5,9を除去し、第４図に示
すように、接続孔10を形成する。接続孔10は、フォトレ
ジスト膜等のエッチング用マスクを用い、例えば、異方
性エッチング技術で形成する。After the step of forming the insulating film 9 shown in FIG. 3, the insulating films 5 and 9 on the predetermined upper portions of the semiconductor regions 7 and 8 are removed, and the connection hole 10 is formed as shown in FIG. The connection hole 10 is formed by, for example, an anisotropic etching technique using an etching mask such as a photoresist film.
第４図に示す接続孔10を形成する工程の後に、第５図
に示すように、接続孔10部分を半導体領域7,8の主面上
部に、拡散防止膜11を形成する。また、拡散防止膜11
は、接続孔10を形成する工程において、絶縁膜5,9を除
去する際にその一部を残すことにより形成してもよい。After the step of forming the connection hole 10 shown in FIG. 4, as shown in FIG. 5, a diffusion prevention film 11 is formed on the connection hole 10 portion above the main surfaces of the semiconductor regions 7 and 8. In addition, the diffusion prevention film 11
May be formed by leaving a part of the insulating films 5 and 9 when the insulating films 5 and 9 are removed in the step of forming the connection hole 10.
拡散防止膜11は、半導体領域７に接合深さの深い部分
を形成するために導入される不純物が、その引き伸し拡
散工程中に外部雰囲気中に拡散しないようにするための
ものである。また、拡散防止膜11は、外部雰囲気中に拡
散する不純物が半導体領域８の主面部に拡散しないよう
にするためのものである。The diffusion prevention film 11 is for preventing impurities introduced to form a portion having a deep junction depth in the semiconductor region 7 from diffusing into the external atmosphere during the stretching diffusion process. The diffusion prevention film 11 is for preventing impurities that diffuse in the external atmosphere from diffusing into the main surface portion of the semiconductor region 8.
また、拡散防止膜11は、前記不純物の導入による半導
体領域７の主面部のダメージを抑制するようになってい
る。Further, the diffusion prevention film 11 is adapted to suppress damage to the main surface portion of the semiconductor region 7 due to the introduction of the impurities.
拡散防止膜11は、例えば、900［℃］程度の温度と20
［min］程度の時間の熱酸化技術を用い、その膜厚を10
［nm］程度で形成する。The diffusion prevention film 11 has a temperature of about 900 [° C.] and a temperature of about 20 ° C., for example.
Using thermal oxidation technology for a time of about [min], reduce the film thickness to 10
It is formed in the order of [nm].
また、拡散防止膜11は、例えば、CVD技術で形成した
酸化シリコン膜、窒化シリン膜等で形成してもよい。Further, the diffusion prevention film 11 may be formed of, for example, a silicon oxide film formed by a CVD technique, a silicon nitride film, or the like.
第５図に示す拡散防止膜11を形成する工程の後に、接
合深さの深い部分を形成するために、拡散防止膜11を通
して半導体領域７の主面部のみにｎ型の不純物を導入す
る。該不純物は、例えば、５×1015［atoms/cm2］程度
の不純物濃度のリンイオンを50［KeV］程度のエネルギ
のイオン打込み技術で導入すればよい。After the step of forming the diffusion prevention film 11 shown in FIG. 5, n-type impurities are introduced only into the main surface portion of the semiconductor region 7 through the diffusion prevention film 11 in order to form a portion having a deep junction depth. For the impurities, for example, phosphorus ions having an impurity concentration of about 5 × 10 15 [atoms / cm 2 ] may be introduced by an ion implantation technique with an energy of about 50 [KeV].
この不純物は、拡散防止膜11を通して導入しているの
で、導入による半導体領域７の主面部のダメージを抑制
することができる。Since this impurity is introduced through the diffusion prevention film 11, it is possible to suppress damage to the main surface portion of the semiconductor region 7 due to the introduction.
この後、前記導入された不純物に引き伸し拡散を施
し、第６図に示すように、半導体領域７と同一導電型で
電気的に接続され、それによりも接合深さの深いn+型の
半導体領域12を形成する。半導体領域12は、MISFETQnの
ソース領域又はドレイン領域の一部として使用されるも
ので、アルミスパイクによるpn接合部の破壊を抑制する
ためのものである。半導体領域12は、例えば、0.4〜0.5
［μｍ］程度の接合深さで形成する。After that, the introduced impurities are stretched and diffused, and as shown in FIG. 6, they are electrically connected to the semiconductor region 7 with the same conductivity type, and thereby, the n + type with a deep junction depth is also formed. A semiconductor region 12 is formed. The semiconductor region 12 is used as a part of the source region or the drain region of the MISFET Qn, and is for suppressing the destruction of the pn junction portion due to the aluminum spike. The semiconductor region 12 is, for example, 0.4 to 0.5.
The junction depth is about [μm].
前記半導体領域12は、例えば、950［℃］程度の温度
と20［min］程度の時間の引き伸し拡散によって形成す
る。The semiconductor region 12 is formed by stretch diffusion at a temperature of about 950 [° C.] and a time of about 20 [min], for example.
そして、半導体領域12を形成するｎ型の不純物は、拡
散防止膜11が設けられているので、引き伸し拡散工程中
に半導体領域７部分から外部雰囲気中に拡散することを
防止できる。さらに、たとえ外部雰囲気中にｎ型の不純
物が拡散しても、拡散防止膜11が設けられているので、
接続孔10を通して半導体領域８の主面部にそれが拡散す
ることを防止できる。すなわち、接続孔10部分における
半導体領域８の主面部の不純物濃度の低下を抑制し、ア
ルミニウム膜との接続部の抵抗値を例えば30［Ω／μ
m2］程度の小さな値にすることができる。これによっ
て、半導体集積回路装置の全体の配線抵抗値を低減する
ことができるので、動作速度の高速化を図ることができ
る。Since the diffusion prevention film 11 is provided for the n-type impurities forming the semiconductor region 12, it can be prevented from diffusing into the external atmosphere from the semiconductor region 7 portion during the stretching diffusion process. Further, even if n-type impurities are diffused in the external atmosphere, the diffusion prevention film 11 is provided,
It can be prevented from diffusing into the main surface portion of the semiconductor region 8 through the connection hole 10. That is, a decrease in the impurity concentration of the main surface portion of the semiconductor region 8 in the connection hole 10 portion is suppressed, and the resistance value of the connection portion with the aluminum film is, for example, 30 [Ω / μ.
m 2 ]. As a result, the wiring resistance value of the entire semiconductor integrated circuit device can be reduced, so that the operating speed can be increased.
第６図に示す半導体領域12を形成した工程の後に、拡
散防止膜11を除去する。After the step of forming the semiconductor region 12 shown in FIG. 6, the diffusion prevention film 11 is removed.
この後、第７図に示すように、接続孔10を通して半導
体領域7,8と電気的に接続するように、絶縁膜９の上部
に導電層13を形成する。導電層13は、例えば、スパッタ
技術により形成したアルミニウム膜を用いる。この導電
層13は、製造工程における第２層目の導電層形成工程に
よって形成される。Thereafter, as shown in FIG. 7, a conductive layer 13 is formed on the insulating film 9 so as to be electrically connected to the semiconductor regions 7 and 8 through the connection hole 10. As the conductive layer 13, for example, an aluminum film formed by a sputtering technique is used. The conductive layer 13 is formed by the second conductive layer forming step in the manufacturing process.
前述したように、拡散防止膜11を形成したことによ
り、接続孔10部分における半導体領域８の主面部は、半
導体領域12を形成する不純物の拡散がなくなるので、半
導体領域８と導電層13との接続部における抵抗値を低減
することができる。As described above, since the diffusion prevention film 11 is formed, the main surface portion of the semiconductor region 8 in the connection hole 10 portion does not diffuse the impurities forming the semiconductor region 12, so that the semiconductor region 8 and the conductive layer 13 are not separated from each other. The resistance value at the connection portion can be reduced.
なお、前記実施例は、本発明を、ｎ型の半導体領域７
に接合深さが深い半導体領域12を設けた例に適用した
が、ｐ型の半導体領域８に接合深さの深い半導体領域を
設けた例に適用してもよい。In addition, the above-mentioned embodiment applies the present invention to the n-type semiconductor region 7.
Although it is applied to the example in which the semiconductor region 12 having a deep junction depth is provided in the above, it may be applied to an example in which the semiconductor region having a deep junction depth is provided in the p-type semiconductor region 8.
［効果］ 以上説明したように、本願において開示された新規な
技術によれば、以下に述べる効果を得ることができる。[Effects] As described above, according to the novel technology disclosed in the present application, the effects described below can be obtained.
（１）接合深さの深い部分を有する半導体領域と導電層
との接続部を有する半導体集積回路装置において、前記
接続部に拡散防止膜を形成し、接合深さの深い部分を形
成する不純物の拡散を防止することによって、前記不純
物が反対導電型の半導体領域の主面部に拡散することを
防止できるので、接続部における抵抗値の増加を抑制す
ることができる。(1) In a semiconductor integrated circuit device having a connecting portion between a semiconductor region having a deep junction depth and a conductive layer, a diffusion prevention film is formed at the connecting portion to prevent impurities forming a deep junction depth. By preventing the diffusion, it is possible to prevent the impurities from diffusing into the main surface portion of the semiconductor region of the opposite conductivity type, and thus it is possible to suppress an increase in the resistance value at the connection portion.
（２）前記（１）により、半導体集積回路装置の動作速
度の高速化を図ることができる。(2) Due to the above (1), the operating speed of the semiconductor integrated circuit device can be increased.
（３）前記（１）により、拡散防止膜を通して前記不純
物を導入するので、半導体基板又はウエル領域の主面部
のダメージを抑制することができる。(3) According to the above (1), since the impurities are introduced through the diffusion prevention film, damage to the semiconductor substrate or the main surface portion of the well region can be suppressed.
（４）前記（３）により、半導体集積回路装置の電気的
特性の劣化を抑制することができる。(4) Due to the above (3), it is possible to suppress the deterioration of the electrical characteristics of the semiconductor integrated circuit device.
以上、本発明者によってなされた発明を、前記実施例
にもとずき具体的に説明したが、本発明は、前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
において、種々変形し得ることは勿論である。The invention made by the present inventor has been specifically described above based on the above-mentioned embodiments, but the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. Of course, it can be modified.
第１図乃至第７図は、本発明の一実施例の製造方法を説
明するための各製造工程における半導体集積回路装置の
要部断面図である。 図中、7,8,12…半導体領域、９…絶縁膜、10…接続孔、
11…拡散防止膜、13…導電層である。1 to 7 are cross-sectional views of a main part of a semiconductor integrated circuit device in respective manufacturing steps for explaining a manufacturing method according to an embodiment of the present invention. In the figure, 7,8,12 ... semiconductor region, 9 ... insulating film, 10 ... connection hole,
11 ... Diffusion prevention film, 13 ... Conductive layer.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭53−115173（ＪＰ，Ａ) 特開 昭59−72759（ＪＰ，Ａ) 特開 昭59−197161（ＪＰ，Ａ) 特開 昭58−25258（ＪＰ，Ａ) 特公 昭54−24269（ＪＰ，Ｂ１) ─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-53-115173 (JP, A) JP-A-59-72759 (JP, A) JP-A-59-197161 (JP, A) JP-A-58- 25258 (JP, A) JP 54-24269 (JP, B1)
Claims (3)
及びそれと反対の第２導電型を示す領域主面とを有する
半導体基体を準備し、その第１導電型を示す領域主面及
び第２導電型を示す領域主面にゲート電極をそれぞれ形
成する工程と、 （２）該第１導電型を示す領域主面にそのゲート電極に
よって規定されるソースまたはドレイン領域となる第２
導電型の第１の半導体領域を、第２導電型を示す領域主
面にそのゲート電極によって規定されるソースまたはド
レイン領域となる第１導電型の第２の半導体領域をそれ
ぞれ形成する工程と、 （３）該第１の半導体領域、第２の半導体領域及びゲー
ト電極上部に第１の絶縁膜を形成する工程と、 （４）該第１の半導体領域面上部及び第２の半導体領域
面上部の該第１の絶縁膜を選択的に除去して半導体領域
との接続をなすための接続孔を形成する工程と、 （５）該接続孔部の第１の半導体領域及び第２の半導体
領域面部に第２の絶縁膜を設け、前記第２の半導体領域
面部をマスクで覆い、マスクされていない前記第１の半
導体領域面部の第２の絶縁膜を通して第１の半導体領域
内に第２導電型を示す不純物を導入した後に、前記マス
クを除去し、導入した不純物を熱拡散することにより第
１の半導体領域よりも接合深さの深い第３の半導体領域
を形成する工程と、しかる後 （６）前記接続孔部内に位置した前記第２の絶縁膜を除
去することにより、接続孔の大きさに対応する前記第３
の半導体領域表面及び第２の半導体領域表面を露出させ
る工程と、 （７）前記接続孔部に埋め込まれ、前記第３の半導体領
域表面及び第２の半導体領域表面に接する導電層をそれ
ぞれ形成する工程と、 からなることを特徴とする相補型MISFETを有する半導体
集積回路装置の製造方法。(1) A semiconductor substrate having, on one main surface thereof, a region main surface showing a first conductivity type and an area main surface showing a second conductivity type opposite thereto is prepared, and a semiconductor substrate showing the first conductivity type is prepared. Forming a gate electrode on each of the region main surface and the region main surface exhibiting the second conductivity type; and (2) forming a source or drain region defined by the gate electrode on the region main surface exhibiting the first conductivity type. Second
Forming a first semiconductor region of a conductivity type and a second semiconductor region of a first conductivity type serving as a source or drain region defined by the gate electrode on the main surface of the region showing the second conductivity type; (3) a step of forming a first insulating film on the first semiconductor region, the second semiconductor region and the upper part of the gate electrode, (4) the first semiconductor region surface upper part and the second semiconductor region surface upper part Selectively removing the first insulating film to form a connection hole for connecting to the semiconductor region, (5) the first semiconductor region and the second semiconductor region of the connection hole portion. A second insulating film is provided on the surface portion, the second semiconductor region surface portion is covered with a mask, and the second conductive film is formed in the first semiconductor region through the second insulating film on the unmasked first semiconductor region surface portion. The mask is removed after introducing the type-indicating impurities. A step of forming a third semiconductor region having a junction depth deeper than that of the first semiconductor region by thermally diffusing the introduced impurities, and thereafter (6) the second insulation located in the connection hole portion The third film corresponding to the size of the connection hole is removed by removing the film.
Exposing the surface of the semiconductor region and the surface of the second semiconductor region, and (7) forming conductive layers that are buried in the connection hole and are in contact with the surface of the third semiconductor region and the surface of the second semiconductor region, respectively. A method of manufacturing a semiconductor integrated circuit device having a complementary MISFET, comprising:
域は、ｎ型の半導体領域であり、前記第２の半導体領域
は、ｐ型の半導体領域であることを特徴とする特許請求
の範囲第１項記載の相補型MISFETを有する半導体集積回
路装置の製造方法。2. The first semiconductor region and the third semiconductor region are n-type semiconductor regions, and the second semiconductor region is a p-type semiconductor region. A method of manufacturing a semiconductor integrated circuit device having a complementary MISFET according to claim 1.
比べて薄く構成されてなることを特徴とする特許請求の
範囲第１項記載の相補型MISFETを有する半導体集積回路
装置の製造方法。3. A semiconductor integrated circuit device having a complementary MISFET according to claim 1, wherein the second insulating film is thinner than the first insulating film. Manufacturing method.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60021673A JP2509173B2 (en) | 1985-02-08 | 1985-02-08 | Method of manufacturing semiconductor integrated circuit device having complementary MISFET |
| KR1019850008576A KR940006668B1 (en) | 1984-11-22 | 1985-11-16 | Manufacturing method of semiconductor ic device |
| EP85114857A EP0183204A3 (en) | 1984-11-22 | 1985-11-22 | Process for fabricating semiconductor integrated circuit devices |
| CN85109742A CN85109742B (en) | 1984-11-22 | 1985-11-22 | Method of producing semiconductor integrated circuit devices |
| US06/800,954 US4734383A (en) | 1984-11-22 | 1985-11-22 | Fabricating semiconductor devices to prevent alloy spiking |
| US07/351,323 US5055420A (en) | 1984-11-22 | 1989-05-09 | Process for fabricating semiconductor integrated circuit devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60021673A JP2509173B2 (en) | 1985-02-08 | 1985-02-08 | Method of manufacturing semiconductor integrated circuit device having complementary MISFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61182254A JPS61182254A (en) | 1986-08-14 |
| JP2509173B2 true JP2509173B2 (en) | 1996-06-19 |
Family
ID=12061565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60021673A Expired - Lifetime JP2509173B2 (en) | 1984-11-22 | 1985-02-08 | Method of manufacturing semiconductor integrated circuit device having complementary MISFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2509173B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100320436B1 (en) * | 1999-12-03 | 2002-01-16 | 박종섭 | Method for manufacturing mosfet |
| JP4876193B1 (en) * | 2011-08-08 | 2012-02-15 | 渡 高橋 | Pollen mating machine |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53115173A (en) * | 1977-03-18 | 1978-10-07 | Hitachi Ltd | Production of semiconductor device |
| JPS5424269A (en) * | 1977-07-26 | 1979-02-23 | Hitachi Ltd | Catalytic reactor |
| JPS5825258A (en) * | 1981-08-07 | 1983-02-15 | Mitsubishi Electric Corp | Complementary mos ic |
| JPS5972759A (en) * | 1982-10-20 | 1984-04-24 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS6046804B2 (en) * | 1983-04-22 | 1985-10-18 | 株式会社東芝 | Manufacturing method of semiconductor device |
-
1985
- 1985-02-08 JP JP60021673A patent/JP2509173B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61182254A (en) | 1986-08-14 |
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