JPH1041503A - Mos transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS transistor having the resistance to the high voltage noise, etc., coming from outside by a method in which the second conductive type region, having deep junction depth, is provided in a source/drain region including the contact part between a source electrode and a drain electrode. SOLUTION: An n-type source region 5 and an n-type drain region 6 are formed on the surface layer of a p-type substrate 1, a gate electrode layer 4 is provided between them through a gate oxide film 3, and an auxiliary region 15, having the conductive type same as the n-type source region 5 and the n-type drain region 6 and also having the junction depth deeper than them, is formed on the part directly under source and drain electrodes 9 and 10. As a result, the contact part of the source electrode 9 is instantaneously heated up by high voltage noise, a fused part 14 is generated between the electrode and the junction, but as the fused part 14 stays in the auxiliary region 15, the junction between the drain region 10 and the p-type silicon substrate 1 is not short-circuited. Accordingly, even when a fused part is generated by surge voltage, the junction is not short-circuited, and the MOS transistor has high resistivity to the noise, etc., of the high voltage applied from outside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS field effect transistor (hereinafter referred to as a MOS transistor), and more particularly to a MOS transistor integrated as an input / output stage transistor in a semiconductor integrated circuit and a method of manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor integrated circuit (hereinafter, referred to as an IC) in which a large number of semiconductor elements such as transistors are integrated, particularly,
M with integrated MOS transistor of oxide film-semiconductor structure
High integration of OS type integrated circuits (hereinafter referred to as MOSIC),
The progress of miniaturization is remarkable.

FIGS. 6A to 6C show general MOSICs.
FIG. 14 is a cross-sectional view of a MOS transistor portion in the order of steps showing the method for fabricating the semiconductor device. A pattern of a hard-to-oxidize film is formed on the surface of a p-type silicon substrate 1 and oxidized to form a selective oxide film 2. Next, a thin gate oxide film 3 is formed on the surface of the p-type silicon substrate 1 from which the pattern of the hard-to-oxidize film has been removed, and polycrystalline silicon is deposited on the gate oxide film 3 to form a pattern. This is used as the gate electrode layer 4 (FIG. 6A).

Using the selective oxide film 2 and the gate electrode layer 4 as a mask, arsenic and boron are ion-implanted and heat-treated to form an n source region 5, an n drain region 6 and ap ⁺ fixed region 7, and then a CVD method. To deposit an interlayer insulating film 8 [FIG. After providing a contact hole in the interlayer insulating film 8 by photoetching, an aluminum alloy is sputter-deposited and patterned to form an n-source region 5, n.
Drain region 6, p ⁺ fixed region 7, and gate electrode layer 4
A source electrode 9, a drain electrode 10,
A substrate fixed electrode 11 and a gate electrode 12 are provided, and finally a protective film 13 is deposited [FIG.

FIGS. 6A to 6C show an n-channel MOS.
The method of manufacturing the transistor has been described.
If the conductivity type of the impurity to be introduced into the S transistor is changed,
It can be formed in a similar manner.

[0006]

In the case of ICs and MOSICs, externally, ICs are mounted on input signal lines and output signal lines.
Integrated as an input / output transistor due to high voltage noise or surge voltage such as static electricity invading
In order to prevent the OS transistor from being destroyed, a protection element such as a resistor or a diode is usually provided between the input / output pad and the input / output stage transistor.

However, in recent years, with the progress of high integration and miniaturization of MOSIC, the junction depth of source / drain regions has become shallower than before, and even if the above-described protection element is provided, external In some cases, destruction was thought to be caused by high voltage noise or the like such as static electricity invading from the outside. FIG.
7A is a plan view of a broken MOS transistor in a MOSIC on the surface of a silicon substrate, and FIG. 7B is a cross-sectional view thereof.

In the MOS transistor shown in the figure, an n source region 5 and an n drain region 6 are formed in a surface layer of a p-type substrate 1,
On the right side of the figure, p for fixing the potential of the p-type silicon substrate 1 is shown.
^{+ A} fixed region 7 is formed. The thin lines represent the contact portions of the electrodes provided on each region. FIG. 7 (b)
As shown in the cross-sectional view of FIG. 3, a gate oxide film 3 is formed on the surface of the silicon substrate between n source region 5 and n drain region 6.
Channel-type MO provided with a gate electrode layer 4 through
It is an S transistor.

The destruction occurs immediately below the drain electrode 10, and a melted portion 14 is generated, and the pn junction between the n-drain region 6 and the p-type substrate 1 is short-circuited. n source region 5
In some cases, the pn junction between the semiconductor device and the p-type substrate 1 is short-circuited. Such destruction is caused by high voltage noise such as static electricity applied from the outside, the contact portion of the source electrode 4 or the drain electrode 5 of the MOS transistor is instantaneously heated to a high temperature, and the gap between the electrode and the junction is melted. It is considered that the junction was short-circuited.

In view of the above problems, an object of the present invention is to provide a semiconductor device which is resistant to external high-voltage noise and the like, and a method of manufacturing the same.

[0011]

According to the present invention, there is provided a MOS transistor having a source region and a drain region of a second conductivity type formed on a surface side of a semiconductor layer of a first conductivity type. A second conductivity type auxiliary region having a junction depth deeper than the source region and the drain region formed in the source region and the drain region so as to include a source electrode provided in contact with the drain region and a contact portion with the drain electrode. Shall be provided.

In a MOS transistor having a second conductivity type offset region formed to include at least one of a source region and a drain region and having a junction depth deeper than the source region and the drain region, It has a second conductivity type auxiliary region having a junction depth deeper than the region. By doing so, since there is a second conductivity type auxiliary region having a deep junction depth, even if a fused portion is generated due to a surge voltage, there is almost no possibility that the junction will be short-circuited, and the electrostatic breakdown resistance will be improved. .

As a method of manufacturing the MOS transistor as described above, the auxiliary region of the second conductivity type is formed prior to the formation of the source and drain regions of the second conductivity type. It is convenient to form the diffusion region having a deeper junction depth first, because the heat treatment time can be used later. Conversely, if a diffusion region having a shallower junction depth is formed first, the junction depth may be increased more than necessary due to the subsequent heat treatment time.

In particular, a guard ring having the second conductivity type is provided, and the auxiliary region of the second conductivity type is formed simultaneously with the guard ring of the second conductivity type. In this case, a step for forming the second conductivity type auxiliary region is not particularly necessary. After the formation of the source and drain regions of the second conductivity type, a contact hole for electrode connection is formed in the insulating film on the semiconductor substrate, and 1 M of the second conductivity type impurity is passed through the contact hole.
The second conductivity type auxiliary region may be formed by ion implantation at an acceleration voltage of eV or more.

This eliminates the need for heat treatment for forming the second conductivity type auxiliary region having a large junction depth, and can reduce the number of steps.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below based on examples. Embodiment 1 FIG. 1A shows a MOS transistor according to a first embodiment of the present invention.
FIG. 1B is a plan view of one MOS transistor portion of the IC on the surface of the silicon substrate, and FIG. 1B is a cross-sectional view taken along the line AA ′. This MOSIC is an n-channel type M
A CMOS IC including an OS transistor and a p-channel MOS transistor may be used.

In FIG. 1A, reference numerals 5 and 6 denote n, respectively.
A source region and an n-drain region. On the right side of the figure, p
A p ⁺ diffusion region 7 for fixing the potential of the mold substrate 1 is provided. The dotted lines show the gate electrode layer 4, the n source region 5, the n drain region 6, and the p ⁺ fixed region 7, and the thin lines show the contact portions of the source electrode, the drain electrode and the fixed electrode. Represents. At the contact portion between the source electrode and the drain electrode in the n source region 5 and the n drain region 6, an n auxiliary region 15 larger than the contact portion is formed.

The cross section shown in FIG. 1B is almost the same as that of a conventional general MOS transistor, in which an n source region 5 and an n drain region 6 are formed in a surface layer of a p-type substrate 1, and a substrate between them is formed. A gate electrode layer 4 of polycrystalline silicon is provided on the surface of the semiconductor device 1 via a gate oxide film 3. 9, 1
0, 11, and 12 represent a source electrode, a drain electrode,
A fixed electrode and a gate electrode. The conventional MO shown in FIG.
The difference from the S transistor is that the n auxiliary region 15 is formed in the substrate surface layer immediately below the source electrode 9 and the drain electrode 10. The n auxiliary region 15 is of the same conductivity type as the n source region 5 and the n drain region 6, and has a junction depth of 1 μm and is formed deeper than 0.3 μm of the n source region 5 and the n drain region 6.

FIG. 1C shows an MO according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view of a MOS transistor portion after applying high-voltage noise to an SIC. The contact portion of the source electrode 9 of the MOS transistor is instantaneously heated to a high temperature by high-voltage noise such as static electricity applied from the outside, and a fused portion 14 in which the electrode and the junction are fused is seen. , N drain region 1
The junction between 0 and the p-type silicon substrate 1 is not short-circuited.

The MOS transistor of the first embodiment is replaced by C = 2
In the electrostatic breakdown resistance test at 00 [μF] and R = 0 [Ω], the breakdown resistance was improved from about 300 [V] to about 500 [V] in the past. As described above, just below the source electrode 9 and the drain electrode 10, n
By forming the n-type auxiliary region 15 having the same conductivity type as the source region 5 and the n-drain region 6 and having a deeper junction depth, a highly reliable semiconductor device resistant to external high-voltage noise and the like. It can be.

FIGS. 2A to 2D show M of the embodiment of the present invention.
FIG. 6 is a cross-sectional view of a MOS transistor portion in a process order, showing a method for manufacturing an OSIC. A pattern of a hard-to-oxidize film is formed on the surface of a p-type silicon substrate 1 and oxidized to form a selective oxide film 2
To form Next, a gate oxide film 3 having a thickness of about 25 nm is formed on the surface of the p-type silicon substrate 1 from which the pattern of the hard-to-oxidize film has been removed, and polycrystalline silicon is deposited on the gate oxide film 3. Form a pattern to form the gate electrode layer 4
[FIG. 2A].

Next, phosphorus is selectively ion-implanted into the locations where the contact holes of the source and drain electrodes of the n-channel MOS transistor are to be formed, using a photoresist as a mask (implantation conditions: acceleration voltage 150 keV, dose 5 × 10 ¹⁴ atoms / cm ² ), followed by heat treatment (heat treatment conditions: temperature 1000 ° C., 40 minutes), and a junction depth of about 1 μm
Is formed (FIG. 2B). In a cross section (not shown), a p auxiliary region is formed by ion implantation of boron and heat treatment at a place where a contact hole of a source electrode and a drain electrode of the p-channel MOS transistor is to be formed.

Using the selective oxide film 2 and the gate electrode layer 4 as a mask, arsenic (implantation condition; acceleration voltage 90 keV, dose amount 4 × 10 ¹⁵ atoms / cm ² ) and boron are ion-implanted, and heat treatment (heat treatment condition: temperature 900 ℃, 25 minutes)
Thus, n source region 5, n drain region 6, and p ⁺ fixed region 7 are formed. Similarly, a p source region, a p drain region, and the like of a p-channel MOS transistor are formed, then PSG (phosphorus silicate glass) is deposited by a CVD method, and a reflow process (heat treatment condition; temperature 950)
C. for 15 minutes) to form an interlayer insulating film 8 [FIG. After this, the junction depth of the n source region 5 and the n drain region 6 is about 0.3 μm.

After a contact hole is formed in the interlayer insulating film 8 by photoetching, an aluminum alloy is sputter-deposited and patterned to form an n source region 5, an n drain region 6, a p ⁺ fixed region 7 and a gate electrode layer 4. A source electrode 9, a drain electrode 10, a substrate fixed electrode 11 and a gate electrode 12 which are in contact with each other are provided.
A protective film 13 of silicon nitride is deposited by the VD method [FIG.

Thus, a MOS transistor having an n auxiliary region 15 having a junction depth deeper than that of the n source region 5 and the n drain region 6 can be realized. [Embodiment 2] FIG. 3A shows a MOS transistor according to a second embodiment of the present invention.
FIG. 1B is a plan view of one MOS transistor portion of the IC on the surface of the silicon substrate, and FIG. 1B is a cross-sectional view taken along the line BB ′. This MOSIC is an n-channel type M
A CMOS IC including an OS transistor and a p-channel MOS transistor may be used.

In this example, a silicon substrate is an n-type substrate, and an n-channel MOS transistor is formed on a surface layer of a p-well laminated thereon. The n-channel type MOS transistor includes a low breakdown voltage MOS transistor and a high breakdown voltage MOS transistor, and the high breakdown voltage MOS transistor is shown in the figure. In FIG. 3A, an n source region 5 and an n drain region 6 are formed in a surface layer of a p well 17, and a gate electrode layer 4 of polycrystalline silicon is provided on a substrate surface therebetween via a gate oxide film. Have been. An n-type offset region 18 of the same conductivity type is formed outside the n-source region 5 and the n-drain region 6 to increase the breakdown voltage. Further, an n guard ring region 19 is formed between the n channel type MOS transistor and the p ⁺ fixed region 7.

FIG. 3B is a sectional view of a MOS transistor portion according to the second embodiment. An n-offset region 18 is formed in a surface layer of the p-well 17 laminated on the n-type substrate 17. n source region 5 in n offset region 18;
An n drain region 6 is formed. 9, 10, 11,
Reference numeral 12 denotes a source electrode, a drain electrode, a fixed electrode, and a gate electrode. On the substrate surface layer immediately below the source electrode 9 and the drain electrode 10, an n auxiliary region 15 including a contact portion of the electrode and having a junction depth deeper than the n source region 5, the n drain region 6, and the n offset region 18 is formed. I have. The junction depth of n auxiliary region 15 is 3 μm, and 0.3 μm of n source region.
It is deeper than 2 μm in the m and n offset regions.

FIG. 3C is a cross-sectional view of the MOS transistor portion after applying high-voltage noise to the MOSIC of the second embodiment. The contact portion of the source electrode 9 or the drain electrode 10 of the MOS transistor is instantaneously heated to a high temperature due to high voltage noise such as static electricity applied from the outside, and a fused portion 14 where the electrode and the junction are fused is seen. Since the fusion portion 14 remains in the n auxiliary region 15, the junction is not short-circuited.

As described above, immediately below the source electrode 9 and the drain electrode 10, the n source region 5, the n drain region 6, and the n
By forming the n-type auxiliary region 15 having the same conductivity type as the offset region 18 and having a deeper junction depth, a semiconductor device having resistance to external high-voltage noise or the like can be obtained. FIGS. 4A to 4D are cross-sectional views in the order of steps of a MOS transistor portion showing a method of manufacturing a MOSIC according to an embodiment of the present invention. This MOSIC has n
This is a CMOS IC including a channel type MOS transistor and a p-channel type MOS transistor.

First, boron is ion-implanted into the surface layer of the n-type substrate 16 (implantation condition; dose amount: 10 ¹² atoms / c).
m ² ), a p-well 17 is formed. Similarly, phosphorus is ion-implanted to form an n-well for a p-channel MOS transistor. Next, phosphorus is ion-implanted into the p-well 17 to selectively form the n-offset region 18 using a photoresist as a mask (implantation condition; acceleration voltage 150 ke).
V, and the dose amount is 10 ¹³ atoms / cm ² ). Subsequently, phosphorus is ion-implanted into a portion below the selective oxide film for n guard ring (implantation condition; acceleration voltage 150
keV and a dose of 5 × 10 ¹⁴ atoms / cm ² ). At this time, phosphorus is ion-implanted into the source and drain electrode contact holes of the n-channel MOSFET at the same time. Subsequent offset heat treatment (heat treatment conditions at 1150 ° C. for 120 minutes) results in a junction depth of about 2 μm.
An n offset region 18 of m and an n guard ring 19 having a junction depth of 3 μm are formed. At the same time, n offset region 1
An n auxiliary region 15 having a junction depth of 3 μm is formed in FIG. 8 (FIG. 4A). In a cross section (not shown), a p-protected region is formed at a location where a contact hole of a source electrode and a drain electrode of the p-channel MOSFET is to be formed by ion implantation of boron and heat treatment.

A pattern of a hard-to-oxidize film is formed on the surface of the p-well 17 and then oxidized to form a selective oxide film 2 to separate an element formation region. Next, a gate oxide film 3 having a thickness of about 130 nm is formed on the surface of the p-well 17 from which the pattern of the hard-to-oxidize film has been removed, and polycrystalline silicon having a thickness of about 320 nm is deposited on the gate oxide film 3. The gate electrode layer 4 is formed by depositing, patterning, and etching [FIG. When polycrystalline silicon is deposited, phosphorus is introduced so that it can be used as a conductor.

Using the selective oxide film 2 and the gate electrode layer 4 as a mask, arsenic (implantation conditions;
Acceleration voltage 90 keV, dose 4 × 10 ¹⁵ atoms / c
m ² ) and heat-treated (heat treatment conditions; temperature 90)
(0 ° C., 25 minutes) to form an n source region 5 and an n drain region 6. Similarly, p ⁺
The fixed area 7 is formed. At this time, the p-channel type MOS
A p source region, a p drain region, and the like of the transistor may be formed. Subsequently, PSG (phosphorus silicate glass) is deposited by a CVD method, and is subjected to a reflow treatment (a heat treatment condition: a temperature of 950 ° C. for 15 minutes) to form an interlayer insulating film 8 [FIG. After this, the junction depth of the n source region 5 and the n drain region 6 is about 0.3 μm.

After patterning and etching the interlayer insulating film 8 by photoetching to form a contact hole, an aluminum alloy is sputter-deposited and patterned to form an n source region 5, an n drain region 6, and ap ⁺ fixed region 7. And a source electrode 9, a drain electrode 10, a substrate fixed electrode 11, and a gate electrode 12 which are respectively in contact with the gate electrode layer 4, and finally a silicon nitride protective film 13 is deposited by a plasma CVD method [FIG. .

As described above, if the n auxiliary region 15 is formed by using phosphorus ion implantation for forming the n guard ring 19, there is no need to add a new process, and the current process can be used as it is. [Embodiment 3] FIGS. 5A to 5D are cross-sectional views of a MOS transistor portion in a process order showing another method of manufacturing a MOSIC including a MOS transistor according to Embodiment 2 of the present invention. The MOSIC is a CMOSIC including an n-channel MOSFET and a p-channel MOS transistor.

First, the p-well 1 is formed on the surface layer of the n-type substrate 16.
7 is formed by ion implantation of boron. (Injection conditions;
A dose of 10 ¹² atoms / cm ² ) If necessary, phosphorus ions are implanted to form an n-well. Next, phosphorus is ion-implanted into the surface layer of the p-well 17 using a photoresist as a mask to selectively form an n-offset region 18 (implantation condition; dose amount: 10 ¹³ atoms / cm ² ). Subsequently, phosphorus for forming the n guard ring 19 is ion-implanted into a portion below the selective oxide film (implantation conditions; acceleration voltage 150 keV, dose amount 5 × 10 ¹⁴ atoms / cm ² ). Subsequent offset heat treatment (heat treatment conditions: 1150 ° C, 1
20 minutes), an n offset region 18 having a junction depth of about 2 μm and an n guard ring 19 having a junction depth of 3 μm are formed (FIG. 5A).

Next, a pattern of a hard-to-oxidize film is formed on the surface of the p-well 17 and oxidized to form a selective oxide film 2 to separate an element formation region. Thereafter, a gate oxide film 3 having a thickness of about 130 nm is formed on the surface of the p-type silicon substrate 1 from which the pattern of the hard-to-oxidize film has been removed, and a thickness of about 320 nm is formed on the gate oxide film 3 by a low pressure CVD method. Is deposited, patterned and etched to form a gate electrode layer 4. Polycrystalline silicon is used as a conductor by introducing phosphorus during deposition.

The selective oxidation is performed in the n-offset region 18.
Arsenic is ionized using the film 2 and the gate electrode layer 4 as a mask.
Implantation (injection conditions; acceleration voltage 90 keV, dose 4 ×)
10 ^FifteenAtom / cm^Two) And heat treatment (heat treatment conditions; temperature 9)
(00 ° C., 25 minutes) to form n source region 5 and n drain region
Region 6 is formed. Similarly, boron is ion-implanted and heat-treated.
P⁺Fixed region 7, p-channel type MOS transistor
P source region, p drain region, etc.
Deposit PSG (phosphosilicate glass) by VD method,
Reflow treatment (heat treatment conditions: temperature 950 ° C, 15 minutes)
To form an interlayer insulating film 8 [FIG.

After opening contact holes for contacting the source electrode and the drain electrode of the interlayer insulating film 8 by photoetching, phosphorus is ion-implanted (injection conditions; acceleration voltage).
3 MeV, dose amount 5 × 10 ¹⁴ atoms / cm ² ), and low-temperature annealing (heat treatment condition: 800 ° C., 25 minutes) to form an n auxiliary region 15 having a junction depth deeper than the n offset region 18 only under the contact formation portion. [FIG. (C)]. The junction depth of the diffusion layer below the contact formation part is
About 3 μm. In a cross section (not shown), a p auxiliary region is formed at a location where a contact hole of a source electrode and a drain electrode of a p-channel MOSFET is to be formed by ion implantation of boron and heat treatment.

An aluminum alloy is sputter-deposited and patterned to form an n source region 5, an n drain region 6, p ⁺
A source electrode 9, a drain electrode 10, a substrate fixed electrode 11, and a gate electrode 12 are provided in contact with the fixed region 7 and the gate electrode layer 4, respectively. Finally, a silicon nitride protective film 13 is deposited by a plasma CVD method to complete a MOSIC. [FIG. (D)].

[0040]

As described above, according to the present invention, M
By including a contact portion with a source electrode and a drain electrode in a source region and a drain region of an OS transistor, and in a case where a source region, a drain region or an offset region is provided, an auxiliary region having a junction depth deeper than the offset region is provided. Even if a fused portion is generated by the surge voltage, the junction is not short-circuited, and the MOS transistor has high resistance to high-voltage noise or the like applied from the outside.

For example, as described in the embodiment,
In the electrostatic breakdown resistance test with C = 200 [μF] and R = 0 [Ω], the breakdown voltage was 300 V in the past, but improved to 500 V.

[Brief description of the drawings]

FIG. 1A is a plan view of a silicon surface of a MOS transistor according to a first embodiment of the present invention, and FIG.
(C) is a partial sectional view after applying a surge voltage.

FIGS. 2A to 2D show MOS transistors according to a first embodiment of the present invention;
Partial cross-sectional view in transistor manufacturing process order

FIG. 3A is a plan view of a silicon surface of a MOS transistor according to a second embodiment of the present invention, and FIG.
(C) is a partial sectional view after applying a surge voltage.

FIGS. 4A to 4D show MOS transistors according to a second embodiment of the present invention;
Partial cross-sectional view in transistor manufacturing process order

FIGS. 5A to 5D show MOS transistors according to a second embodiment of the present invention;
Partial cross-sectional view of another manufacturing process of a transistor

FIGS. 6A to 6C are partial cross-sectional views of another conventional MOS transistor in another manufacturing process order;

FIG. 7 is a plan view of a conventional MOS transistor on a silicon surface, and FIG. 7B is a partial cross-sectional view after a surge voltage is applied.

[Explanation of symbols]

Reference Signs List 1 p-type substrate 2 selective oxide film 3 gate oxide film 4 gate electrode layer 5 n source region 6 n drain region 7 p ⁺ fixed region 8 interlayer insulating film 9 source electrode 10 drain electrode 11 fixed electrode 12 gate electrode 13 protective film 14 melting Part 15 n auxiliary region 16 n-type substrate 17 p well 18 n offset region 19 n guard ring

Claims (5)

[Claims] An M transistor having a second conductivity type source region and a drain region formed on the surface side of a first conductivity type semiconductor layer.
In an OS transistor, a source electrode formed in contact with a source electrode and a drain electrode provided in contact with a source region and a drain region, and a junction depth larger than the source region and the drain region formed in the drain region including the contact portion. A MOS transistor having a deep second conductivity type auxiliary region. 2. An M transistor having a second conductivity type offset region formed to include at least one of a source region and a drain region and having a junction depth deeper than the source region and the drain region.
2. The MOS transistor according to claim 1, wherein the OS transistor has a second conductivity type auxiliary region having a junction depth deeper than the second conductivity type offset region. 3. A first conductivity type semiconductor layer sandwiched between a second conductivity type source region and a drain region formed on a surface side of the first conductivity type semiconductor layer and a second conductivity type source region and a drain region. A gate electrode layer provided on the surface of the via a gate insulating film, a second conductivity type source region, a drain region,
Source and drain regions formed in the source and drain regions including the source electrode, the drain electrode, and the contact portion between the source and drain electrodes provided in contact with the gate electrode layer, respectively. A method of manufacturing a MOS transistor having a second conductivity type auxiliary region having a deeper junction depth, wherein the second conductivity type auxiliary region is formed prior to the formation of the second conductivity type source region and the drain region. A method for manufacturing a MOS transistor. 4. The method of manufacturing a MOS transistor according to claim 3, further comprising a guard ring of the second conductivity type, and forming the auxiliary region of the second conductivity type simultaneously with the guard ring of the second conductivity type. 5. A first conductivity type semiconductor layer sandwiched between a second conductivity type source region and a drain region formed on a surface side of the first conductivity type semiconductor layer and a second conductivity type source region and a drain region. A gate electrode layer provided on the surface of the via a gate insulating film, a second conductivity type source region, a drain region,
Source and drain regions formed in the source and drain regions including the source electrode, the drain electrode, and the contact portion between the source and drain electrodes provided in contact with the gate electrode layer, respectively. In a method of manufacturing a MOS transistor having a second conductivity type auxiliary region having a deeper junction depth, a contact hole for electrode connection is provided in an insulating film on a semiconductor substrate after forming a second conductivity type source region and a drain region. And ion-implanting a second conductivity type impurity at an acceleration voltage of 1 MeV or more through the contact hole to form a second conductivity type auxiliary region.
A method for manufacturing an OS transistor.