JP2975083B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which isolation between elements is performed using a trench.

[Conventional technology]

FIG. 3 is a cross-sectional view of a conventional semiconductor device which performs element isolation using a trench, and shows a case where the device is an NMOS.

In the figure, 1 is a silicon substrate, 2 is a gate dielectric film, 3 is a gate electrode, 4 is a first source / drain region, 5 is a second source / drain region, 8 is an interlayer insulating film, and 9 is a wiring layer. , 11 are buried oxide layers, and 12 is an n-type inversion layer.

 Next, the operation will be described.

The silicon substrate 1 contains p-type impurities, for example, 10 ¹⁶ -10 ¹⁷ / c
m ³ and comprise, on the silicon substrate 1, a gate electrode 3 is formed through the gate dielectric film 2. On the silicon substrate 1, an n-type impurity, for example, 10 ¹⁹ to 10 ²¹
A first source / drain region 4 containing / cm ³ is formed.

When a positive voltage is applied to the gate electrode 3, n-type carriers having the same conductivity type as the first source / drain region 4 are induced under the gate dielectric film 2, and are the same as the first source / drain region 4. Because of the conductivity type, it is possible to allow a current to flow between the first source / drain regions 4 separated by the gate electrode 3, and the current flowing at this time is controlled by the voltage applied to the gate electrode 3. This is the operation principle of the MOS field effect transistor.

Further, an interlayer insulating film 8 having a part thereof opened is provided on the silicon substrate 1, and the wiring layer 9 is formed of a first source film.
It is connected to the drain region 4 or the gate electrode 3. In addition, the first having the first source / drain region 4
Next to the MOSFET A, a second MOSFET B having a second source / drain region 5 is provided.

Here, since the n-type first source / drain region 4 and the second source / drain region 5 have the same conductivity type, a p-type impurity region is required between them in order to prevent conduction between them. Since the semiconductor substrate 1 is p-type, separation is performed.

Further, since electrodes and wiring layers are usually provided on the isolation region, these electrodes and the like, here the gate electrode 3 generate n-type carriers at the lower portion by applying a positive voltage, and the first source The drain region 4 and the second source / drain region 5 may be short-circuited. Therefore, a device is usually devised so that a thick insulating film is provided in the isolation region so that n-type carriers are not easily generated by an electrode or a wiring layer.

Therefore, in this conventional example, a groove-shaped trench C is dug to a depth of, for example, about 5 μm in the silicon substrate 1 by anisotropic dry etching or the like as a thick insulating film.
By embedding an oxide film (embedded insulating layer) 11 by the above, isolation between elements is ensured.

Such a method is called trench isolation, and is a method used for element isolation of submicron transistors.

Although the NMOS using the n-type impurity for the source / drain regions has been described here, the p-type impurity is used for the source / drain region.
Separation can be similarly performed for the PMOS used for the drain region.

Further, such a trench isolation can easily separate a P-well used for an NMOS and an N-well used for a PMOS in a CMOS in which an NMOS and a PMOS are formed on the same silicon substrate.
This is also a useful separation method to prevent latch-up due to parasitic thyristor operation occurring between S transistors.

There are also semiconductor devices disclosed in Japanese Patent Application Laid-Open Nos. 60-206040, 61-290753, and 63-12148.

[Problems to be Solved by the Invention] Since the conventional semiconductor device is configured as described above, the buried oxide film easily generates positive charges as fixed charges at the interface with the silicon substrate, and the surface of the silicon substrate 1 is n The n-type inversion layer 12 causes the first source
There is a problem in that the drain region 4 and the second source / drain region 5 are short-circuited, and the circuit is likely to malfunction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a semiconductor device capable of reliably separating elements without causing a malfunction in a circuit and further simplifying a formation process thereof. The purpose is to provide.

[Means for solving the problem]

A semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type, a second conductivity type region provided on the semiconductor substrate,
A trench dielectric film provided on an inner wall of a groove-shaped trench formed by dug a semiconductor substrate between the second conductivity type regions, and a trench dielectric film provided inside the trench via the trench dielectric film and A metal layer having an upper portion extending beyond the substrate surface and having a Fermi level closer to the Fermi level of the semiconductor substrate of the first conductivity type than the intrinsic Fermi level of the semiconductor substrate, and connected to the metal layer; And a wiring layer fixed to the same potential as the semiconductor substrate.

[Action]

In the present invention, the first ferromagnetic level of the semiconductor substrate fixed at the same potential as the semiconductor substrate is equal to the first ferromagnetic level.
A metal layer having a Fermi level on the Fermi level side of a conductive semiconductor substrate has a small work function difference between the substrate and the buried layer because the Fermi level is close to the semiconductor substrate.
The MOS field effect transistor formed through the trench dielectric film has a high threshold. Further, the metal layer having the Fermi level on the Fermi level side of the semiconductor substrate of the first conductivity type with respect to the intrinsic Fermi level of the semiconductor substrate is fixed at the substrate potential. As a result, carriers of the same conductivity type as the semiconductor substrate are formed on the trench surface. Because of the induction, the generation of n-type carriers, which is likely to occur in the conventional NMOS, is suppressed, and the transistor can be easily separated.

Further, by forming the buried semiconductor or metal layer so as to extend from the surface of the substrate, the separation of the source / drain region adjacent to the trench is further ensured, and the step of forming the source / drain region is simplified. can do.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, in which the same reference numerals as in FIG. 3 denote the same or corresponding parts. Reference numeral 6 denotes a trench dielectric film, 7 denotes a polysilicon buried layer, and 10 denotes a ground electrode connected to the polysilicon buried layer 7.

Next, the operation will be described. Since the basic operation is almost the same as that described in the conventional example, only the differences from the conventional example will be described.

In this embodiment, a trench dielectric film 6 is formed on the inner wall surface of the trench C by, for example, a thermal oxidation method, and a p-type polysilicon layer 7 is buried on the trench dielectric film 6. The polysilicon buried layer 7 is connected to the ground electrode 10 and is fixed at 0 V at the same potential as the substrate.

Here, the buried polysilicon layer 7 is p-type, and the silicon substrate 1 is p-type. Since the work function difference between the two is small, the threshold value of the MOS transistor formed via the trench dielectric film 6 is large. Has become. In addition, since the polysilicon layer 7 is grounded and is at 0 V, p-type carriers are induced on the trench surface, and the first source region 4
And the second source region 5 are completely separated from each other.

In the above embodiment, a polysilicon buried layer having the same conductivity type as the silicon substrate 1 is used. However, a metal whose Fermi level is closer to the Fermi level of the semiconductor substrate than the intrinsic Fermi level of the semiconductor substrate, for example, platinum silicide Even if is used as a buried layer with respect to a p-type substrate, the work function difference between the metal layer and the semiconductor substrate is small, so that it is effective for isolation between elements, and the same effect as in the above embodiment can be obtained.

In the above embodiment, the NMOS having the n-type source / drain regions has been described.
A PMOS may be used, and the same effects as in the above embodiment can be obtained.

Also, when separating between NMOS and PMOS, the NMOS side
If the isolation trench and the PMOS isolation trench are provided on the PMOS side, complete element isolation between the two transistors becomes possible.

Further, as in another embodiment of the present invention shown in FIG. 2, an electrode such as a gate electrode 3 or a wiring layer may be provided above the trench, for example. Also, the buried layer has a fixed potential, and does not affect the separation.

[Effects of the Invention] As described above, according to the semiconductor device of the present invention,
A first conductivity type semiconductor substrate, a second conductivity type region provided on the semiconductor substrate, and an inner wall of a groove-shaped trench provided by dug the semiconductor substrate between the second conductivity type regions. A trench dielectric film formed between the first dielectric layer and the intrinsic Fermi level of the semiconductor substrate, the trench dielectric film being provided inside the trench through the trench dielectric film and having an upper portion extending beyond the substrate surface. A metal layer having a Fermi level on the Fermi level side of a conductive semiconductor substrate,
Since the semiconductor device has a wiring layer connected to the metal layer and fixed to the same potential as the semiconductor substrate, carriers of the same conductivity type as the semiconductor substrate are induced on the trench surface, and a source / source of the opposite conductivity type is induced. There is an effect that the drain region is completely separated between adjacent elements.

In addition, since the trench structure is formed, there is an effect that a separation withstand voltage is large and a device suitable for miniaturization of an element is obtained.

Further, in the element forming process, Japanese Patent Application Laid-Open No. 60-2060
No. 40, JP-A-61-290753, and JP-A-63-12
Unlike the one disclosed in Japanese Patent Publication No. 148, a polysilicon buried layer or a metal layer was formed extending from the surface of the substrate, and this was used as a mask to implant ions into each source / drain region. It can be performed directly, and has an effect that the manufacturing process can be simplified.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to one embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor device according to another embodiment of the present invention, and FIG. 3 is a sectional view of a conventional semiconductor device. In the figure, 1 is a silicon substrate, 2 is a gate dielectric film,
3 is a gate electrode, 4 is a first source / drain region, 5 is a second source / drain region, 6 is a trench dielectric film, 7
Is a polysilicon buried layer, 8 is an interlayer insulating film, 9 is a wiring layer, and 10 is a ground electrode. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, a second conductivity type region provided on the semiconductor substrate, and a trench-shaped trench provided by digging the semiconductor substrate between the second conductivity type regions. A trench dielectric film provided on the inner wall of the semiconductor substrate, and an intrinsic fermi-metal of the semiconductor substrate provided inside the trench via the trench dielectric film and having an upper portion extending beyond the substrate surface. A metal layer having a Fermi level on the Fermi level side of the semiconductor substrate of the first conductivity type from a level, and a wiring layer connected to the metal layer and fixed at the same potential as the semiconductor substrate. Semiconductor device.