JP2004289177A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method using an SOI (silicon on insulator) substrate capable of high integration that is achieved by solving the problem of breakdown voltage lowering between source and drain which has been a problem in the conventional SOI FET (field effect transister), and by efficiently arranging a body contact region that may be a problem for achieving high integration. <P>SOLUTION: In the semiconductor device, a field oxide film 10 is formed so that it may reach, from the main surface of an SOI layer 5, the main surface of an embedded oxide film 4. Thus, the pMOS (P-channel metal oxide semiconductor) active region 6 of SOI and the nMOS (N-channel MOS) active region 8 of SOI can be electrically separated completely. Therefore, the occurrence of a latch up can be completely prevented. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device formed on an SOI (Silicon on Insulator) substrate to realize high-speed operation and a method of manufacturing the same.

  First, with reference to FIGS. 75 to 77, a planar structure and a cross-sectional structure of a semiconductor device having a gate laid-down gate array formed on a silicon substrate will be described. FIG. 76 is a sectional view taken along line AA in FIG. FIG. 77 is a cross-sectional view taken along line XX in FIG.

  First, a field oxide film 302 is formed at a predetermined position on the silicon substrate 316. In the semiconductor substrate 316, a p-type MOS field effect transistor forming region 310 and an n-type MOS field effect transistor forming region 312 are formed. Gate electrodes 304 are regularly arranged in lower transistor formation regions 310 and 312. In the semiconductor device including the gate array structure having the above structure, each block on which the gate electrode 304 is laid is electrically separated by the field oxide film 302. In one block, an active region is electrically separated by a gate electrode 304.

  Next, with reference to FIG. 78, the operation principle of the nMOS field effect transistor forming region 312 will be specifically described. For example, by fixing the gate electrode 304 to the ground potential, the transistor 317 including the gate electrode 318, the source region 320, and the drain region 322, and the transistor 323 including the gate electrode 324, the source region 326, and the drain region 328 It is electrically separated and can operate independently and separately. In the p-type MOS field effect transistor forming region 310, the same effect can be obtained by fixing the gate electrode between the transistors to be separated to the power supply potential.

  The method of electrically isolating the transistors by fixing the gate electrode between the transistors to be separated to the power supply potential or the ground potential in this manner is called a gate isolation method, and the gate electrode between the transistors is separated. Is called a gate isolation gate electrode. The gate isolation method is a method suitable for high integration, in which the gate electrode can be used effectively without waste compared to the isolation method using a field oxide film.

  Next, a semiconductor device including a three-input NAND gate using the above-described gate isolation method will be described with reference to FIGS. FIG. 80 is a plan view of a semiconductor device including the three-input NAND gate shown in FIGS. 79 (a) and (b). In FIG. 80, the upper block is a p-type MOS field-effect transistor formation region, and the lower block is an n-type MOS field-effect transistor formation region. By forming the gate electrode and the source / drain region into an internal wiring structure as shown in FIG. 80, a three-input NAND gate can be easily formed. In FIG. 80, the gate electrode at the right end of the block is a p-type MOS field-effect transistor formation region, and the n-type MOS field-effect transistor formation region is fixed to a power supply potential and a ground potential, respectively, so that the adjacent transistor is electrically connected. It becomes possible to separate them.

The semiconductor device having the conventional gate-laying type gate array described above is manufactured on a bulk silicon substrate. In recent years, it has been studied to form this on an SOI (Silicon on Insulator) substrate. When a CMOS field effect transistor is formed on an SOI substrate, compared with a CMOS field effect transistor formed on a bulk silicon substrate,
(1) Increase in driving capability (2) Reduction in junction capacitance in source / drain regions (3) Features such as latch-up free are obtained.

  FIGS. 81 and 82 are cross-sectional views showing the case where MOS field-effect transistors are formed on a bulk silicon substrate and an SOI substrate, respectively. According to the SOI substrate, since the depletion layer under the channel extends only to the buried oxide film, the voltage applied to the gate electrode effectively generates carriers in the channel and obtains a feature that the driving capability is increased. Can be. Further, the junction capacitance of the source / drain region can be reduced because the junction of the source / drain is formed only on the surface perpendicular to the SOI layer due to the buried oxide film. Further, since each MOS field-effect transistor is electrically separated completely by the buried oxide film, latch-up which has conventionally been a problem does not occur.

  With the above-described features, when a gate array is formed over an SOI substrate, high-speed operation without latch-up can be expected.

  However, in a conventional MOS field-effect transistor formed on an SOI substrate, the breakdown voltage between the source and the drain is lower than that formed on a bulk silicon substrate due to the substrate floating effect of the SOI layer serving as a channel. There was a problem. FIGS. 83 and 84 illustrate how the withstand voltage between the source and the drain is reduced by the substrate floating effect. FIG. 83 shows the Id-Vd characteristics of a MOS field-effect transistor formed on a bulk silicon substrate, and FIG. 84 shows the Id-Vd characteristics of a MOS field-effect transistor formed on an SOI substrate.

  Referring to both figures, a MOS field effect transistor fabricated on a bulk silicon substrate has a breakdown voltage of 5 volts or more, whereas a MOS field effect transistor fabricated on an SOI substrate has a breakdown voltage of only about 2 V. Understand.

  Here, the substrate floating effect will be described with reference to FIGS. Holes 338 generated by impact ionization in the depletion layer near the drain region 334 accumulate below the channel region 332 near the source region 330. The accumulated holes 338 are sequentially accumulated below the channel region 332 to raise the potential of the SOI layer and induce injection of electrons 336 from the source region 330. The injected electrons 336 reach the vicinity of the drain region 334 and generate a new hole 338. As described above, the so-called feed-forward loop due to the injection of the electrons 336 and the generation of the holes 338 causes a decrease in the breakdown voltage between the source and the drain.

  As a countermeasure against the substrate floating effect, several methods have been studied. The most reliable method is to fix the potential of the channel region 344 and prevent the accumulation of the holes 338 with reference to FIG. . For example, in the case of an nMOS field-effect transistor, the channel region is fixed to the ground potential, and in the case of a p-type MOS field-effect transistor, the channel region is fixed to the power supply potential, whereby the accumulation of holes 338 can be prevented. It becomes. In order to fix the potential of the channel region 332, the SOI layer is usually drawn out from under the gate electrode 340 to form a region 350 for taking the body contact 352. According to this method, accumulation of the holes 338 can be prevented. However, there is a problem that an extra region 350 for forming a body contact is required, and it is difficult to cope with high integration of a semiconductor device.

  The present invention has been made to solve the above problems, and has the following objects. A first object is to solve the problem of the MOS field-effect transistor formed on the conventional SOI substrate, that is, to solve the problem of the decrease in the breakdown voltage between the source and the drain and to make the region of the body contact which is a problem for high integration. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which enable high integration of a semiconductor device using an SOI substrate by efficiently arranging the semiconductor devices. A second object is to provide a first transistor forming region including a first conductivity type MOS electric field transistor and a second transistor including a second conductivity type MOS electric field transistor capable of realizing high-speed operation and high integration on an SOI substrate. An object of the present invention is to provide a semiconductor device including a CMOS field-effect transistor having a transistor formation region and a method for manufacturing the same.

  In one aspect of the semiconductor device according to the present invention, a semiconductor layer provided on a main surface of an insulating layer, a plurality of first conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer, A first transistor formation region including a first field oxide film for isolating each of the plurality of first conductivity type MOS field effect transistors; and a plurality of second field oxide films provided on a main surface of the semiconductor layer. A second transistor formation region including a conductive type MOS field effect transistor, and a second field oxide film for separating the plurality of second conductive type MOS field effect transistors from each other; The semiconductor device has a thickness greater than a thickness of the second field oxide film, is formed so as to reach a main surface of the insulating layer from a main surface of the semiconductor layer, and Comprising a first transistor forming region, and a third field oxide film for isolating the said second transistor forming region.

  In the above invention, preferably, in the first transistor formation region, a first electrode penetrating the first field oxide film and electrically connected to the semiconductor layer; A second electrode penetrating the second field oxide film and electrically connected to the semiconductor layer.

  In another aspect of the semiconductor device according to the present invention, a semiconductor layer provided on a main surface of an insulating layer, a plurality of first conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer, A first transistor formation region including a first field shield gate electrode for isolating the plurality of first conductivity type MOS field effect transistors; and a plurality of first field shield gate electrodes provided on a main surface of the semiconductor layer. A second transistor formation region including a two-conductivity-type MOS field-effect transistor, a second field shield gate electrode for separating the plurality of second-conductivity-type MOS field-effect transistors, respectively, A first transistor forming region, a second transistor forming region, a first transistor forming region, and a second transistor forming region. And a field oxide film for separating.

  In the above invention, preferably, a first electrode electrically connected to the first transistor formation region of the semiconductor layer, and electrically connected to the second transistor formation region of the semiconductor layer. A second electrode.

  In the above invention, preferably, the first electrode is electrically connected to the first field shield gate electrode, and the second electrode is electrically connected to the second field shield gate electrode. Connected and placed.

  In the above invention, preferably, the first electrode is disposed outside a plane region of the first field shield gate electrode, and the second electrode is disposed outside a plane region of the second field shield gate electrode. Are also located outside.

  In the above invention, preferably, the first field shield gate electrode includes a main first field shield gate electrode extending in a direction orthogonal to a direction in which the gate electrode of the first conductivity type MOS field effect transistor extends. A second sub-field shield gate electrode orthogonal to the main first field shield gate electrode; the first electrode is provided between the two sub-first field shield gate electrodes; The field shield gate electrode includes a main second field shield gate electrode extending in a direction perpendicular to the direction in which the gate electrode of the second conductivity type MOS field effect transistor extends, and a second field shield gate electrode orthogonal to the main second field shield gate electrode. And two sub-second field shield gate electrodes. Between the field shield gate electrode, the second electrode is provided.

  In the above invention, preferably, the first electrode is connected to the semiconductor layer between any two gate electrodes of the plurality of first conductivity type MOS field effect transistors, and the second electrode is Connected to the semiconductor layer between any two gate electrodes of the plurality of second conductivity type MOS field effect transistors.

  In the above invention, preferably, the semiconductor layer in a region outside the first field shield gate electrode includes a first impurity region of a second conductivity type for maintaining the semiconductor layer at a predetermined potential, The semiconductor layer in a region outside the two-field shield gate electrode includes a first impurity region of a first conductivity type for maintaining the semiconductor layer at a predetermined potential.

  In the above invention, preferably, the semiconductor layer between the first field shield gate electrode and the second field shield gate electrode has an impurity of a first conductivity type for maintaining the semiconductor layer at a predetermined potential. With regions.

  Preferably, in the above invention, a high-concentration impurity region having an impurity concentration higher than that of the source region is provided near the source region below the gate electrode of the second conductivity type MOS field effect transistor.

  In still another aspect of the semiconductor device according to the present invention, there are provided a semiconductor layer provided on a main surface of an insulating layer, and a plurality of first conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer. A first transistor formation region including a first field shield gate electrode for isolating the plurality of first conductivity type MOS field effect transistors; and a plurality of first field shield gate electrodes provided on a main surface of the semiconductor layer. A second transistor formation region including a second conductivity type MOS field effect transistor; a second field shield gate electrode for separating the plurality of second conductivity type MOS field effect transistors; A first transistor forming region, which is provided so as to reach a main surface of the insulating layer from the main surface; A field oxide film for isolating the first field shield gate electrode from the region, wherein the first field shield gate electrode is formed in the first transistor formation region and located at an end of the first field shield gate electrode. A recess is provided in the first transistor formation region, and the second field shield gate electrode is formed in the second transistor formation region and is located at an end of the second field shield gate electrode. A recess is provided in the second transistor formation region.

  In still another aspect of the semiconductor device according to the present invention, there are provided a semiconductor layer formed on a main surface of an insulating layer, and a plurality of first conductivity type MOS field effect transistors formed on the main surface of the semiconductor layer. A first transistor formation region including: a first field shield gate electrode for isolating the plurality of first conductivity type MOS field effect transistors; and a plurality of first field shield gate electrodes formed on a main surface of the semiconductor layer. A second transistor forming region including a second conductivity type MOS field effect transistor, a second field shield gate electrode for separating the plurality of second conductivity type MOS field effect transistors from each other; And a mesa isolation region for isolating the second transistor formation region.

  In the above invention, preferably, a first electrode electrically connected to the first transistor formation region of the semiconductor layer and an electrical connection to the second transistor formation region of the semiconductor layer are formed. And a second electrode.

  In the above invention, preferably, the first electrode is electrically connected to the first field shield gate electrode, and the second electrode is electrically connected to the second field shield gate electrode. Connected and placed.

  In the above invention, preferably, the first electrode is disposed outside a plane region of the first field shield gate electrode, and the second electrode is disposed outside a plane region of the second field shield gate electrode. Are also located outside.

  In the above invention, preferably, the first field shield gate electrode includes a main first field shield gate electrode extending in a direction orthogonal to a direction in which the gate electrode of the first conductivity type MOS field effect transistor extends. A second sub-field shield gate electrode orthogonal to the main first field shield gate electrode; the first electrode is provided between the two sub-first field shield gate electrodes; The field shield gate electrode includes a main second field shield gate electrode extending in a direction perpendicular to the direction in which the gate electrode of the second conductivity type MOS field effect transistor extends, and a second field shield gate electrode orthogonal to the main second field shield gate electrode. And two sub-second field shield gate electrodes. Between the field shield gate electrode, the second electrode is provided.

  In the above invention, preferably, the first electrode is connected to the semiconductor layer between any two gate electrodes of the plurality of first conductivity type MOS field effect transistors, and the second electrode is Connected to the semiconductor layer between any two gate electrodes of the plurality of second conductivity type MOS field effect transistors.

  In the above invention, preferably, the semiconductor layer in a region outside the first field shield gate electrode includes a first impurity region of a second conductivity type for maintaining the semiconductor layer at a predetermined potential, The semiconductor layer in a region outside the two-field shield gate electrode has a first impurity type first impurity region for maintaining the semiconductor layer at a predetermined potential.

  In the above-mentioned invention, preferably, the semiconductor layer between the first field shield gate electrode and the second field shield gate electrode has a first conductivity type impurity for maintaining the semiconductor layer at a predetermined potential. With regions.

  Preferably, in the above invention, a high-concentration impurity region having a higher impurity concentration than the source region is provided near the source region below the gate electrode of the second conductivity type MOS field-effect transistor.

  In still another aspect of the semiconductor device according to the present invention, there are provided a semiconductor layer formed on a main surface of an insulating layer, and a plurality of first conductivity type MOS field effect transistors formed on the main surface of the semiconductor layer. A first transistor formation region including: a first field shield gate electrode for separating the plurality of first conductivity type MOS field effect transistors; and a plurality of first field shield gate electrodes formed on a main surface of the semiconductor layer. A second transistor forming region including a second conductivity type MOS field effect transistor, a second field shield gate electrode for separating the plurality of second conductivity type MOS field effect transistors from each other; And a mesa isolation region for isolating the second transistor formation region from the second transistor formation region. The end face portion of the semiconductor layer, and a third field shield gate electrode.

  In still another aspect of the semiconductor device according to the present invention, there are provided a semiconductor layer formed on a main surface of an insulating layer, and a plurality of first conductivity type MOS field effect transistors formed on the main surface of the semiconductor layer. A first transistor formation region including: a first field shield gate electrode for separating the plurality of first conductivity type MOS field effect transistors; and a plurality of first field shield gate electrodes formed on a main surface of the semiconductor layer. A second transistor forming region including a second conductivity type MOS field effect transistor, a second field shield gate electrode for separating the plurality of second conductivity type MOS field effect transistors from each other; And a mesa isolation region for isolating the second transistor formation region from the second transistor formation region. A field gate electrode formed in the first transistor formation region, and a recess provided in the first transistor formation region located at an end of the first field shield gate electrode; A gate electrode is formed in the second transistor formation region, and a recess is provided in the second transistor formation region located at an end of the second field shield gate electrode.

  In still another aspect of the semiconductor device according to the present invention, there are provided a semiconductor layer provided on a main surface of an insulating layer, and a plurality of first conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer. A first transistor forming region including a first field shield gate electrode for isolating the plurality of first conductivity type MOS field effect transistors; and a plurality of first field shield gate electrodes provided on a main surface of the semiconductor layer. A second transistor forming region including a two-conductivity type MOS field effect transistor, a second field shield gate electrode for separating the plurality of second conductivity type MOS field effect transistors, respectively, and the first field shield The first transistor formation region is provided outside the gate electrode in the first transistor formation region. A first impurity region of a second conductivity type for holding the second transistor shield region, and a second impurity region provided outside the second field shield gate electrode in the second transistor formation region. A second impurity region of a first conductivity type for holding, wherein the first impurity region and the second impurity region allow electrical isolation between the first transistor formation region and the second transistor formation region. Is achieved.

  In the above invention, preferably, the first impurity region and the second impurity region are provided so as to be in contact with each other.

  Preferably, in the above invention, the first impurity region is electrically connected to the first field shield gate electrode, and the second impurity region is electrically connected to the second field shield gate electrode. I do.

  In the above invention, preferably, the first conductivity type is p-type, the second conductivity type is n-type, and the first impurity region of the second conductivity type is equal to or higher than a power supply potential. The potential is fixed, and the second impurity region of the first conductivity type is fixed to be equal to or lower than the ground potential.

  In the above invention, preferably, the semiconductor device further includes a first electrode in contact with the first impurity region, and a second electrode in contact with the second impurity region, wherein the first electrode is formed of the first field shield gate electrode. And the second electrode is disposed outside the planar region of the second field shield gate electrode.

  In the above invention, preferably, the first field shield gate electrode includes a main first field shield gate electrode extending in a direction orthogonal to a direction in which the gate electrode of the first conductivity type MOS field effect transistor extends. A second sub-field shield gate electrode orthogonal to the main first field shield gate electrode; the first electrode is provided between the two sub-first field shield gate electrodes; The field shield gate electrode includes a main second field shield gate electrode extending in a direction perpendicular to the direction in which the gate electrode of the second conductivity type MOS field effect transistor extends, and a second field shield gate electrode orthogonal to the main second field shield gate electrode. And two sub-second field shield gate electrodes. Between the field shield gate electrode, the second electrode is provided.

  In the above invention, preferably, the first electrode is connected to the semiconductor layer between any two gate electrodes of the plurality of first conductivity type MOS field effect transistors, and the second electrode is Connected to the semiconductor layer between any two gate electrodes of the plurality of second conductivity type MOS field effect transistors.

  In the above-mentioned invention, preferably, the semiconductor layer between the first field shield gate electrode and the second field shield gate electrode has a first conductivity type impurity for maintaining the semiconductor layer at a predetermined potential. With regions.

  Preferably, in the above invention, a high-concentration impurity region having a higher impurity concentration than the source region is provided near the source region below the gate electrode of the second conductivity type MOS field-effect transistor.

  Preferably, in the above invention, a third impurity region of a second conductivity type having a lower impurity concentration than the first impurity region is provided outside the first impurity region, and outside the second impurity region. There is a fourth impurity region of the first conductivity type having an impurity concentration lower than that of the second impurity region.

  In still another aspect of the semiconductor device according to the present invention, there are provided a semiconductor layer provided on a main surface of an insulating layer, and a plurality of first conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer. A first transistor formation region including a first field shield gate electrode for isolating the plurality of first conductivity type MOS field effect transistors; and a plurality of first field shield gate electrodes provided on a main surface of the semiconductor layer. A second transistor formation region including a second conductivity type MOS field effect transistor, and a second field shield gate electrode for separating the plurality of second conductivity type MOS field effect transistors from each other; The first transistor formation region is provided on the semiconductor layer in a region outside the shield gate electrode and holds the first transistor formation region at a predetermined potential. A first impurity region of a second conductivity type, and a first conductive region provided in the semiconductor layer in a region outside the second field shield gate electrode, for maintaining the second transistor formation region at a predetermined potential. The second impurity region of the type and the first field shield gate electrode are formed in the first transistor formation region, and the first transistor formation gate located at an end of the first field shield gate electrode. A concave portion is provided in the region, the second field shield gate electrode is formed in the second transistor formation region, and the second transistor formation region is located at an end of the second field shield gate electrode. Is provided with a concave portion.

  In still another aspect of the semiconductor device according to the present invention, there are provided a semiconductor layer provided on a main surface of an insulating layer, and a plurality of first conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer. A first isolation insulating film for isolating each of the plurality of first conductivity type MOS field effect transistors, a second conductivity type MOS field effect transistor provided on a main surface of the semiconductor layer, and a first conductivity type MOS field effect transistor. A field effect transistor; and a second isolation insulating film for isolating the second conductivity type MOS field effect transistor from the second conductivity type. The first isolation insulating film is formed on the semiconductor layer at a predetermined distance from the insulating layer. The second isolation insulating film is provided on the surface, and is provided so as to reach from the main surface of the semiconductor layer to the insulating layer.

  In the above invention, preferably, the impurity concentration provided in the semiconductor layer between the first isolation insulating film and the insulating layer is higher than that of the semiconductor layer provided with the first conductivity type MOS field effect transistor. And a second conductivity type impurity region having

  Further, in the above invention, preferably, it is electrically connected to an electrode for controlling the substrate potential of the first conductivity type MOS field effect transistor.

  Further, in the above invention, preferably, the thickness of the first isolation insulating film is provided to be smaller than the thickness of the second isolation insulating film.

  In the above invention, preferably, the first isolation insulating film and the second isolation insulating film have different surface heights.

  Preferably, in the above invention, the first conductivity type MOS field effect transistor and the second conductivity type MOS field effect transistor each include a source / drain region extending from the semiconductor layer surface to the insulating layer.

  In the above invention, preferably, a plurality of the second conductivity type MOS field effect transistors are provided, provided on a main surface of the semiconductor layer at a predetermined distance from the insulating layer, and a plurality of the second conductivity type MOS field effect transistors are provided. A third isolation insulating film for isolating the conductive type MOS field effect transistors is provided.

  In the above invention, preferably, the impurity concentration provided in the semiconductor layer between the first isolation insulating film and the insulating layer is higher than that of the semiconductor layer provided with the first conductivity type MOS field effect transistor. Formed in the semiconductor layer between the third isolation insulating film and the insulating layer, and higher than the semiconductor layer in which the second conductivity type MOS field effect transistor is formed. A first conductivity type impurity region having an impurity concentration.

  Further, in the above invention, preferably, the thickness of the first and third isolation insulating films is provided to be smaller than the thickness of the second isolation insulating film.

  In the above invention, preferably, the first and third isolation insulating films have different surface heights from the second isolation insulating film.

  Preferably, in the above invention, the first conductivity type MOS field effect transistor and the second conductivity type MOS field effect transistor each include a source / drain region extending from the semiconductor layer surface to the insulating layer.

  In one aspect of the method for manufacturing a semiconductor device according to the present invention, a step of forming an insulating film on a substrate; a step of forming a semiconductor layer on the insulating film; Forming a film and forming a plurality of first field oxide films reaching the insulating film at predetermined positions by using a selective oxidation method; Forming a second field oxide film thinner than the first field oxide film using

  In another aspect of the method for manufacturing a semiconductor device according to the present invention, a step of forming an insulating film on a substrate; a step of forming a semiconductor layer on the insulating film; Forming a film and using a selective oxidation method to form a first field oxide film having a first width and a second field oxide film having a second width smaller than the first width; A step of further oxidizing only the first field oxide film by using the selective oxidation method again and growing the thickness of the first field oxide film until reaching the insulating film.

  In still another aspect of the method for manufacturing a semiconductor device according to the present invention, a step of forming an insulating film on a substrate; a step of forming a semiconductor layer on the insulating film; Forming an oxide film, forming a nitride film on the oxide film, forming a resist film having a predetermined pattern on the nitride film, and using the resist film as a mask, forming a resist film on the semiconductor layer. Etching to a predetermined depth, a step of forming a concave portion of a predetermined depth in the semiconductor layer, after removing the resist film, again forming a resist film having a predetermined pattern, using this resist film as a mask, Patterning a nitride film positioned between the concave portion and the concave portion, and removing the resist film, and then using the nitride film as a mask, selectively oxidizing the nitride film in the concave portion. Comprising a first field oxide monolayer reaches the insulating film, and forming a second field oxide film between the concave portion and the recess.

  In still another aspect of the method for manufacturing a semiconductor device according to the present invention, a step of forming an insulating film on a substrate; a step of forming a semiconductor layer on the insulating film; Forming an oxide film, forming a buffer layer on the oxide film, forming a nitride film on the buffer layer, forming a first opening on the nitride film, Forming a first resist film having a second opening wider than the first opening, and etching the nitride film using the resist film as a mask until the surface of the buffer layer is exposed; Forming a second resist film so as to fill only the first opening, and etching the buffer layer using the first resist film and the second resist film as masks And the first and second steps After removing the resist film, a first field oxide film reaching the insulating film at the position of the first opening and a second field oxide film reaching the position of the insulating film by a selective oxidation method using the nitride film as a mask. Forming a field oxide film.

  According to the semiconductor device of the present invention, the field oxide film is formed so as to reach the main surface of the insulating layer from the main surface of the semiconductor layer. Accordingly, the first transistor formation region and the second transistor formation region can be electrically completely separated from each other, so that a semiconductor device using an SOI substrate can be highly integrated. It is possible to obtain a CMOS field-effect transistor structure capable of realizing high-speed operation and high integration. Further, occurrence of a latch-up phenomenon occurring between the first transistor formation region and the second transistor formation region can be completely prevented.

  According to another semiconductor device based on the present invention, a mesa isolation region is provided in order to separate the first transistor formation region and the second transistor formation region. Accordingly, the first transistor formation region and the second transistor formation region can be electrically completely separated from each other, so that a semiconductor device using an SOI substrate can be highly integrated. It is possible to obtain a CMOS field-effect transistor structure capable of realizing high-speed operation and high integration. Further, the occurrence of latch-up can be completely prevented.

  According to still another semiconductor device based on the present invention, each semiconductor layer in the first and second transistor formation regions can be separately fixed to a predetermined potential. As a result, it is possible to prevent a decrease in the breakdown voltage between the source and the drain due to the substrate floating effect.

  According to still another semiconductor device based on the present invention, the third field shield gate electrode is provided on the end face portion of the semiconductor layer in the mesa isolation region. Thereby, a voltage can be applied to the end face portion of the semiconductor layer by the field shield gate electrode. As a result, the electric potential at the end face portion of the semiconductor layer is suppressed, so that the electric field concentration can be prevented, and the leakage current can be prevented from flowing. It is possible to prevent a decrease.

  According to still another semiconductor device based on the present invention, the first electrode is disposed so as to be electrically insulated from the first field shield gate electrode, and the second electrode is connected to the second field shield gate electrode. They are arranged electrically insulated. This makes it possible to set the first field shield gate electrode and the second field shield gate electrode to different potentials from the semiconductor layer.

  According to still another semiconductor device based on the present invention, the first electrode is disposed so as to be electrically connected to the first field shield gate electrode, and the second electrode is connected to the second field shield gate electrode. They are arranged electrically connected. Thereby, the first field shield gate electrode and the second field shield gate electrode can be set to the same potential as the semiconductor layer.

  Further, according to still another semiconductor device based on the present invention, the MOS field effect transistor is separated by using the gate electrode in the unused area. Accordingly, it is not necessary to form an isolation region, so that high integration of a semiconductor device can be achieved.

  According to still another semiconductor device based on the present invention, a recess is provided in a first transistor forming region located at an end of a first field shield gate electrode, and a recess is provided in an end of a second field shield gate electrode. A recess is provided in the located second transistor formation region. Thus, the first and second field shield gate electrodes can be formed in the first and second MOS transistor formation regions. As a result, the interval when the MOS transistor formation regions are arranged in parallel can be set to the minimum separation width. Therefore, high integration of the semiconductor device can be achieved.

  According to still another semiconductor device based on the present invention, the first impurity region of the second conductivity type and the first impurity region of the first conductivity type are provided. As a result, excess carriers generated by impact ionization can be extracted by using the impurity regions, and an increase in channel potential can be prevented. As a result, the withstand voltage between the source and the drain can be improved.

  According to still another semiconductor device based on the present invention, the predetermined groove is provided at the interface between the first impurity region of the first conductivity type and the first impurity region of the second conductivity type. This makes it possible to reduce a high electric field applied between the first impurity region of the first conductivity type and the first impurity region of the second conductivity type.

  According to still another semiconductor device based on the present invention, a first impurity region of a first conductivity type is provided between a first impurity region of a first conductivity type and a first impurity region of a second conductivity type. Also, a second impurity region of the first conductivity type having a low impurity concentration and a second impurity region of the second conductivity type having an impurity concentration lower than that of the first impurity region of the second conductivity type are provided. Accordingly, a high electric field applied between the first impurity region of the first conductivity type and the first impurity region of the second conductivity type can be reduced, and a high breakdown voltage can be secured.

  According to still another semiconductor device based on the present invention, a first conductivity type impurity region is provided in a semiconductor layer between a first field shield gate electrode and a second field shield gate electrode. This allows holes generated by impact ionization in the channel to be pulled out, thereby preventing a rise in channel potential.

  According to still another semiconductor device based on the present invention, a high-concentration impurity region having an impurity concentration higher than that of the source region is provided near the source region below the gate electrode of the second conductivity type MOS field effect transistor. ing. As a result, holes generated by impact ionization in the channel region near the drain region flow toward the source region. At this time, since the high-concentration impurity region is formed, the potential barrier to the source region is increased, thereby making it difficult for holes to flow into the source region and suppressing injection of electrons from the source region. It becomes.

  Further, according to the method of manufacturing a semiconductor device according to the present invention, the semiconductor device reaches the main surface of the insulating layer from the main surface of the semiconductor layer, and electrically completely separates the first transistor formation region and the second transistor formation region. , A first field oxide film in the first transistor formation region, and a second field oxide film in the second transistor formation region can be easily formed. As a result, high integration of a semiconductor device using an SOI substrate becomes possible, and a first transistor including a first conductivity type MOS field-effect transistor capable of realizing high-speed operation and high integration on an SOI substrate It is possible to obtain a semiconductor device including a CMOS field effect transistor having a formation region and a second transistor formation region including a second conductivity type MOS field transistor.

  Hereinafter, a first embodiment based on the present invention will be described with reference to the drawings.

  First, a sectional structure of the semiconductor device according to the first embodiment will be described with reference to FIG. A buried oxide film 4 having a thickness of about 3800-4200 ° is formed on silicon substrate 2. On this buried oxide film 4, an SOI layer 5 having a thickness of about 500 to 1000 ° is formed. A first field oxide film 10 extending from the surface of the SOI layer 5 to the surface of the buried oxide film 4 is formed on the surface of the SOI layer 5, and the first field oxide film 10 allows the pMOS field effect transistor active region 6 to be formed. And an nMOS field effect transistor active region 8. On the surface of the pMOS field effect transistor active region 6, a second field oxide film 12 for isolating the pMOS field effect transistor is formed. A second field oxide film 12 for isolating the nMOS field effect transistor is also formed on the surface of the nMOS field effect transistor active region 8.

  As shown in FIG. 1, the first field oxide film 10 is thickened and formed so as to be in contact with the buried oxide film 4, so that the pMOS field effect transistor forming region and the nMOS field effect transistor forming region are completely formed. Separation can completely prevent the occurrence of latch-up. On the other hand, the thickness of the second field oxide film 12 is made smaller than that of the first field oxide film 10, so that the potential of the channel portion can be reduced by using the SOI layer 5 in a region below the second field oxide film 12. It can be fixed.

  Next, a method of fixing the potential under the second field oxide film 12 will be described with reference to FIG.

  First, in the pMOS field effect transistor active region 6, an n-type potential fixed region 22 is formed in a region below the second field oxide film 12 so as to be electrically connected to the n-type potential fixed region 22. , A potential fixed electrode 18 penetrating through the second field oxide film 12 is provided. Further, also in the nMOS field effect transistor active region 8, a p-type potential fixing region 20 is provided in a region below the second field oxide film 12, and is electrically connected to the p-type potential fixing region 20. A potential fixing electrode 16 is provided through the second field oxide film 12.

  Next, a planar structure of the semiconductor device shown in FIGS. 1 and 2 will be described with reference to FIG. The cross section of FIG. 2 is a cross section corresponding to the cross section taken along line XX in FIG. First, a first field oxide film 10 is formed so as to surround a pMOS field effect transistor active region 6 and an nMOS field effect transistor active region 8. In the pMOS field effect transistor active region 6, a second field oxide film 12 is formed. Further, a plurality of gate electrodes 24 of the pMOS field effect transistor are arranged so as to extend over the first field oxide film 10 and the second field oxide film 12. Further, a potential fixing electrode 18 is provided between the gate electrode 24 of the pMOS field effect transistor of the second field oxide film 12.

  On the other hand, a second field oxide film 12 is also provided in the nMOS field effect transistor active region 8. Further, a gate electrode 26 of the nMOS field effect transistor is provided so as to straddle the first field oxide film 10 and the second field oxide film 12. Further, a potential fixing electrode 16 is provided between the gate electrode 26 of the nMOS field effect transistor of the second field oxide film 12.

Next, with reference to FIG. 4, the conductivity type in the plan view of the semiconductor device shown in FIG. 3 will be described. First, in the pMOS field-effect transistor active region 6, a source / drain region 32 of a pMOS field-effect transistor formed of a p-type region having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more is formed. In addition, a channel region 28 of a pMOS field effect transistor including an n-type impurity region having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or less is formed. In a region located below the second field oxide film 12, an n-type potential fixing region 22 having an impurity concentration higher than that of the channel region 28 is formed.

Next, in the nMOS field effect transistor active region 8, the source / drain region 34 of the nMOS field effect transistor formed of an n-type region having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more is formed. Further, a channel region 30 of an nMOS field effect transistor formed of a p-type region having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or less is formed. Further, a p-type potential fixing region 20 having a higher impurity concentration than p-type channel region 30 is formed corresponding to a region below second field oxide film 12.

Next, with reference to FIG. 5, improvement of the breakdown voltage between the source and the drain will be described. FIG. 5 is an enlarged view of the region A of the nMOS field effect transistor active region 8 shown in FIG. In the figure, an n-type source region 34 has an impurity concentration of 1 × 10 ²⁰ cm ⁻³ , an n-type drain region 34 has an impurity concentration of 1 × 10 ²⁰ cm ⁻³ , and a p-type channel region. 30 has an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ , and the p-type potential fixed region 20 has an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ .

  For example, consider a state in which a MOS field-effect transistor whose gate potential is set to 0 V is off. When, for example, 5 V is applied to the drain region 34 with respect to the source potential 0 V, the depletion layer 40 extends at the pn junction near the drain region 34, and most of 5 V is applied to the depletion layer 40. As a result, carriers accelerated by the electric field in the depletion layer 40 cause impact ionization and generate a new pair of electrons 36 and holes 38. The generated electrons 36 are drawn by the electric field in the depletion layer 40 and enter the drain region 34.

  On the other hand, the generated holes 38 enter the channel region 30 according to the electric field in the depletion layer 40. As shown in FIG. 5B, the potential of the hole 38 is such that the channel region 30 has a valley bottom, and the hole 38 is accumulated in the channel region 30.

  However, in this embodiment, since the p-type potential fixing region 20 is formed on the lateral side of the channel region 30, the accumulated holes 38 have a further lower potential level of the p-type potential fixing region. It flows to the area 20. Accordingly, the holes 38 flowing into the p-type potential fixing region 20 are drawn out of the element by the potential fixing electrode 16. Thus, the potential does not increase due to the accumulation of the holes 38 in the channel region 30, so that the withstand voltage between the source and the drain can be improved. On the other hand, even in the active region of the pMOS field effect transistor, electrons accumulated in the channel are extracted via the potential fixing electrode 18 so that the withstand voltage between the source and the drain can be improved.

  Next, a second embodiment based on the present invention will be described with reference to FIGS. The second embodiment shows a first method of manufacturing the semiconductor device shown in FIGS.

First, referring to FIG. 6, a buried oxide film having a film thickness of 3800 to 4200 ° is formed on silicon substrate 2 under the conditions of an oxygen ion concentration of 1 × 10 ¹⁸ cm ³ , an energy of about 180 keV and a heat treatment temperature of 1300 to 1350 ° C. 4 is formed. Thereafter, on this buried oxide film 4, an SOI layer 5 having a film thickness of 500 to 1000 ° is formed under the conditions of an oxygen ion concentration of 1 × 10 18 cm ³ , an energy of about 1800 keV, and a heat treatment temperature of 1300 to 1350 ° C.

  Next, a silicon oxide film 14 having a thickness of 100 to 300 ° is formed on the SOI layer 5 at a heat treatment temperature of about 950 ° C. by using a thermal oxidation method. Thereafter, on this silicon oxide film 14, a silicon nitride film 42 having a predetermined opening portion 44 and a thickness of about 500 to 2000 ° is formed.

  Next, referring to FIG. 7, a first field oxide film 10 having a thickness of about 1000 to 2000 ° is formed by using a selective oxidation method at a heat treatment temperature of 950 to 1100 ° C. At this time, the lower surface of the first field oxide film 10 is formed so as to reach the surface of the buried oxide film 4. Next, referring to FIG. 8, after a silicon nitride film 46 is deposited on the entire surface of silicon substrate 2, a resist film 48 having a predetermined opening 50 is formed in a region between first field oxide films 10. The silicon nitride film 46 is etched using the resist film 48 as a mask.

Next, referring to FIG. 9, after removing resist film 48, for example, boron or the like is implanted as an n-type impurity at 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² using new resist film 47 as a mask. The p-type potential fixed region 20 is formed by implanting the SOI layer 5 with the energy of about 20 keV. Next, referring to FIG. 10, after removing the resist film 47, phosphorus or the like is implanted as n-type impurity ions at 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ^{−2 using} the new resist film 49 as a mask. The n-type potential fixing region 22 is formed by implanting the SOI layer 4 under the condition of an energy of 40 keV.

  Next, referring to FIG. 11, after the resist film 49 is removed, the second silicon nitride film 46 is used as a mask by selective oxidation at a heat treatment temperature of 950 to 1100 ° C. and a second film thickness of 500 to 1000 °. Of the field oxide film 12 is formed.

  Next, referring to FIG. 12, after removing silicon nitride film 46, potential fixing electrodes 16 reaching p-type potential fixing region 20 and n-type potential fixing region 22 are formed on second field oxide film 12, respectively. , 18 are formed. Thus, the semiconductor device shown in FIG. 2 is completed. By using the above steps, it is possible to form two types of field oxide films having different film thicknesses.

  Next, a third embodiment based on the present invention will be described with reference to FIGS. The third embodiment shows a second method of manufacturing the semiconductor device shown in FIGS.

First, referring to FIG. 13, on silicon substrate 2, an oxygen ion concentration of 1 × 10 ¹⁸ cm ⁻³ , an energy of about 180 keV, and a heat treatment temperature of 1300 to 1350 ° C., a thickness of 3800 to 4200 ° is embedded. An oxide film 4 is formed. Thereafter, on this buried oxide film 4, an SOI layer 5 having a thickness of 500 to 1000 ° is formed under the conditions of an oxygen ion concentration of 1 × 10 ¹⁸ cm ⁻³ , an energy of 180 keV, and a heat treatment temperature of 1300 to 1350 ° C.

  Next, a silicon oxide film 14 having a thickness of 100 to 300 ° is formed on the SOI layer 5 at a heat treatment temperature of about 950 ° C. by using a thermal oxidation method. Thereafter, on the silicon oxide film 14, a silicon film having a thickness of 500 to 2000 Å having a first opening 54 having a predetermined width and a second opening 55 wider than the first opening. A nitride film 52 is formed. Next, referring to FIG. 14, using silicon nitride film 52 as a mask, first field oxide film 10a and second field oxide film 12 are formed by a selective oxidation method at a heat treatment temperature of 950 ° C. to 1100 ° C. I do.

  Next, referring to FIG. 15, a polysilicon layer 56 and a silicon nitride film 58 are deposited on the entire surface of silicon substrate 2, and only silicon nitride film 58 located above first field oxide film 10a is It is removed by etching. At this time, the polysilicon layer 56 plays a role as an etching stopper.

  Next, referring to FIG. 16, using silicon nitride film 58 as a mask, the thickness of first field oxide film 10a is grown by selective oxidation at a heat treatment temperature of 950 ° C. to 1100 ° C. The first field oxide film 10 reaching the oxide film 4 is completed. Next, referring to FIG. 17, boron ions are implanted into a region below second field oxide film 12 to form p-type potential fixed region 20. Next, referring to FIG. 18, similarly to the above, an n-type potential fixing region 22 is formed by implanting phosphorus ions into a region below second field oxide film 12.

  Next, referring to FIG. 19, potential fixing electrodes 16 and 18 reaching p-type potential fixing region 20 and n-type potential fixing region 22 are formed on second field oxide film 12, respectively. Thus, the semiconductor device shown in FIGS. 1 and 2 is completed. By using the above method, it is also possible to form the first field oxide film and the second field oxide film having different film thicknesses.

  Next, a fourth embodiment based on the present invention will be described with reference to FIGS. The fourth embodiment shows a third method of manufacturing the semiconductor device shown in FIGS.

  First, referring to FIG. 20, buried oxide film 4, SOI layer 5, silicon oxide film 14, and silicon nitride film 42 are formed on silicon substrate 2 by the same method as in the second embodiment. . Thereafter, a resist film 62 having a predetermined opening 64 is formed on the silicon nitride film 42.

  Next, referring to FIG. 21, etching is performed to a predetermined depth of SOI layer 5 using resist film 62 as a mask, to form a recess 66 having a predetermined depth in SOI layer 5. Next, referring to FIG. 22, after removing the resist film 62, a resist film 68 having a predetermined opening 70 is formed again, and the resist film 68 is used as a mask between the concave portions 66. The nitride film 42 located is patterned.

  Next, referring to FIG. 23, after removing resist film 68, first field oxide film 10 and second field oxide film 12 are formed simultaneously by selective oxidation using nitride film 42 as a mask. At this time, the bottom surface of first field oxide film 10 formed in concave portion 66 has reached the upper surface of buried oxide film 4.

  Next, referring to FIG. 24, an impurity such as boron is implanted into a region below one first field oxide film 10 to form a p-type potential fixing region 20. Next, referring to FIG. 25, an impurity such as phosphorus is implanted into a region below the other second field oxide film 12 to form an n-type potential fixing region 22.

  Next, referring to FIG. 26, potential fixing electrodes 16 and 18 reaching p-type potential fixing region 20 and n-type potential fixing region 22, respectively, are formed on second field oxide film 12. Thus, the semiconductor device shown in FIGS. 1 and 2 is completed. By using the above manufacturing method, the first field oxide film 10 and the second field oxide film 12 having two different thicknesses can be formed.

  Next, a fifth embodiment based on the present invention will be described with reference to FIGS. This fifth embodiment shows a fourth method of manufacturing the semiconductor device shown in FIGS.

  First, referring to FIG. 27, buried oxide film 4, SOI layer 5, and silicon oxide film 14 are formed on silicon substrate 2 by the same method as in the first embodiment. Thereafter, a polysilicon layer 72 having a thickness of 50 to 150 nm is formed on the silicon oxide film 14. Next, on this polysilicon layer 72, a silicon nitride film 42 having a thickness of about 500 to 2000 Å is formed. Thereafter, a resist film 74 having a first opening 76 and a second opening 77 wider than the first opening 76 is formed on the silicon nitride film 42.

  Next, referring to FIG. 28, patterning of silicon nitride film 42 is performed using resist film 74 as a mask. Next, referring to FIG. 29, a second resist film 78 is formed so as to fill only the first opening 77, and the first resist film 74 and the second resist film 78 are masked. Then, the polysilicon layer 72 is etched.

  Next, referring to FIG. 30, after removing the first resist film 74 and the second resist film 78, the first field oxide film 10 and the second field oxide film 10 are formed by selective oxidation using the nitride film 42 as a mask. Field oxide film 12 is formed. At this time, the lower surface of the first field oxide film has reached the upper surface of buried oxide film 4. Next, referring to FIG. 31, an impurity such as boron is implanted into a region below one second field oxide film 12 to form a p-type potential fixed region 20. Thereafter, referring to FIG. 32, an impurity such as phosphorus is further implanted into a region below one second field oxide film 12 to form an n-type potential fixing region 22.

  Next, referring to FIG. 33, potential fixing electrodes 16 and 18 reaching p-type potential fixing region 20 and n-type potential fixing region 22 formed in the region below second field oxide film 12 are formed. . Thus, the semiconductor device shown in FIGS. 1 and 2 is completed. By using the above manufacturing method, the first field oxide film 10 and the second field oxide film 12 having different film thicknesses can be formed.

Next, a sixth embodiment according to the present invention will be described with reference to the drawings. In the first to fifth embodiments, the separation method using a field oxide film has been described. In this embodiment, a case in which a mesa separation method or a field shield separation method is used will be described. Here, the mesa isolation method is a method in which an SOI layer in an active region is left and another portion is removed by etching, and the isolation is performed. The field shield isolation method is a field shield gate in an nMOS field effect transistor formation region. In this method, a voltage of 0 V is applied to the electrodes so that electricity does not flow to the n ⁺ layers on both sides of the field shield gate electrode and the field shield gate electrode is separated.

  First, a planar structure of a semiconductor device using the mesa separation method and the field shield separation method will be described with reference to FIG. The active region 104 of the nMOS field effect transistor and the active region 106 of the pMOS field effect transistor are electrically separated by the mesa separation region 102.

  The active region 104 of the nMOS field effect transistor is provided with a gate electrode 116 and separated by a field shield gate electrode 108. Also, a gate electrode 118 is arranged in the active region 106 of the pMOS field effect transistor, and is separated by a field shield gate electrode 110. A p-type contact region 112 is provided in the nMOS field-effect transistor active region 104, and an n-type contact region 114 is provided in the active region 106 of the pMOS field-effect transistor.

  The p-type contact region 112 and the n-type contact region 114 are each set to have a higher impurity concentration than the channel region. Even when a semiconductor device having the above structure is used, the same effect as that when a field oxide film is used can be obtained.

  Next, a seventh embodiment based on the present invention will be described with reference to FIGS. When the structure of the semiconductor device shown in the sixth embodiment is used, when the mesa separation method is used for separating the active region of the field effect transistor, a leak current may flow on the side wall of the separated SOI layer. This is because electric field concentration occurs at the edge portion of the SOI layer, and the threshold voltage at the side wall and the corner portion of the SOI layer decreases. In order to prevent this, the structure shown in FIGS. 35 and 6 can be used. FIG. 35 is a sectional view taken along line ZZ of the planar structure shown in FIG.

  Referring to both figures, a buried oxide film 122 is formed on a silicon substrate 120. On the buried oxide film 122, a channel region 124 of an nMOS field effect transistor made of an SOI layer and a channel region 126 of a pMOS field effect transistor are formed. A gate electrode 116 is formed on the nMOS field effect transistor channel region 124 via a silicon oxide film 132. On the channel region 126 of the pMOS field effect transistor, a gate electrode 118 is formed via a silicon oxide film 134.

  Further, a field shield gate electrode 108 is provided on an end face of the channel region 124 of the nMOS field effect transistor via a silicon oxide film 132, and the field shield gate electrode 108 is covered with an interlayer insulating film 136. On the other hand, the field shield gate electrode 110 is also provided via the silicon oxide film 134 at the end face of the channel region 126 of the pMOS field effect transistor. The field shield gate electrode 110 is covered with an interlayer insulating film 138.

  As shown in FIGS. 35 and 36, by providing a field shield gate electrode at the edge of the active region of the field effect transistor, a voltage is applied to the edge by the field shield gate electrode. , The potential of the edge portion is suppressed, and the leakage current can be prevented from flowing.

  Next, a method for improving the withstand voltage between the source and the drain by a separation method using the field shield separation method will be described with reference to FIGS. FIG. 37 is a sectional view taken along the line AA shown in FIG.

  Referring to both figures, buried oxide film 122 is formed on silicon substrate 120. On the buried oxide film 122, an nMOS field effect transistor forming region 140 and a pMOS field effect transistor forming region 142 are provided. The nMOS field effect transistor formation region 140 and the pMOS field effect transistor formation region 142 are insulated and separated by an isolation oxide film 144. In addition, field shield gate electrodes 108 and 110 are formed in the isolation within each field effect transistor formation region.

  An SOI region 148 is formed in a region below the field shield gate electrode 108 in the nMOS field effect transistor formation region 140, and a wiring layer 152 and a contact layer 156 are connected to the SOI region 148. Thus, the potential of the SOI region 148 below the field shield gate electrode 108 can be fixed. Also, in the pMOS field effect transistor forming region 142, an SOI region 146 is formed in a region below the field shield gate electrode 110, and the wiring layer 150 and the contact layer 154 are provided in the SOI region 146. . Thus, the potential of SOI region 146 below field shield gate electrode 110 can be fixed.

  Thus, the SOI region 148 can be p-type doped and used to draw holes generated by impact ionization, and the SOI region 146 can be n-type doped and used to extract electrons generated by impact ionization. be able to. By using the above structure, latch-up can be completely prevented, and the withstand voltage between the source and the drain can be improved by fixing the potential under the channel of the transistor via the field shield portion.

  Next, a ninth embodiment based on the present invention will be described with reference to FIGS. In the above-described eighth embodiment, the separation method using an isolation oxide film is used to separate the nMOS field effect transistor formation region 140 and the pMOS field effect transistor formation region 142. However, in this embodiment, And a structure using a mesa separation method. Other structures are the same as in the eighth embodiment. 39 is a cross-sectional view taken along line BB shown in FIG. As described above, even when the mesa separation method is used, the same operation and effect as the eighth embodiment can be obtained.

  Next, with reference to FIG. 41, characteristics of the semiconductor device having the above-described structures of the sixth to ninth embodiments will be described. As an evaluation method, 53-stage CMOS ring oscillators are formed on a thin film SOI substrate and a bulk silicon substrate, and their delay times are compared. There are two types of ring oscillator isolation structures formed on the thin film SOI substrate: a field shield isolation structure in which the potential of the channel region is fixed, and a field isolation structure in which the potential of the channel region is in a floating state.

  These structures were compared with those of a field shield isolation structure formed on a bulk silicon substrate. The horizontal axis of FIG. 41 represents the power consumption normalized by the oscillation frequency. Voltages range from 2V to 5V, and within these voltage ranges, the delay time when formed on a bulk silicon substrate is much greater than that formed on a thin SOI layer. This is because the effect is exhibited by the fact that the parasitic capacitance (junction capacitance) of the source / drain region is smaller on a thin-film SOI substrate than on a bulk silicon substrate.

  Next, with reference to FIG. 42, a case where the power consumption with respect to the power supply voltage in the same structure as in FIG. 41 is compared will be described. Like the ring oscillator shown in FIG. 41, the power consumption formed on the bulk silicon substrate is much larger than that formed on the thin film SOI layer. Next, comparing the power consumption of the two types of isolation structures formed on the thin film SOI layer, when the power supply voltage is low (2 to 3 V), there is no difference between the two, but when the power supply voltage is high (4 to 4 V). 5V), the power consumption of the field isolation becomes larger than that when formed on a bulk silicon substrate, and the characteristic of low power consumption, which is a characteristic of an SOI substrate, cannot be obtained.

  This is because, as described above, the source-drain breakdown voltage decreases due to the parasitic bipolar operation. However, when the substrate potential is fixed by the field shield isolation structure, holes accumulated in the channel region are extracted, and the withstand voltage between the source and the drain is improved, the power consumption of the ring oscillator formed on the bulk silicon substrate up to 5 V is lower than that of the ring oscillator. A low value can be realized.

  As described above, in the semiconductor device in which the substrate potential is fixed, the breakdown voltage between the source and the drain, which is the biggest defect of the MOS field effect transistor formed on the SOI substrate, is improved while utilizing the features of the SOI structure. In a region where the power supply voltage is high, in other words, a circuit operation with the same power supply voltage as a circuit on a bulk silicon substrate can be performed.

  Next, a tenth embodiment based on the present invention will be described with reference to FIGS. In this embodiment, the wiring layer 152 and the contact layer 156 in the nMOS field effect transistor formation region 140, the contact with the SOI region 148 and the wiring layer 150 and the contact layer 154 in the pMOS field effect transistor formation region 142, and the SOI region 146 How to make contact with the user will be described.

  In this embodiment, a case where the potentials of the field shield gate electrodes 108 and 110 and the SOI regions 146 and 148 are separately set will be described. When the field shield gate electrodes 108 and 110 and the SOI regions 146 and 148 are set to different potentials, the field shield gate electrodes 108 and 110 and the wiring layers 150 and 152 are formed so as not to be in electrical contact. There is a need to. In this case, in order to facilitate extraction of holes and electrons, in the SOI regions 146 and 148, the regions of the regions 146b and 148b in contact with the wiring layers 150 and 152 have a higher impurity concentration than the other regions 146a and 148a. It is set high. The cross-sectional view shown in FIG. 43 is a cross-sectional view taken along line CC of the plan view shown in FIG.

  Next, a manufacturing process of the semiconductor device shown in FIG. 43 will be described with reference to FIGS. First, referring to FIG. 45, a buried oxide film 122 is formed on a silicon substrate 120. On the buried oxide film 122, the active region 104 of the nMOS field effect transistor or the active region 106 of the pMOS field effect transistor is formed. A gate oxide film 164 is formed on the active region 104 of the nMOS field effect transistor and the active region 106 of the pMOS field effect transistor. Field shield gate layers 110 and 108 are formed on gate oxide film 164.

  Next, referring to FIG. 46, the field shield gate layers 110 and 108 are patterned into a predetermined shape using photolithography, and the field shield gate electrodes 110 and 108 are patterned. After that, the entire surface of the silicon substrate 120 is covered with the interlayer insulating film 162. Next, referring to FIG. 47, the surface of the active region 104 of the nMOS field effect transistor or the active region 106 of the pMOS field effect transistor is formed in the region between the field shield gate electrodes 110 and 108 by using photolithography. An exposed contact hole 153 is opened. Next, referring to FIG. 48, by forming contact layers 154 and 156 in contact hole 153 and forming wiring layers 150 and 152, a semiconductor device having the structure shown in FIG. 43 is completed.

  Next, an eleventh embodiment based on the present invention will be described with reference to the drawings. In the above-described tenth embodiment, the structure in the case where the potentials of the field shield gate electrodes 108 and 110 and the SOI regions 146 and 148 are set separately has been described. , 110 and the SOI regions 146, 148 have the same potential.

  First, referring to FIG. 49, when compared with the structure shown in FIG. 43, field shield gate electrodes 108 and 110 and contact layers 154 and 156 are arranged so as to be in contact with each other. Thus, the potentials of field shield gate electrodes 108 and 110 and the potentials of SOI regions 146 and 148 can be made equal. The contacts between the wiring layers 150 and 152 and the contact layers 154 and 156 and the field shield gate electrodes 108 and 110 may have various configurations as shown in FIGS. It is possible.

  Next, a manufacturing method for obtaining the structure shown in FIG. 49 will be described with reference to FIGS. First, referring to FIG. 53, a buried oxide film 122 is formed on a silicon substrate 120. On the buried oxide film 122, the active region 104 of the nMOS field effect transistor or the active region 106 of the pMOS field effect transistor is formed. A gate oxide film 164 is formed on active regions 104 and 106 of the field effect transistor. Further, on the gate oxide film 164, field shield gate electrodes 108 and 110 patterned into a predetermined shape are formed.

  Next, referring to FIG. 54, the entire surface of silicon substrate 120 is covered with interlayer insulating film 162. Next, referring to FIG. 55, a resist film 166 having a predetermined pattern is formed on interlayer insulating film 162, and a part of interlayer insulating film 162 is formed using anisotropic etching and isotropic etching. Remove.

  Next, referring to FIG. 56, patterning of field shield gate electrodes 108 and 110 is performed using resist film 166 as a mask. Further, referring to FIG. 57, silicon oxide film 164 is etched using resist film 166 as a mask. Thereafter, referring to FIG. 58, after removing resist film 166, wiring layers 150 and 152 are deposited to complete the semiconductor device having the structure shown in FIG.

  Next, a twelfth embodiment based on the present invention will be described with reference to the drawings. In this embodiment, the relationship between the contact to the active region and the contact to the field shield gate electrode will be described.

  Referring to FIG. 59, a gate electrode 172 is arranged at a predetermined position on active region 170. On the gate electrode 172, a field shield gate electrode 178 is provided. A contact (hereinafter referred to as a body contact) region 176 and a body contact 174 to the active region, and a field shield gate electrode contact 180 are formed to extend in opposite directions.

  Next, referring to FIG. 60, when active regions 170 are arranged in parallel, field shield gate electrode contact 180 of field shield gate electrode 178 is shared with body contact region 176 and body contact 174 in common. It is also possible to provide them in opposite directions.

  Next, a thirteenth embodiment based on the present invention will be described with reference to FIG. In the twelfth embodiment described above, the body contact is provided outside the active region 170. In this embodiment, the body contact with the active region 170 is provided inside the active region 170.

  First, the field shield gate electrode 178 in this embodiment includes a main field shield gate electrode 178a extending in a direction orthogonal to the direction in which the gate electrode 172 of the MOS field effect transistor extends, and a field shield gate electrode 178a orthogonal to the main field shield gate electrode. And a sub-field shield gate electrode 178b. Further, a body contact region 176 is formed between the two sub-field shield gate electrodes to form a body contact 174. The impurity concentration of body contact region 174 is set such that the same impurity concentration is higher than that of the channel region of the field effect transistor.

  Next, a fourteenth embodiment based on the present invention will be described with reference to FIG. In this embodiment, in the gate electrode 172, two gate electrodes 182 not used as the gate electrodes of the MOS field-effect transistors are used, and these gate electrodes 182 are used as field shield gate electrodes to form a field shield isolation. Is performed. By using such a structure, it is not necessary to form a new isolation region, and an unused gate electrode can be used. Therefore, high integration of a semiconductor device can be achieved.

  Next, a fifteenth embodiment based on the present invention will be described with reference to FIGS. First, referring to FIG. 63, according to the semiconductor device of this embodiment, a gate electrode 208 constituting a MOS field effect transistor is arranged on active region 202, and a field shield gate electrode is formed on gate electrode 208. 204 are arranged.

  As can be seen from the structures of the twelfth through fourteenth embodiments, the field shield gate electrode must originally extend outside the active region 202. However, in the present embodiment, instead of extending the field shield gate electrode 204 from the active region 202, a recess 206 is provided in the active region 202 located below the field shield gate electrode 204, so that the field shield gate electrode 204 is It can be formed in the active region 202.

  By providing recesses 206 in field shield gate electrode 204 in this manner, referring to FIG. 64, when active regions 202 are formed in parallel, spacing y between active regions 202 is set to the minimum separation width. It becomes possible. Therefore, high integration of the semiconductor device can be achieved.

  Next, a sixteenth embodiment based on the present invention will be described with reference to FIGS. In this embodiment, a structure in which pMOS field effect transistor forming regions 210 and nMOS field effect transistor forming regions 212 are alternately arranged will be described. FIG. 66 is a cross-sectional view taken along line DD in FIG.

  Referring to both figures, an active region 214 of a pMOS field effect transistor is formed in a pMOS field effect transistor forming region 210, and a gate electrode 218 of the pMOS field effect transistor is formed in the active region 214 of the pMOS field effect transistor. It is arranged at a predetermined position. On the gate electrode 218, a field shield gate electrode 222 is arranged.

  On the other hand, an active region 216 of the nMOS field effect transistor is provided in the nMOS transistor formation region 212, and a gate electrode 220 of the nMOS field effect transistor is arranged at a predetermined position on the active region of the nMOS field effect transistor. I have. Further, a field shield gate electrode 224 is arranged on the gate electrode 220.

  Further, an n-type body contact region 226 and a p-type body contact region 228 are formed at the interface between the pMOS field effect transistor forming region 210 and the nMOS field effect transistor forming region 212. The n-type body contact region 226 is fixed at a power supply potential (Vcc) or higher. The p-type body contact region 28 is fixed to a ground potential (GND) or a potential lower than the ground potential.

  By providing the n-type body contact region 226 and the p-type body contact region 228 in this manner, extra carriers generated by impact ionization can be extracted and a rise in the channel potential can be prevented. Can be improved.

  Next, a seventeenth embodiment according to the present invention will be described with reference to FIGS. FIG. 68 is a sectional view taken along line EE in FIG. 67. In the sixteenth embodiment described above, there is a problem that the withstand voltage is reduced because a high electric field is applied to the interface between the n-type body contact region 226 and the p-type body contact region 228. In order to solve this problem, in the present embodiment, a groove 230 having a minimum separation width is provided at the interface between the n-type body contact region 226 and the p-type body contact region 228. By providing groove portion 230 in this manner, n-type body contact region 226 and p-type body contact region 228 are electrically separated, so that a high voltage is not applied and a decrease in breakdown voltage does not occur. .

Next, a seventeenth embodiment according to the present invention will be described with reference to FIGS. FIG. 70 is a sectional view taken along line EE in FIG. As one structure for solving the problem in the sixteenth embodiment described above, in the seventeenth embodiment, a groove 230 is formed between an n-type body contact region 226 and a p-type body contact region 228. and that although, in this embodiment, the interface between the n-type body contact region 226 and the p-type body contact region 228, and further, the impurity concentration of about 1 × ¹⁰ 16 ^{cm -3} n ^- isolation region 232 and p ^- An isolation region 234 is provided. By providing such a low-concentration impurity region, the electric field can be reduced, so that a decrease in withstand voltage can be avoided.

Next, a nineteenth embodiment based on the present invention will be described with reference to FIG. In the eighteenth embodiment of the above, the interface further n of n-type body contact region 226 and the p-type body contact region 228 ^- the isolation region 232 p ^- but be provided with a separation region 234, transistor formation region Since carriers that are problematic due to impact ionization in the channel in the above are holes, as shown in FIG. 71, the entire outside of the field shield gate electrodes 222 and 224 is covered with p-type impurities and fixed to the ground potential. By doing so, the above problem can be solved.

  Next, a twentieth embodiment according to the present invention will be described with reference to FIGS. As described in the nineteenth embodiment, since the carrier generated by impact ionization in the channel and causing a problem is a hole, a method is considered in which attention is paid only to the source / drain breakdown voltage of the nMOS field effect transistor. Can be As a structure for improving the withstand voltage between the source and the drain of the nMOS field effect transistor, a region having a higher impurity concentration than the p-type channel portion is formed in the channel portion near the source region, thereby injecting electrons from the source region. Can be prevented.

  First, referring to FIG. 72, source region 240 and drain region 242 are formed on both sides of gate electrode 246. On one side of the channel region 244 below the gate electrode 246, a region 252 having a higher p-type impurity concentration than the channel region 24 near the source region 240 is formed. Referring to FIG. 74, a field shield isolation 254 is formed around gate electrode 246.

Referring to FIG. 72 again, a method of manufacturing the nMOS field effect transistor shown in FIG. 72 will be described. First, after the SOI layer is field-separated, boron, which is a p-type impurity, is implanted in a channel of about 1 × 10 ¹² cm ^{−2 over the} entire surface of the SOI layer to form a gate electrode. Next, boron of about 1 × 10 ¹³ cm ⁻² is additionally implanted from one direction. Thereafter, by forming normal source / drain regions, the transistor is completed. Thus, as shown in FIGS. 72 and 73, a high-concentration channel region 252 having a higher impurity concentration than the channel region 244 is formed in the channel region 244 near the source region 240.

  By forming such an impurity profile, holes generated by impact ionization in the channel region 244 near the drain region 242 flow to the source region 240. At this time, since the high-concentration channel region 252 is provided, the potential barrier to the source region 240 is increased, so that holes hardly flow into the source region 240 and the injection of electrons from the source region 240 is suppressed. It is possible to do.

(The invention's effect)
According to the semiconductor device according to the present invention, the first transistor formation region and the second transistor formation region can be completely electrically separated from each other, and high integration of a semiconductor device using an SOI substrate can be achieved. In addition, it is possible to obtain a CMOS field-effect transistor structure capable of realizing high-speed operation and high integration on an SOI substrate. Further, it is possible to completely prevent the occurrence of latch-up.

  Next, according to another aspect of the semiconductor device according to the present invention, the semiconductor device has a mesa isolation region for isolating the first transistor formation region and the second transistor formation region. Accordingly, the first transistor formation region and the second transistor formation region can be electrically completely separated from each other, so that a semiconductor device using an SOI substrate can be highly integrated. It is possible to obtain a CMOS field-effect transistor structure capable of realizing high-speed operation and high integration. Further, the occurrence of latch-up can be completely prevented.

  Next, according to still another aspect of the semiconductor device according to the present invention, each of the semiconductor layers in the first and second transistor formation regions can be separately fixed to a predetermined potential. As a result, it is possible to prevent a decrease in the breakdown voltage between the source and the drain due to the substrate floating effect.

  Next, according to still another aspect of the semiconductor device based on the present invention, a third field shield gate electrode is provided on an end face portion of the semiconductor layer in the mesa isolation region.

  Thus, a voltage is applied to both end portions of the semiconductor layer by the gate electrode. As a result, the potential at the end face portion of the semiconductor layer is suppressed, electric field concentration is prevented, and furthermore, leakage current is prevented from flowing. It can be suppressed.

    Next, according to still another aspect of the semiconductor device according to the present invention, the first electrode is disposed so as to be electrically insulated from the first field shield gate electrode, and the second electrode is disposed in the second field shield gate. It is arranged so as to be electrically insulated from the electrodes. Thus, the first electrode and the second electrode can be set at different potentials from the semiconductor layer.

  Next, according to still another aspect of the semiconductor device according to the present invention, the first electrode is arranged so as to be electrically connected to the first field shield gate electrode, and the second electrode is arranged in the second field shield gate. It is arranged so as to be electrically connected to the electrodes. Thus, the first electrode and the second electrode can be set to the same potential as the semiconductor layer.

  Next, according to still another aspect of the semiconductor device according to the present invention, the MOS transistor is separated by using the gate electrode in the unused area. Thus, it is not necessary to form an isolation region, so that high integration of a semiconductor device can be achieved.

  Next, according to still another aspect of the semiconductor device according to the present invention, a recess is provided in a first transistor formation region located at an end of a first field shield gate electrode, and a second field shield gate electrode is provided. Are formed in the second transistor formation region located at the end of the second transistor. This makes it possible to form the first and second field shield gate electrodes in the first and second MOS field effect transistor formation regions. As a result, the interval when the MOS field effect transistor forming regions are arranged in parallel can be made the minimum separation width. Therefore, high integration of the semiconductor device can be achieved.

  Next, according to still another aspect of the semiconductor device according to the present invention, the first impurity region of the second conductivity type and the first impurity region of the first conductivity type are provided. As a result, excess carriers generated by impact ionization can be extracted by using the impurity regions, and an increase in channel potential can be prevented. As a result, the withstand voltage between the source and the drain can be improved.

  Next, according to still another aspect of the semiconductor device according to the present invention, a groove is provided at an interface between the first impurity region of the second conductivity type and the first impurity region of the first conductivity type. Thus, the first impurity region of the second conductivity type and the first impurity region of the first conductivity type can be electrically separated, so that the first impurity region of the second conductivity type and the first impurity region of the first conductivity type can be electrically separated. A high electric field applied between the first impurity region and the first impurity region can be reduced, and a decrease in breakdown voltage of the semiconductor device can be prevented.

  Next, according to still another aspect of the semiconductor device according to the present invention, a first conductive type first impurity region is provided between a second conductive type first impurity region and a first conductive type first impurity region. A second conductivity type second impurity region having an impurity concentration lower than the impurity region and a first conductivity type second impurity region having an impurity concentration lower than the first conductivity type first impurity region are provided. Accordingly, a high electric field between the first impurity region of the second conductivity type and the first impurity region of the first conductivity type can be reduced, and a decrease in breakdown voltage of the semiconductor device can be reduced.

  Next, according to still another aspect of the semiconductor device according to the present invention, the semiconductor layer is held at a predetermined potential in the semiconductor layer between the first field shield gate electrode and the second field shield gate electrode. The first conductivity type impurity region is provided. As a result, holes generated by impact ionization in the channel can be extracted, and the potential of the channel region can be prevented from rising.

  Next, according to still another aspect of the semiconductor device according to the present invention, a high-concentration impurity region having an impurity concentration higher than that of the source region is provided near the source region. As a result, holes generated by impact ionization in the channel region near the drain region flow toward the source region. At this time, since the high-concentration impurity region is provided, the potential barrier to the source region is increased, so that holes are less likely to flow into the source region, and the injection of electrons from the source region can be suppressed. Become.

Next, according to the method of manufacturing a semiconductor device according to the present invention, the semiconductor device for separating the first transistor formation region and the second transistor formation region from the main surface of the semiconductor layer to reach the main surface of the insulating layer. The two-field oxide film, the first field oxide film in the first transistor formation region, and the second field oxide film in the second transistor formation region can be easily formed. As a result, high integration of a semiconductor device using an SOI substrate becomes possible, and a first transistor including a first conductivity type MOS field-effect transistor capable of realizing high-speed operation and high integration on an SOI substrate It is possible to obtain a semiconductor device including a CMOS field effect transistor having a formation region and a second transistor formation region including a second conductivity type MOS field transistor.

FIG. 1 is a first sectional view of a semiconductor device in a first embodiment based on the present invention. FIG. 2 is a second sectional view of the semiconductor device in the first embodiment based on the present invention; FIG. 1 is a first plan structural view of a semiconductor device in a first embodiment based on the present invention. FIG. 3 is a second plan structural view of the semiconductor device in the first embodiment based on the present invention. FIGS. 3A and 3B are schematic diagrams showing the operation principle of the semiconductor device according to the first embodiment based on the present invention. FIG. 10 is a cross-sectional view showing a first manufacturing step of the semiconductor device in the second embodiment based on the present invention. FIG. 15 is a cross-sectional view showing a second manufacturing step of the semiconductor device in the second embodiment based on the present invention. FIG. 14 is a cross-sectional view showing a third manufacturing step of the semiconductor device in the second embodiment based on the present invention. FIG. 14 is a sectional view showing a fourth manufacturing step of the semiconductor device in the second embodiment based on the present invention. FIG. 14 is a sectional view showing a fifth manufacturing step of the semiconductor device in the second embodiment based on the present invention. FIG. 16 is a sectional view showing a sixth manufacturing step of the semiconductor device in the second embodiment based on the present invention. FIG. 15 is a cross-sectional view showing a seventh manufacturing step of the semiconductor device in the second embodiment based on the present invention. FIG. 15 is a sectional view showing a first manufacturing step of a semiconductor device according to a third embodiment of the present invention. FIG. 15 is a cross-sectional view showing a second manufacturing step of the semiconductor device in the third embodiment based on the present invention. FIG. 14 is a sectional view showing a third manufacturing step of the semiconductor device in the third embodiment based on the present invention. FIG. 15 is a sectional view showing a fourth manufacturing step of the semiconductor device according to the third embodiment of the present invention. FIG. 15 is a sectional view showing a fifth manufacturing step of the semiconductor device according to the third embodiment of the present invention. FIG. 16 is a sectional view showing a sixth manufacturing step of the semiconductor device in the third embodiment based on the present invention. FIG. 16 is a sectional view showing a seventh manufacturing step of the semiconductor device in the third embodiment based on the present invention. FIG. 14 is a sectional view showing a first manufacturing step of a semiconductor device according to a fourth embodiment of the present invention. FIG. 15 is a sectional view showing a second manufacturing step of the semiconductor device in the fourth embodiment based on the present invention. FIG. 15 is a sectional view showing a third manufacturing step of the semiconductor device according to the fourth embodiment based on the present invention. FIG. 15 is a sectional view showing a fourth manufacturing step of the semiconductor device according to the fourth embodiment of the present invention. FIG. 15 is a sectional view showing a fifth manufacturing step of the semiconductor device according to the fourth embodiment of the present invention. FIG. 15 is a sectional view showing a sixth manufacturing step of the semiconductor device in the fourth embodiment based on the present invention. FIG. 15 is a sectional view showing a seventh manufacturing step of the semiconductor device in the fourth embodiment based on the present invention. FIG. 21 is a sectional view showing a first manufacturing step of a semiconductor device according to a fifth embodiment based on the present invention. FIG. 21 is a sectional view showing a second manufacturing step of the semiconductor device according to the fifth embodiment based on the present invention. FIG. 15 is a sectional view showing a third manufacturing step of the semiconductor device in the fifth embodiment based on the present invention. FIG. 15 is a sectional view showing a fourth manufacturing step of the semiconductor device according to the fifth embodiment based on the present invention. FIG. 21 is a sectional view showing a fifth manufacturing step of the semiconductor device according to the fifth embodiment based on the present invention. FIG. 15 is a sectional view showing a sixth manufacturing step of the semiconductor device in the fifth embodiment based on the present invention. FIG. 21 is a sectional view showing a seventh manufacturing step of the semiconductor device in the fifth embodiment based on the present invention. FIG. 16 is a plan view of a semiconductor device according to a sixth embodiment of the present invention. FIG. 14 is a sectional structural view of a semiconductor device according to a seventh embodiment based on the present invention. FIG. 16 is a plan view of a semiconductor device according to a seventh embodiment of the present invention. FIG. 16 is a sectional structural view of a semiconductor device according to an eighth embodiment based on the present invention. FIG. 16 is a plan view of a semiconductor device according to an eighth embodiment of the present invention. FIG. 21 is a sectional structural view of a semiconductor device according to a ninth embodiment based on the present invention. FIG. 21 is a plan view of a semiconductor device according to a ninth embodiment of the present invention. FIG. 3 is a first diagram showing the effect of the semiconductor device based on the present invention. FIG. 4 is a second diagram showing the effect of the semiconductor device based on the present invention. FIG. 21 is a sectional structural view of a semiconductor device according to a tenth embodiment based on the present invention. FIG. 21 is a plan structural view of a semiconductor device according to a tenth embodiment based on the present invention. FIG. 39 is a sectional view showing a first manufacturing step of a semiconductor device according to a tenth embodiment based on the present invention; FIG. 39 is a cross-sectional view showing a second manufacturing step of the semiconductor device in the tenth embodiment based on the present invention. FIG. 39 is a sectional view showing a third manufacturing step of the semiconductor device in the tenth embodiment based on the present invention. FIG. 21 is a sectional view showing a fourth manufacturing step of the semiconductor device according to the tenth embodiment based on the present invention. FIG. 21 is a sectional structural view of a semiconductor device according to an eleventh embodiment based on the present invention. FIG. 35 is a first diagram showing a shape of a contact region of a semiconductor device according to an eleventh embodiment based on the present invention. FIG. 26 is a second diagram showing the shape of the contact region of the semiconductor device in the eleventh embodiment according to the present invention. FIG. 34 is a third diagram showing the shape of the contact region of the semiconductor device in the eleventh embodiment according to the present invention. FIG. 39 is a cross-sectional view showing a first manufacturing step of the semiconductor device according to the eleventh embodiment based on the present invention. FIG. 39 is a cross-sectional view showing a second manufacturing step of the semiconductor device according to the eleventh embodiment based on the present invention. FIG. 39 is a cross-sectional view showing a third manufacturing step of the semiconductor device according to the eleventh embodiment based on the present invention. FIG. 39 is a sectional view showing a fourth manufacturing step of the semiconductor device according to the eleventh embodiment based on the present invention. FIG. 39 is a sectional view showing a fifth manufacturing step of the semiconductor device according to the eleventh embodiment based on the present invention. FIG. 39 is a sectional view showing a sixth manufacturing step of the semiconductor device according to the eleventh embodiment based on the present invention. FIG. 35 is a first plan structural view of a semiconductor device according to a twelfth embodiment based on the present invention. FIG. 35 is a second plan view showing the structure of a semiconductor device according to a twelfth embodiment of the present invention; FIG. 34 is a plan view of a semiconductor device according to a thirteenth embodiment of the present invention; FIG. 21 is a plan view of a semiconductor device according to a fourteenth embodiment of the present invention. FIG. 35 is a first plan structural view of a semiconductor device according to a fifteenth embodiment based on the present invention. FIG. 35 is a second plan structural view of the semiconductor device in the fifteenth embodiment based on the present invention. FIG. 35 is a plan view of a semiconductor device according to a sixteenth embodiment of the present invention. FIG. 66 is a cross-sectional view taken along line DD in FIG. 65. FIG. 47 is a plan view of a semiconductor device according to a seventeenth embodiment of the present invention. FIG. 67 is a sectional view taken along line EE in FIG. 67. FIG. 37 is a plan view of a semiconductor device according to an eighteenth embodiment based on the present invention. FIG. 69 is a sectional view taken along line FF in FIG. 69. FIG. 39 is a plan view of a semiconductor device according to a nineteenth embodiment based on the present invention. FIG. 21 is a sectional structural view of a semiconductor device according to a twentieth embodiment based on the present invention. FIG. 39 is a first plan structural view of a semiconductor device according to a twentieth embodiment based on the present invention. FIG. 35 is a second plan structural view of a semiconductor device according to a twentieth embodiment based on the present invention. It is a top view of the semiconductor device in the prior art. FIG. 76 is a sectional view taken along the line AA in FIG. 75. 75 is a sectional view taken along line XX in FIG. 75. FIG. 4 is a partially enlarged view showing a planar structure of a semiconductor device in a conventional technique. (A) is a block diagram of a three-input NAND gate. (B) is a circuit diagram of a three-input NAND gate. FIG. 3 is a plan structural view of a semiconductor device implementing a three-input NAND gate. FIG. 3 is a schematic diagram showing the expansion of a depletion layer of a bulk field effect transistor. FIG. 3 is a schematic diagram showing the expansion of a depletion layer in an SOI field-effect transistor. FIG. 81 is a diagram showing a relationship between a drain current and a drain voltage of the MOS field-effect transistor shown in FIG. 81. FIG. 83 is a view showing the relationship between the drain current and the drain voltage of the MOS field effect transistor shown in FIG. 82. It is a 1st figure for demonstrating a substrate floating effect. (A), (b) is the 2nd figure for demonstrating a board | substrate floating effect. It is a plane structure figure of a semiconductor device for eliminating a substrate floating effect in a conventional technology.

Explanation of reference numerals

  2,120 silicon substrate, 4,122 buried oxide film, 6 pMOS / FET active region, 8 nMOS / FET active region, 10 first field oxide film, 12 second field oxide film, 16, 18 potential fixed electrode, 20 p-type potential fixed region, 22 n-type potential fixed region. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (24)

A semiconductor layer provided on a main surface of the insulating layer,
A plurality of first conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer, and a first field shield gate electrode for separating the plurality of first conductivity type MOS field effect transistors, respectively; A first transistor formation region including:
A plurality of second conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer, and a second field shield gate electrode for separating the plurality of second conductivity type MOS field effect transistors, respectively; A second transistor formation region including:
A field oxide film provided so as to reach the main surface of the insulating layer from the main surface of the semiconductor layer and separating the first transistor formation region and the second transistor formation region;
A first electrode electrically connected to the first transistor formation region of the semiconductor layer to fix the semiconductor layer at a first potential;
A second electrode electrically connected to the second transistor formation region of the semiconductor layer to fix the semiconductor layer at a second potential;
And a semiconductor device. A semiconductor layer provided on a main surface of the insulating layer,
A plurality of first conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer, and a first field shield gate electrode for separating the plurality of first conductivity type MOS field effect transistors, respectively; A first transistor forming region including:
A plurality of second conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer, and a second field shield gate electrode for separating the plurality of second conductivity type MOS field effect transistors, respectively; A second transistor formation region including:
A mesa isolation region for isolating the first transistor formation region and the second transistor formation region;
A first electrode electrically connected to the first transistor formation region of the semiconductor layer to fix the semiconductor layer at a first potential;
A second electrode electrically connected to the second transistor formation region of the semiconductor layer to fix the semiconductor layer at a second potential;
And a semiconductor device.   3. The semiconductor device according to claim 2, further comprising a third field shield gate electrode on an end surface of said semiconductor layer in said mesa isolation region. 4. The first electrodes are electrically connected to each other by being arranged in contact with the first field shield gate electrode,
The second electrodes are electrically connected to each other by being arranged in contact with the second field shield gate electrode.
The semiconductor device according to claim 1. The first field shield gate electrode includes:
A main first field shield gate electrode extending in a direction orthogonal to a direction in which the gate electrode of the first conductivity type MOS field effect transistor extends, and two sub first fields orthogonal to the main first field shield gate electrode And a shield gate electrode, wherein a second conductivity type impurity region is provided between the two sub-first field shield gate electrodes, and wherein the first electrode is provided on a surface of the second conductivity type impurity region. 3. The semiconductor device according to claim 1 or 2. An arbitrary pair of the gate electrodes of the plurality of first conductivity type MOS field effect transistors adjacent to each other without using a first field shield gate electrode therebetween is used as a gate electrode of the MOS field effect transistor. Because it is used as a gate electrode,
3. The semiconductor device according to claim 1, wherein a second conductivity type impurity region is provided on a surface of said semiconductor layer sandwiched between said pair of field shield gate electrodes, and said first electrode is provided on a surface of said second conductivity type impurity region. 3. The semiconductor device according to claim 1.   7. The semiconductor device according to claim 5, wherein said second conductivity type impurity region has a higher concentration than a second conductivity type impurity concentration of a channel region of said first conductivity type MOS field effect transistor. A second transistor provided in the semiconductor layer of the first transistor formation region, separated from another active region by the first field shield gate electrode, and configured to maintain the semiconductor layer of the first transistor formation region at a predetermined potential; A first impurity region of two conductivity type;
A second field shield gate electrode provided on a semiconductor layer of the second transistor formation region, separated from another active region by the second field shield gate electrode, for maintaining the semiconductor layer of the second transistor formation region at a predetermined potential; The semiconductor device according to claim 1, further comprising a first impurity region of one conductivity type. A recess is provided in the first transistor formation region located at an end of the first field shield gate electrode;
3. The semiconductor device according to claim 1, wherein a recess is provided in the second transistor formation region located at an end of the second field shield gate electrode. 4. A semiconductor layer provided on a main surface of the insulating layer,
A plurality of first conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer, and a first field shield gate electrode for separating the plurality of first conductivity type MOS field effect transistors, respectively; A first transistor formation region including:
A plurality of second conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer, and a second field shield gate electrode for separating the plurality of second conductivity type MOS field effect transistors, respectively; A second transistor formation region including:
A first impurity region of a second conductivity type, which is provided in the first transistor formation region outside of the first field shield gate electrode and holds the first transistor formation region at a predetermined potential;
A second impurity region of a first conductivity type, which is provided in the second transistor formation region outside of the second field shield gate electrode and holds the second transistor formation region at a predetermined potential. ,
A semiconductor device, wherein the first impurity region and the second impurity region realize electrical separation between the first transistor formation region and the second transistor formation region.   The semiconductor device according to claim 10, wherein the first impurity region and the second impurity region are provided so as to be in contact with each other. The first impurity region is electrically connected to the first field shield gate electrode;
The semiconductor device according to claim 10, wherein the second impurity region is electrically connected to the second field shield gate electrode. A third impurity region of a second conductivity type having an impurity concentration lower than that of the first impurity region outside the first impurity region;
The semiconductor device according to claim 10, further comprising a first conductivity type fourth impurity region having a lower impurity concentration than the second impurity region, outside the second impurity region. The second conductivity type is an n-type;
11. The high-concentration impurity region having a higher impurity concentration than a p-type channel portion in the vicinity of a source region below a gate electrode of the second conductivity type MOS field effect transistor. The semiconductor device according to any one of the above. A semiconductor layer provided on a main surface of the insulating layer,
A plurality of first conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer, and a first field shield gate electrode for separating the plurality of first conductivity type MOS field effect transistors, respectively; A first transistor formation region including:
A plurality of second conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer, and a second field shield gate electrode for separating the plurality of second conductivity type MOS field effect transistors, respectively; A second transistor formation region including:
A p-type impurity region formed on the entire region outside the first field shield gate electrode and outside the second field shield gate electrode, and fixed to a ground potential. , Semiconductor devices. A semiconductor layer provided on a main surface of the insulating layer,
A plurality of first conductivity type MOS field effect transistors are provided on a main surface of the semiconductor layer and include a first field oxide film for separating the plurality of first conductivity type MOS field effect transistors. A first transistor formation region;
A plurality of second conductivity type MOS field effect transistors provided on a main surface of the semiconductor layer, and a second field oxide film for separating the plurality of second conductivity type MOS field effect transistors, respectively. A second transistor formation region;
A third field oxide film formed so as to reach the main surface of the insulating layer from the main surface of the semiconductor layer and separating the first transistor formation region and the second transistor formation region; ,
In the first transistor formation region of the semiconductor layer,
A first electrode electrically connected to fix the semiconductor layer at a first potential;
In the second transistor formation region of the semiconductor layer,
A second electrode electrically connected to fix the semiconductor layer at a second potential;
And a semiconductor device.   A second conductivity type impurity region provided in the semiconductor layer between the first field oxide film and the insulating layer and having a higher impurity concentration than the semiconductor layer provided with the first conductivity type MOS field effect transistor; 17. The semiconductor device according to claim 16, comprising:   17. The semiconductor device according to claim 16, wherein the first conductivity type MOS field effect transistor includes a source / drain region reaching the insulating layer from a surface of the semiconductor layer.   17. The semiconductor device according to claim 16, wherein the first and second field oxide films have a smaller thickness than the third field oxide film.   17. The semiconductor device according to claim 16, wherein the first and second field oxide films have different surface heights from the third field oxide film. Forming an insulating film on the substrate;
Forming a semiconductor layer on the insulating film;
Forming an oxide film on the semiconductor layer and forming a plurality of first field oxide films reaching the insulating film at predetermined positions using a selective oxidation method;
Forming a second field oxide film thinner than the first field oxide film in a region sandwiched by the first field oxide film again by using a selective oxidation method;
A method for manufacturing a semiconductor device comprising: Forming an insulating film on the substrate;
Forming a semiconductor layer on the insulating film;
An oxide film is formed on the semiconductor layer, and a first field oxide film having a first width and a second field oxide film having a second width smaller than the first width are formed by using a selective oxidation method. Forming a film and
Using the selective oxidation method again, further oxidizing only the first field oxide film and growing the thickness of the first field oxide film until reaching the insulating film;
A method for manufacturing a semiconductor device comprising: Forming an insulating film on the substrate;
Forming a semiconductor layer on the insulating film;
Forming an oxide film on the semiconductor layer;
Forming a nitride film on the oxide film;
Forming a resist film having a predetermined pattern on the nitride film, using the resist film as a mask, performing etching to a predetermined depth of the semiconductor layer, and forming a concave portion of a predetermined depth in the semiconductor layer; ,
Forming a resist film having a predetermined pattern again after removing the resist film, and patterning a nitride film located between the concave portion and the concave portion using the resist film as a mask;
After removing the resist film, using the nitride film as a mask, a first field oxide film in which the oxide film in the recess reaches the insulating film by a selective oxidation method, and a second field oxide film between the recess and the recess. Forming a field oxide film;
A method for manufacturing a semiconductor device comprising: Forming an insulating film on the substrate;
Forming a semiconductor layer on the insulating film;
Forming an oxide film on the semiconductor layer;
Forming a buffer layer on the oxide film;
Forming a nitride film on the buffer layer;
A first resist film having a first opening and a second opening wider than the first opening is formed on the nitride film, and the buffer is formed by using the resist film as a mask. Etching the nitride film until the surface of the layer is exposed;
Forming a second resist film so as to fill only the first opening, and etching the buffer layer using the first resist film and the second resist film as masks;
After removing the first and second resist films, a first field oxide film reaching the insulating film at the position of the second opening by a selective oxidation method using a nitride film as a mask; Forming a second field oxide film at the position of the portion;
A method for manufacturing a semiconductor device comprising:

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