JP3111948B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and, more particularly, to an SOI in which a semiconductor layer constituting a semiconductor element is formed on an insulator layer formed on a semiconductor substrate.
The present invention relates to a semiconductor integrated circuit having a (silicon on insulator) structure.

[0002]

2. Description of the Related Art Semiconductor integrated circuits, in particular, CMOS-LS
In recent years, high integration and operating speed of I have been promoted, and such a tendency is expected to be further promoted in the future. Up to now, performance improvement of a semiconductor integrated circuit has been achieved mainly by reduction (scaling) of physical dimensions (element dimensions) of semiconductor elements. Scaling has been performed under a constant power supply voltage up to a submicron-order element size, so that a significant increase in operating speed has been achieved. However, device dimensions smaller than the submicron order (for example, when the gate length of a MOSFET is 0.2 μm
In the following, the power supply voltage must be reduced, and there is a limit in increasing the operating speed by simply scaling.

To overcome this limitation, a new technology is being developed, and a CMOS-LSI having an SOI structure in which a semiconductor layer constituting a semiconductor element is formed on an insulator layer formed on a semiconductor substrate. Is one of them. In a CMOS-LSI having such an SOI structure, since the bottom surface of the diffusion layer serving as the source / drain region of the MOSFET is in contact with the insulator layer, the boundary between the diffusion layer and the insulator layer includes electrons and electrons. There is no depletion layer, which is a region where holes do not exist, and the diffusion layer capacitance is extremely small as compared with a conventional MOSFET, so that high-speed operation is possible.

In a CMOS-LSI, in particular,
Heat is generated in the operating region of the MOSFET. This heat value sometimes reaches several tens of watts, and the temperature of the CMOS-LSI rises from tens of degrees to nearly one hundred degrees. Such a rise in temperature has many adverse effects. In particular, there is a problem that the mobility of carriers is reduced, the on-current of the MOSFET is reduced, and the resistance value of the metal wiring is increased, so that the propagation delay due to the metal wiring is increased. In this regard, in a normal CMOS-LSI having no SOI structure, heat generated in the operating region of the MOSFET mainly passes through a semiconductor substrate having a high thermal conductivity, for example, a silicon substrate, and the semiconductor chip is stored therein. Heat is quickly dissipated from the package whose back surface is in contact. On the other hand, S
In a CMOS-LSI having an OI structure, MOS
Since an insulating layer having low thermal conductivity, for example, a silicon oxide film exists between the operation region of the FET and the semiconductor substrate,
The heat generated in the operating region of the MOSFET is not dissipated to the outside, and the temperature of the CMOS-LSI rises rapidly, causing many of the above-mentioned problems.

[0005] Therefore, conventionally, C
A MOS-LSI is disclosed in, for example, JP-A-5-3474.
As disclosed in Japanese Patent Application Laid-Open No. 12, a technique for quickly radiating the heat generated in the operating region of the MOSFET to the outside has been proposed. FIG. 8 is a cross-sectional view of a main part showing a schematic structure example of a CMOS-LSI having a conventional SOI structure disclosed in the above publication. An insulator layer 2 is formed on the entire surface of the silicon substrate 1, and a P-type semiconductor layer 3 and an N-type semiconductor layer 4 are formed on a part of the insulator layer 2. N-type high concentration diffusion layers 5a and 5b are formed on both sides of the P-type semiconductor layer 3, and P-type high concentration diffusion layers 6 on both sides of the N-type semiconductor layer 4.
a and 6b are formed. Further, a silicon oxide film 7 is formed on the entire surface of the insulator layer 2. Gate electrodes 8 a and 8 b are formed above the P-type semiconductor layer 3 and the N-type semiconductor layer 4 with a silicon oxide film 7 interposed therebetween. The silicon oxide film 7 between the P-type semiconductor layer 3 and the gate electrode 8a and the silicon oxide film 7 between the N-type semiconductor layer 4 and the gate electrode 8b are particularly called gate oxide films 9a and 9b. The P-type semiconductor layer 3, the N-type high concentration diffusion layers 5a and 5b, the gate electrode 8a and the gate oxide film 9a
A channel MOSFET (NMOSFET)
Semiconductor layer 4, P-type high-concentration diffusion layers 6a and 6b, gate electrode 8b and gate oxide film 9b are P-channel MOS
An FET (PMOSFET) is configured.

Further, N-type high concentration diffusion layers 5a and 5b, P-type high concentration diffusion layers 6a and 6
b and the insulator layer 2 respectively, and the silicon substrate 1
Contact hole 10 to reach
a to 10d are opened, and tungsten (W) is buried in these contact holes 10a to 10d to form contact plugs 11a to 11d.
Are formed. On the surface of silicon oxide film 7, aluminum wirings 12a to 12c electrically connected to contact plugs 11a to 11d are formed. The contact plugs 11a to 11d play a role of electrically connecting the electrodes of each element formed in the lower layer and the aluminum wiring formed in the upper layer in a semiconductor integrated circuit having a multilayer structure as shown in FIG. Of course, the gate electrodes 8a and 8b are also electrically connected to the aluminum wiring formed on the surface of the silicon oxide film 7 via the contact plug, but are not shown in FIG. In addition, the silicon oxide film 7 is used for each element, in this case,
It plays a role of electrically separating the NMOSFET and the PMOSFET therein.

According to such a configuration, since the contact plugs 11a to 11d and the silicon substrate 1 are in direct contact, the thermal resistance can be extremely reduced, and the MOSF
The heat generated in the ET operation region can be quickly radiated to the outside via the silicon substrate 1. Further, in the above configuration, for example, when an N-type silicon substrate having an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or less is used as the silicon substrate 1, the contact plugs 11a to 11d and the silicon substrate 1
A good Schottky junction is formed between the contact plugs 11a to 11d and the silicon substrate 1 when the silicon substrate 1 is set to the highest potential used in the semiconductor integrated circuit. can do. Here, the Schottky junction refers to a junction that exhibits rectifying properties when a metal and a semiconductor are brought into contact with each other, and electrically insulates the metal and the semiconductor by positively biasing the semiconductor. You can do it.

[0008]

By the way, in the conventional semiconductor integrated circuit disclosed in the above publication, a Schottky junction is formed between the contact plugs 11a to 11d and the silicon substrate 1, so that the diffusion layer capacitance is reduced. However, since the capacitance of the parasitic Schottky junction increases, the effect of reducing the diffusion layer capacitance by using the SOI structure is offset.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor integrated circuit having a small diffusion layer capacitance and excellent heat dissipation.

According to another aspect of the present invention, there is provided a semiconductor integrated circuit comprising: an insulator layer formed on a first conductivity type semiconductor substrate; and a semiconductor element formed on the insulator layer. A semiconductor integrated circuit, comprising: a semiconductor layer forming the semiconductor layer; an insulating film formed on the semiconductor layer; and a plurality of contact plugs for electrically connecting the semiconductor layer and a metal wiring formed on the insulating film. And a second conductive type diffusion layer formed in or on the first conductive type semiconductor substrate, wherein the contact plugs connected to a first power source among the contact plugs are the semiconductor layer and the insulating layer. A contact plug connected to a second power supply penetrates the semiconductor layer and the insulator layer to reach the second conductivity type diffusion layer through the body layer and reaches the first conductivity type semiconductor substrate. To the power supply The contact plugs that are not connection is characterized in that does not penetrate the insulating layer.

In the present invention, any of a P-type semiconductor substrate and an N-type semiconductor substrate may be used as the first conductivity type semiconductor substrate. However, when the P-type semiconductor substrate is used as the first conductivity type semiconductor substrate, , The second conductivity type diffusion layer is N
Type diffusion layer. On the other hand, when an N-type semiconductor substrate is used as the first conductivity type semiconductor substrate, the second conductivity type diffusion layer means a P-type diffusion layer.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit, comprising: an insulator layer formed on a first conductivity type semiconductor substrate; and a semiconductor layer formed on the insulator layer to constitute a semiconductor element. A semiconductor integrated circuit comprising: an insulating film formed on the semiconductor layer; and a plurality of contact plugs for electrically connecting the semiconductor layer and a metal wiring formed on the insulating film. A second conductivity type diffusion layer formed in or on the upper surface of the mold semiconductor substrate, wherein the insulation under the semiconductor element connected to the contact plug connected to the first power source among the contact plugs The body layer is removed, the lower part of the semiconductor layer contacts the first conductivity type semiconductor substrate, and the insulator layer below the semiconductor layer connected to a contact plug connected to a second power supply is removed. Lower conductive layers are in contact with the second conductive type diffusion layer, the lower portion of the insulator layer of the power is the connection to the connection which do not result the contact plugs the above semiconductor layer is characterized by not being removed.

According to a third aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, the second conductive type diffusion layer is connected to the second power supply. It is characterized by being located at the bottom of the layer.

In the present invention, when the P-type semiconductor substrate is used as the first conductivity type semiconductor substrate, the first power supply is, for example, a ground, and the second power supply is a positive power supply.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit according to the third aspect,
A first conductivity type diffusion layer formed in or on the first conductivity type semiconductor substrate, wherein the first conductivity type diffusion layer is positioned below the semiconductor layer connected to the first power supply; It is characterized by doing.

[0016]

[0017]

[0018]

[0019]

According to the structure of the present invention, at least one contact plug connected to the first power supply and connected to the second conductivity type high concentration diffusion layer whose potential does not change is connected to the first conductivity type semiconductor substrate or the first conductivity type. At least the contact plug connected to the first conductive type high concentration diffusion layer, which is formed to reach the conductive type diffusion layer and is connected to the second power source and whose potential does not change, reaches the second conductive type diffusion layer. Since it reaches and is formed, a heat radiation path is secured.

In addition, when at least one contact plug is in contact with the first conductivity type semiconductor substrate or the first conductivity type diffusion layer and at least one contact plug is in contact with the second conductivity type diffusion layer, the capacitance of the diffusion layer is increased. Although the capacitance of the parasitic Schottky junction increases, there is no problem since the potential does not fluctuate. Therefore, the diffusion layer capacity is small and the heat dissipation is excellent.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. A. First Embodiment FIG. 1 is a sectional view of a principal part showing a schematic structure of a semiconductor integrated circuit according to a first embodiment of the present invention, and FIGS. 2 to 5 are process diagrams showing a method of manufacturing the semiconductor integrated circuit. It is. In FIG. 1, a P-type silicon substrate 21 has an N-type diffusion layer 2 therein.
2, an insulator layer 23 is formed on the entire surface, and a P-type semiconductor layer 24 and an N-type diffusion layer 25 are formed on a part of the insulator layer 23. P-type semiconductor layer 24
N-type high-concentration diffusion layers 26a and 26b are formed on both sides of the P-type high-concentration diffusion layer 27a.
And 27b are formed.

Further, a silicon oxide film 28 is formed on the entire surface of the insulator layer 23. Gate electrodes 29a and 29b are formed above the P-type semiconductor layer 24 and the N-type diffusion layer 25 with a silicon oxide film 28 interposed therebetween.
The silicon oxide film 28 between the P-type semiconductor layer 24 and the gate electrode 29a and the silicon oxide film 28 between the N-type diffusion layer 25 and the gate electrode 29b are particularly called gate oxide films 30a and 30b. The P-type semiconductor layer 24, the N-type high concentration diffusion layers 26a and 26b, the gate electrode 29a and the gate oxide film 30a constitute an NMOSFET, and the N-type diffusion layer 2
5, P-type high concentration diffusion layers 27a and 27b, gate electrode 2
9b and the gate oxide film 30b constitute a PMOSFET.

The surface of the silicon oxide film 28
Contact hole 31a penetrating through the high-concentration diffusion layer 26a and the insulator layer 23 and reaching the silicon substrate 21,
N penetrates the P-type high concentration diffusion layer 27b and the insulator layer 23,
A contact hole 31d reaching the diffusion layer 22 is opened, and a contact reaching from the surface of the silicon oxide film 28 to a partial surface of each of the N-type high concentration diffusion layer 26b and the P-type high concentration diffusion layer 27a. Hall 31
b and 31c are open. Tungsten is buried in these contact holes 31a to 31d, and contact plugs 32a to 32d are formed. On the surface of the silicon oxide film 28, aluminum wirings 33a to 33c electrically connected to the contact plugs 32a to 32d are formed. Of course, the gate electrodes 29a and 29b are also electrically connected to the aluminum wiring formed on the surface of the silicon oxide film 28 via the contact plug, but are not shown in FIG. Further, the silicon oxide film 28 is formed of NMOSFET and P
It plays a role of electrically separating the MOSFET from the inside.

Further, a contact plug 32 connected to the N-type high concentration diffusion layer 26a (source) of the NMOSFET
a is ground (GN) via aluminum wiring 33a.
D), and the N-type high-concentration diffusion layer 2 of the NMOSFET.
Contact plug 33b connected to 6b (drain)
And P-type high concentration diffusion layer 27a of PMOSFET (source)
Are connected to each other via an aluminum wiring 33b, and the contact plug 33c
A contact plug 32d connected to the high-concentration diffusion layer 27b (drain) is connected to a power supply (V _DD ) via an aluminum wiring 33c. Although not shown, N
The gate electrode 29a of the MOSFET and the gate electrode 29b of the PMOSFET are connected to each other via a contact plug and an aluminum wiring.

Next, a method of manufacturing the semiconductor integrated circuit shown in FIG. 1 will be described step by step with reference to FIGS. First, a film thickness of 500 to 200 is formed on the entire surface of the P-type silicon substrate 21 by ion implantation of oxygen atoms.
After forming a 0 nm insulator layer (buried silicon oxide layer) 22, a 500 to 2000 nm thick P
The mold semiconductor layer 24 is formed. Next, a part of the P-type semiconductor layer 24 is selectively oxidized until reaching the insulator layer 23 to form a silicon oxide film 41 (see FIG. 2). This silicon oxide film 41 becomes an insulating isolation region.

Next, a photoresist 42 is applied over the entire surface of the P-type semiconductor layer 24 and the silicon oxide film 41,
An opening is formed only in a portion where an OSFET is to be formed, and phosphorus is ion-implanted into the P-type silicon substrate 21 through the insulator layer 23 at an acceleration energy of about 200 to 300 keV using the photoresist 42 as a mask to form an N-type diffusion layer 22. And using the silicon oxide film 41 and the photoresist 42 as a mask, arsenic is ion-implanted into the P-type semiconductor layer 24 at an acceleration energy of about 100 to 150 keV to form an N-type diffusion layer 25 (see FIG. 3). ).

Next, after removing the photoresist 42,
A silicon oxide film 28 is formed on the entire surface of the P-type semiconductor layer 24, the silicon oxide film 41, and the N-type diffusion layer 25, and substantially above the center of each of the P-type semiconductor layer 24 and the N-type diffusion layer 25 on the silicon oxide film 28. Then, gate electrodes 29a and 29b are formed. The gate electrode 29a is made of, for example, an N-type high-concentration polysilicon layer, and the gate electrode 29b is made of, for example,
It is made of a P-type high concentration polysilicon layer. Further, using the gate electrodes 29a and 29b as a mask, the P-type semiconductor layer 24 is formed.
N-type high concentration diffusion layers 26a and 26b are formed therein, and P-type high concentration diffusion layers 27a and 271b are formed in the N-type diffusion layer 25 (see FIG. 4). Silicon oxide film 28 and N-type diffusion layer 25 between P-type semiconductor layer 24 and gate electrode 29a
The silicon oxide film 28 between the gate electrode 29b and the gate electrode 29b is called the gate oxide films 30a and 30b as described above. In FIG. 4, the silicon oxide film is indicated by a uniform reference numeral 28.

Next, after a silicon oxide film is formed on the entire surface of the silicon oxide film 28 and the gate electrodes 29a and 29b by a plasma chemical vapor deposition (CVD) method, a chemical mechanical polishing (CMP: Ch
The silicon oxide film is flattened by an emical and mechanical polishing method. Then, from the surface of the silicon oxide film, the contact hole 31a penetrates the N-type high-concentration diffusion layer 26a and the insulator layer 23 and reaches the silicon substrate 21, the P-type high-concentration diffusion layer 27b and the insulator layer 23. Then, a contact hole 31d reaching the N-type diffusion layer 22 is opened, and the N-type high-concentration diffusion layer 26b and the P-type high-concentration diffusion layer 27a are separated from the surface of the silicon oxide film 28.
Contact holes 3 reaching the partial surface of each
Open 1b and 31c (see FIG. 5). In FIG. 5, the silicon oxide film is indicated by a uniform reference numeral 28.

Next, tungsten is buried in the contact holes 31a to 31d to form contact plugs 32a to 32d.
After the formation of 2d, aluminum wirings 33a to 33c electrically connected to contact plugs 32a to 32d are formed on the surface of silicon oxide film 28, whereby FIG.
Is completed.

Next, FIG. 6 shows an equivalent circuit diagram of the semiconductor integrated circuit (see FIG. 1) manufactured by the above-described manufacturing method. This is an inverter circuit that is the basis of a CMOS-LSI. Input signals are NMOSFET and PMO
The respective gate electrodes of the SFETs are inputted from input terminals connected to each other. When the input signal is at "H" level, the output signal is at "L" level, and when the input signal is at "L" level, the output signal is " H "level. In this case, NMOSF
ET N-type high concentration diffusion layers 26a and 26b and PMO
Among the P-type high concentration diffusion layers 27a and 27b of the SFET,
The potential changes only in the N-type high-concentration diffusion layer 26b and the P-type high-concentration diffusion layer 27a.
6a and the P-type high-concentration diffusion layer 27b are connected to a ground (GND) and a power supply (V _DD ) whose potentials do not change.

Therefore, in this embodiment, the tip of the contact plug 32a connected to the ground (GND) and connected to the N-type high-concentration diffusion layer 26a whose potential does not change reaches the P-type silicon substrate 21. And is connected to a power supply (V _DD ), so that the potential remains unchanged.
Plug 3 connected to high-concentration diffusion layer 27b
The tip of 2d was formed so as to reach the N-type diffusion layer 22. Thereby, a heat dissipation path is secured. In addition,
The tip of the contact plug 32a is a P-type silicon substrate 21
And the tip of the contact plug 32d is N
The contact with the type diffusion layer 22 increases the capacitance of the parasitic Schottky junction as the diffusion layer capacitance, but does not cause any problem since the potential does not fluctuate. According to such a configuration, since the capacitance of the parasitic Schottky junction can be reduced without impairing the heat radiation effect, the operation speed can be improved by 5 to 20%.

B. Second Embodiment Next, a second embodiment will be described. FIG. 7 is a cross-sectional view of a principal part showing a schematic structure of a semiconductor integrated circuit according to a second embodiment of the present invention. In this figure, parts corresponding to the respective parts in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In the semiconductor integrated circuit shown in this figure, a P-type diffusion layer 51 is formed inside a P-type silicon substrate 21, and the tip of a contact plug 31a reaches the P-type diffusion layer 51. In the manufacturing method of the first embodiment, the P-type diffusion layer 51 passes through the steps shown in FIG.
Boron is applied at a voltage of 100 to 150 keV using a photoresist having an opening only at a portion where an NMOSFET is to be formed as a mask.
It is formed by implanting ions into the P-type silicon substrate 21 through the insulator layer 23 with a moderate acceleration energy. Subsequent manufacturing methods are the same as in the first embodiment described above, and a description thereof will be omitted.

The reason why the P-type diffusion layer 51 is formed as described above is as follows. That is, depending on the package in which the semiconductor chip is stored, there is a type in which the back surface of the semiconductor chip is connected to the ground (GND). In this case, the N-type high concentration diffusion layer 26a connected to the ground (GND) is provided. It is preferable that the contact resistance between the connected contact plug 32a and the P-type silicon substrate 21 be small. Therefore, in order to reduce the right contact resistance, the P-type diffusion layer 51 is formed. Also in the configuration of the second embodiment,
When the tip of the contact plug 32a contacts the P-type diffusion layer 51 and the tip of the contact plug 32d contacts the N-type diffusion layer 22, the capacitance of the parasitic Schottky junction increases as the diffusion layer capacitance. Since it does not fluctuate, there is no problem at all. According to such a configuration, since the capacitance of the parasitic Schottky junction can be reduced without impairing the heat radiation effect, the operation speed can be improved by 5 to 20%.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. Even if there is, it is included in the present invention. For example, in the above-described embodiment, the contact plugs 32a and 32
Although an example has been shown in which all of d reach the P-type silicon substrate 21, the N-type diffusion layer 22, or the P-type diffusion layer 51 through the insulator layer 23, the present invention is not limited to this. The contact plugs 32a to 32d are configured to reach partial surfaces of the N-type high-concentration diffusion layers 26a and 26b and the P-type high-concentration diffusion layers 27a and 27b.
The same effect can be obtained by removing the insulator layer 22 on the lower surface of the a-type and P-type high concentration diffusion layers 27b. Also,
In the above-described embodiment, the example in which both the N-type diffusion layer 22 and the P-type diffusion layer 51 are formed in the P-type silicon substrate 1 has been described. However, the present invention is not limited thereto. Yes, of course.

In the above-described embodiment, an example using a P-type silicon substrate has been described. However, similar effects can be obtained by using an N-type silicon substrate and inverting the conductivity type of each impurity region. The effect can be obtained. Further, similar effects can be obtained when an active element such as an NPN type or PNP type bipolar transistor or a passive element such as a resistor is formed as a semiconductor element. Further, in the above embodiment, the contact plugs 32a to 32d are made of tungsten alone. However, since tungsten is relatively reactive with silicon, before the tungsten is buried in the contact holes 31a to 31d, the contact holes 31a to 31d are formed. ~ 31
It is very preferable to form a titanium (Ti) film or a titanium nitride (TiN) film on the inner wall of d.

[0036]

As described above, according to the structure of the present invention, at least two contact plugs reach the first conductivity type semiconductor substrate or the first and second conductivity type diffusion layers whose potential does not change. Since it is formed, a heat radiation path is secured. When these contact plugs come into contact with the first conductivity type semiconductor substrate and the first and second conductivity type diffusion layers, the capacitance of the parasitic Schottky junction increases as the diffusion layer capacitance, but the potential does not fluctuate. It doesn't matter at all. Therefore, the diffusion layer capacity is small and the heat dissipation is excellent.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing a schematic structure of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a process chart showing a method for manufacturing a semiconductor integrated circuit in the same embodiment.

FIG. 3 is a process chart showing a method for manufacturing a semiconductor integrated circuit in the same example.

FIG. 4 is a process chart showing a method for manufacturing a semiconductor integrated circuit in the same embodiment.

FIG. 5 is a process chart showing a method of manufacturing the semiconductor integrated circuit in the example.

FIG. 6 is an equivalent circuit diagram of the semiconductor integrated circuit shown in FIG. 1;

FIG. 7 is a fragmentary cross-sectional view showing a schematic structure of a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 8 is a cross-sectional view of a principal part showing a schematic structural example of a CMOS-LSI having a conventional SOI structure.

[Explanation of symbols]

Reference Signs List 23 Insulator layer 24 P-type semiconductor layer (semiconductor layer, first conductivity type semiconductor layer) 26a, 26b N-type high concentration diffusion layer (second conductivity type high concentration diffusion layer) 27a, 27b P-type high concentration diffusion layer (second 1 conductivity type high concentration diffusion layer) 28 silicon oxide film 29a, 29b gate electrode 30a, 30b gate oxide film 31a to 31d contact hole 32a to 32d contact plug 33a to 33c aluminum wiring 21 P-type silicon substrate (first conductivity type semiconductor substrate) 22, 25 N-type diffusion layer (second conductivity type diffusion layer) 51 P-type diffusion layer (first conductivity type diffusion layer) _VDD power supply (second power supply) GND Ground (first power supply)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/78 623Z 626C (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21 / 8234-21/8238 H01L 27/06 H01L 27/08 331 H01L 27/088-27/092

Claims (4)

(57) [Claims] 1. An insulator layer formed on a first conductivity type semiconductor substrate, a semiconductor layer formed on the insulator layer and constituting a semiconductor element, and an insulating film formed on the semiconductor layer. In a semiconductor integrated circuit having a plurality of contact plugs for electrically connecting the semiconductor layer and a metal wiring formed on the insulating film, a second integrated circuit formed in the first conductive type semiconductor substrate or on an upper surface thereof A contact plug connected to a first power source among the contact plugs, the contact plug penetrating the semiconductor layer and the insulator layer and reaching the first conductivity type semiconductor substrate; The contact plug connected to the power supply reaches the second conductivity type diffusion layer through the semiconductor layer and the insulator layer, and the contact plug not connected to the power supply passes through the insulator layer. Absent The semiconductor integrated circuit according to claim and. 2. An insulator layer formed on a first conductivity type semiconductor substrate, a semiconductor layer formed on the insulator layer and forming a semiconductor element, an insulating film formed on the semiconductor layer, In a semiconductor integrated circuit having a plurality of contact plugs for electrically connecting the semiconductor layer and a metal wiring formed on the insulating film, a second integrated circuit formed in the first conductive type semiconductor substrate or on an upper surface thereof A conductive type diffusion layer, wherein, of the contact plugs, the insulator layer below the semiconductor element connected to a contact plug connected to a first power supply is removed, and the lower part of the semiconductor layer is the 1
The insulator layer under the semiconductor layer connected to the contact plug connected to the second power supply is removed, and the lower part of the semiconductor layer contacts the second conductivity type diffusion layer. A semiconductor integrated circuit, wherein the insulator layer below the semiconductor layer connected to the contact plug not connected to a power supply is not removed. 3. The semiconductor integrated circuit according to claim 1, wherein the second conductivity type diffusion layer is located below the semiconductor layer connected to the second power supply. 4. The semiconductor device according to claim 1, further comprising a first conductivity type diffusion layer formed in or on the first conductivity type semiconductor substrate, wherein the first conductivity type diffusion layer is connected to the first power supply. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit is located below the layer.