JP2002094070A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and the manufacturing method for reducing parasitic capacitance, reducing element area and lowering the resistance of a terminal part for extracting a body potential. SOLUTION: This semiconductor device is provided with an embedded insulation film formed on a substrate, a channel formation region of a part of a first conductive body region B formed in the semiconductor layer of the upper layer, the source region S and a second conductive drain area D holding the channel formation region there between one of which is formed in a partially chipped shape compared to the other, a gate electrode G formed in the shape to cover the chipped part through a gate insulation film on the channel formation region, a terminal part BT which is a part of the body region B which is other than the lower part of the gate electrode G and connected to only one of the source region S and the drain region D, and a conductor layer formed on the semiconductor layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI (sili)
con on insulator or semico
The present invention relates to a semiconductor device in which a field effect transistor is formed on a substrate on an insulator (insulator) substrate and a method of manufacturing the same, and in particular, to a partially depleted MO on an SOI substrate.
S (metal oxide semiconductor)
or) a semiconductor device having a transistor formed thereon and a method for manufacturing the same.

[0002]

2. Description of the Related Art An SOI substrate has a silicon layer on a silicon substrate via a buried oxide film, and a transistor is formed on the silicon layer on the surface. For example, LOCOS (local oxidation of
When an element isolation region such as silicon is formed so as to reach a buried oxide film, elements are completely separated by the element isolation region and the buried oxide film. This allows
Soft errors are suppressed, and CMOS (complete
In principle, latch-up specific to a primary MOS transistor does not occur. Since the problem of latch-up, which has been a factor that hinders the miniaturization of CMOS, is solved, high integration of LSI becomes possible.

[0003] The transistor formed on the SOI substrate is:
The area of the pn junction is smaller than that of the transistor formed in the low concentration impurity diffusion layer (well) of the bulk silicon substrate. Therefore, the junction capacitance is reduced, and the delay time is reduced. Further, since the load capacity is reduced by reducing the junction capacity, the power required for charging and discharging the load capacity is also reduced. Further, in recent years, the quality of SOI substrates has been improved,
Due to the lower cost of manufacturing an I-substrate, mass production of an LSI using an SOI substrate is in progress.

[0004] MOS transistors formed on an SOI substrate are roughly classified into two types: a fully depleted type and a partially depleted type. A fully depleted MOS transistor has a silicon layer of, for example, 5
It is formed as thin as 0 nm or less, and operates in a state where the body region between the source region and the drain region is always depleted. On the other hand, a partially depleted MOS transistor has a state in which a silicon layer is formed as thick as 100 nm or more and an undepleted region exists at the bottom of the body region, that is, a state in which the depletion layer immediately below the channel does not reach the buried oxide film. Works with

A fully-depleted MOS transistor can greatly reduce the junction capacitance and has excellent sub-threshold characteristics, but a partially-depleted MOS transistor has a more fully depleted MOS transistor with respect to source / drain breakdown voltage. MOS transistor. However, in a partially depleted MOS transistor, it is necessary to fix the potential of the body region (body potential) in order to prevent the following kink phenomenon.

When electrons accelerated by an electric field collide with a crystal lattice, electrons and holes are generated (impact ionization phenomenon). Due to such an impact ionization phenomenon, holes are generated near the drain region of an n-channel MOS transistor (NMOS). In the case of a MOS transistor formed on a bulk silicon substrate, a well and a silicon substrate are in contact with each other and a pn junction is formed, whereas in the case of a MOS transistor formed on an SOI substrate, a body region is electrically floating. (Floatin
g) state.

Therefore, holes generated near the drain region accumulate in the body region and bias the body potential. As a result, the drain current increases and the current-voltage characteristics are disturbed (kink phenomenon). Under the condition where the kink phenomenon is observed, an output signal in which distortion is superimposed on an input signal is detected, particularly in an analog circuit. In addition, since an unstable operation occurs in a digital circuit, it is necessary to design a circuit so that a margin for noise is increased.

On the other hand, in the case of a fully depleted MOS transistor, the kink phenomenon does not occur because the potential barrier between the source and the body with respect to holes is low. However, N
A parasitic bipolar transistor having a source region, a body region, and a drain region of a MOS as an emitter region, a base region, and a collector region, respectively, is turned on using holes generated by the impact ionization phenomenon as a base current. As a result, as described above, the fully depleted MOS
In the transistor, the withstand voltage between the source and the drain is reduced.

As described above, a partially-depleted MOS transistor must be used with a fixed body potential.
The body potential of the MOS is made common to, for example, the source potential. FIG. 10 is an example of a top view of a conventional partially depleted NMOS. According to the layout pattern shown in FIG. 10, a T-shaped gate electrode (T gate) TG is formed.

As shown in FIG. 10, an n-type source region S and a drain region D are formed in a region surrounded by an element isolation region I. On the body region B between the source region S and the drain region D, a T gate TG is formed via a gate insulating film. A part of the body region B separated from the source region S and the drain region D by the T gate TG is a terminal portion BT for extracting a body potential.

The terminal portion BT contains a p-type impurity of a conductivity type opposite to that of the source region S and the drain region D, and further has, for example, a body contact BC in which a metal plug is embedded. The body contact BC is connected to the source contact SC via an upper wiring (not shown). As a result, the body potential is fixed at the source potential. A drain contact DC is formed in the drain region D, and a gate contact GC is formed in the T gate TG.

According to the above MOS transistor, FIG.
An extra gate / body capacitance C _GB is formed in the hatched portion of FIG. An extra gate / drain capacitance _CGD is also formed between the drain region D and the T gate TG. FIG. 12 shows an example of a layout pattern in which such gate / body capacitance and gate / drain capacitance are reduced.

The NMOS shown in FIG. 12 is equivalent to the N shown in FIG.
Similarly to the MOS, the region surrounded by the element isolation region I has an n-type source region S and a drain region D.
On the body region B between the source region S and the drain region D, a T gate TG is formed via a gate insulating film. The source region S, the drain region D, and the terminal portion which is a part of the body region B are separated from each other by the T gate TG. The terminal portion BT of the body region B is p
A body contact BC containing a mold impurity and having, for example, a metal plug embedded therein is formed in the terminal portion BT. The body contact BC is connected to the source contact SC via an upper wiring (not shown). As a result, the body potential is fixed at the source potential. A drain contact DC is formed in the drain region D, and a gate contact GC is formed in the T gate TG.

[0014]

However, also in the NMOS shown in FIG. 12, there is a problem of extra gate / body capacitance and gate / drain capacitance.
FIG. 13 shows the gate-body capacitance C of the NMOS shown in FIG.
_GB and gate / drain capacitance C _GD are shown. In the source region S and the drain region D, it is necessary to diffuse impurities of a conductivity type opposite to that of the body region B at a high concentration. Specifically, impurities are ion-implanted into the source region S and the drain region D using the resist as a mask.

As shown in FIGS. 10 and 12, generally, a gate length L between a source region S and a drain region D is determined.
_ga is designed according to the minimum pattern, that is, the design rule. The gate length L _gb of the T gate TG that separates the terminal portion BT of the body region B from the source region S or the drain region D is determined in consideration of the misalignment of the resist. _Therefore, it is designed to be larger than the minimum pattern or the gate length _Lga . Therefore, according to the MOS transistor shown in FIG. 12 or FIG.
Although the parasitic capacitance is smaller than that of the S transistor, it is difficult to reduce the gate length L _gb of the T gate TG to further reduce the parasitic capacitance.

In addition, when the area of the body contact BC formed in the terminal portion BT of the body region B is reduced, connection failure increases, so that it is relatively difficult to reduce the body contact area. Further, a margin for forming the body contact BC is required, which hinders the reduction of the area of the terminal portion BT of the body region B. Therefore, when the T gate TG is formed,
It becomes difficult to reduce the element area and increase the degree of integration of the LSI.

In addition to the above, there is another problem that the use of the T gate makes it impossible to utilize the design resources that have been conventionally accumulated for the semiconductor device formed on the bulk silicon substrate. Due to a layout change at a lower level such as a gate electrode, a layout change of an upper layer wiring and the like also becomes necessary. In addition, the process may need to be changed accordingly.

In order to solve the above-mentioned problem caused by forming the T gate, a layout pattern for forming a terminal portion of the body region so as to be connected to one of the source region and the drain region without forming the T gate is also provided. Conceivable. FIG. 14 shows an example of such a layout pattern.

According to the layout pattern of the NMOS shown in FIG. 14, a part of the source region S and a terminal portion BT of the body region connected to the body region B are formed in a shape protruding from the source region S. Terminal part BT in body region
In order to prevent the contact between the semiconductor region and the drain region D, the terminal portion BT of the body region is not formed near the drain region D in consideration of misalignment of the resist. Therefore, the width of the portion where the gate electrode G and the body region B overlap, the width between the source / drain, i.e. compared to the gate length L _g, becomes narrower toward the width W of the terminal portion BT of the body region B I have.

In the terminal portion BT of the body region B, a p-type impurity having a conductivity type opposite to that of the n-type source region S and the drain region D is diffused. As a result, a pn junction is formed between the source region S and the terminal portion BT of the body region B, and the body potential of the transistor is fixed at the source potential.

However, the terminal portion B of the body region B
When T has the shape shown in FIG. 14, there is a problem that the resistance of the terminal portion BT of the body region B becomes high. In order to prevent the terminal portion BT of the body region B from being in contact with the drain region D, the W
Must be set to about 1/2 of the minimum pattern. Normal,
Since the gate length L _g is formed with a minimum pattern, W is made approximately ½ of the gate length L _g. As described above, since the connection between the body region B between the source region S and the drain region D and the terminal portion BT of the body region B must be narrowed, the resistance of the terminal portion BT of the body region B increases. Become.

The present invention has been made in view of the above-described problems, and accordingly, the present invention provides a semiconductor device capable of reducing parasitic capacitance, reducing the element area, and reducing the resistance of the terminal portion of the body region. And a method for producing the same.

[0023]

To achieve the above object, a semiconductor device according to the present invention comprises a substrate, a buried insulating film formed on the substrate, and a semiconductor layer formed on the buried insulating film. A channel forming region that is a part of a first conductive type body region formed in the semiconductor layer; and a second conductive type source region and a drain region formed in the semiconductor layer with the channel forming region interposed therebetween. And a gate insulating film formed at least on the channel forming region, a gate electrode formed on the gate insulating film, and the body region other than the lower part of the gate electrode, wherein the source region and the drain region A terminal portion connected to only one of the regions, and a conductor layer formed on the semiconductor layer and connected to both the one region and the terminal portion; The region has a shape in which a portion close to both the terminal portion and the channel forming region is partially missing compared to the other region not connected to the body region, and the gate electrode covers the missing portion. Characterized by having a shape that

The semiconductor device of the present invention is preferably characterized in that the conductor layer includes a metal silicide layer formed on a surface of the semiconductor layer. The semiconductor device of the present invention
Preferably, a side wall made of an insulating film formed on a side surface of the gate electrode, and a second conductive type formed in the semiconductor layer below the side wall at a lower concentration than the source region or the drain region. And an LDD region containing impurities. In the semiconductor device of the present invention, preferably, the one region has a pentagonal shape in which one of the rectangular corners is divided into the defective portion by a straight line when viewed from the upper surface of the substrate, and the other region has a pentagonal shape. The region has a rectangular shape.

This makes it possible to prevent the kink phenomenon of the drain current by fixing the body potential of the transistor formed on the substrate in an electrically floating state to, for example, the source potential. Alternatively, it is possible to prevent the source / drain breakdown voltage from being lowered due to the operation of the parasitic bipolar transistor.

According to the semiconductor device of the present invention, the gate electrode extends at one end to one side of the source region and the drain region, and the lower portion becomes the body region. Therefore, even when the body region is formed so as not to be connected to the other of the source region and the drain region, the body region can be prevented from being narrowed between the channel formation region and the terminal portion of the body region. . This makes it possible to reduce the resistance for taking out the body potential.

When the source region and the terminal portion of the body region are connected by the layout pattern of the semiconductor device of the present invention, for example, a T gate is formed to connect the source region or the drain region to the terminal portion of the body region. It is possible to reduce the gate / body capacitance as compared with the case of separation. Further, it is also possible to substantially eliminate extra gate / drain capacitance.

According to the semiconductor device of the present invention, one of the source region and the drain region and the terminal portion of the body region are connected by the conductor layer formed on each surface, preferably a silicide layer. It is not necessary to form a contact hole for connecting the portions described above, and the element area can be reduced. In addition, there is no increase in the element area as in the case of forming a T gate, and there is no need for a significant layout change such as an upper layer wiring.

Further, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor layer on a substrate via a buried insulating film, and a step of forming a first conductive type body on the semiconductor layer. Forming a region, forming a gate insulating film on a channel forming region that is a part of the body region, and forming a gate electrode on the gate insulating film with one end extended to one side. A source region and a drain region of the second conductivity type in the semiconductor layer on both sides of the gate electrode, in a shape such that one region has a defective portion in an extended portion of the gate electrode as compared with the other region. Forming a part of the body region excluding the lower part of the gate electrode, the terminal part being connected to the one region and not being connected to the other region, and being connected to both the one region. The that conductor layer, characterized in that a step of forming on the semiconductor layer.

In the method for manufacturing a semiconductor device according to the present invention, preferably, the step of forming the conductor layer includes the step of forming a metal layer on the surface of the semiconductor layer and the step of reacting the metal layer by heat treatment. Forming a silicide layer. In the method for manufacturing a semiconductor device according to the present invention, preferably, the step of forming the source region and the drain region includes a step of covering at least the terminal portion with a resist, and the step of forming the semiconductor using the resist and the gate electrode as a mask. A step of ion-implanting a second conductivity type impurity into the layer and a step of removing the resist.

Preferably, in the method of manufacturing a semiconductor device according to the present invention, after the gate electrode is formed, at least the terminal portion is covered with a first resist, and the first resist and the gate electrode are masked. A second conductivity type impurity is ion-implanted into the semiconductor layer, and an LD having a lower impurity concentration than the source region and the drain region.
Forming a source region and a drain region, the method further comprising: forming a D region; removing the first resist; and forming a sidewall made of an insulating film on a side surface of the gate electrode. The step of covering at least the terminal portion with a second resist, the step of ion-implanting a second conductivity type impurity into the semiconductor layer using the second resist and the sidewall as a mask, 2) removing the resist.

As a result, it is possible to form a transistor with reduced body potential extraction resistance on an SOI substrate without adding a manufacturing process to the conventional manufacturing method.
Further, according to the method of manufacturing a semiconductor device of the present invention, it is possible to manufacture a transistor in which the gate-body capacitance is reduced, there is no extra gate-drain (or source) capacitance, and the element area is reduced. It is.

[0033]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1A is a top view of a semiconductor device of the present embodiment, FIG. 1B is a diagram showing a parasitic capacitance of the semiconductor device of FIG. 1A, and FIG. Aa ′ in FIG.
1 (d) is a cross-sectional view taken along line bb 'of FIG. 1 (a). The semiconductor device of the present embodiment has a SO
This is a partially depleted NMOS formed on the I substrate.

As shown in FIG. 1A, in the semiconductor device of this embodiment, the source region S is provided with respect to the gate electrode G (8).
(3) and the drain region D (4) are not symmetrical in shape,
The gate electrode G has a shape that is extended toward the source region S at one end in the gate width direction. The source region S and the drain region D are formed by ion-implanting n-type impurities using the gate electrode G as a mask. Therefore, n is formed below the portion where the gate electrode G extends to the source region S side.
The type impurity is not ion-implanted and becomes the body region B (5). A terminal portion BT of body region B is formed so as to be connected to both body region B and source region S under gate electrode G.

FIG. 1B shows the gate / body capacitance C _GB and the gate / drain capacitance C _GD of the semiconductor device of this embodiment. Comparing FIG. 1B with the conventional layout pattern shown in FIG. 13, it can be seen that extra gate / body capacitance C _GB and gate / drain capacitance C _GD are reduced.

According to the layout pattern of the semiconductor device of the present embodiment, the gate electrode G and the body region under the gate electrode G are extended toward the source region S, so that
The body region between the channel forming region between the drains and the body region terminal portion can be prevented from being narrowed.
This makes it possible to reduce the resistance for taking out the body potential.

Further, according to the layout pattern of the semiconductor device of the present embodiment, in order to prevent the terminal portion BT of the body region B from being in contact with the drain region D, the body region B is provided near the terminal portion BT of the body region B. The end of B is located closer to the gate electrode G than the boundary between the gate electrode G and the drain region D. Thereby, the gate electrode G
In the case where misalignment occurs between at least one of the gate electrode G and the body region B, the lower portion of the gate electrode G serves as a margin, and contact between the terminal portion BT of the body region B and the drain region D is prevented.

In the semiconductor device of the present embodiment, the terminal portion BT of the body region and the gate contact GC are formed on the side facing the channel formation region. It is possible to form the terminal portion BT of the body region B connected to the source region S and the gate contact GC on the same side with respect to the channel formation region. In that case, however, it is necessary to form the gate contact GC. The problem is that the gate-body capacitance C _GB increases. Therefore, it is preferable that the terminal portion BT of the body region B and the gate contact GC are formed on the side facing the channel forming region.

FIG. 1C is a cross-sectional view including the channel forming region of the semiconductor device of this embodiment. As shown in FIG. 1C, a buried oxide film 2 is formed on a silicon substrate 1, and a silicon layer including a source region 3, a drain region 4 and a body region 5 is formed thereon. Body region 5 is made of p-type silicon, and n-type impurities are diffused in source region 3 and drain region 4 at a high concentration. A silicon oxide film is formed on the buried oxide film 2 in the element isolation region 6.

A gate electrode 8 is formed on body region 5 with a gate insulating film 7 interposed therebetween. When a voltage is applied to the gate electrode 8, a channel is formed on the surface layer of the body region 5. These portions are covered with an interlayer insulating film 9 made of, for example, a silicon oxide film. A source contact 10 is formed in the interlayer insulating film 9 on the source region 3, and a drain contact 11 is formed in the interlayer insulating film 9 on the drain region 4. Source region 3, drain region 4
And a high melting point metal silicide layer 12 such as cobalt silicide or titanium silicide on the surface of the gate electrode 8.
Are formed.

On the other hand, regarding the terminal portion of the body region,
As shown in the sectional view of FIG. 1D, a buried oxide film 2 is formed on a silicon substrate 1, and a body region 5 made of p-type silicon and an element isolation region 6 made of a silicon oxide film are formed thereon. Have been. A gate electrode 8 is formed via a gate insulating film 7 so as to cover a part of the body region 5 and the element isolation insulating film 6 near the drain region.

The portion of the body region 5 where the gate electrode 8 is not formed is connected to the source region and becomes a terminal portion of the body region. A refractory metal silicide layer 12 is formed on the terminal portion of the body region and on the surface of the gate electrode 8. The refractory metal silicide layer 12 on the terminal portion of the body region is connected to the refractory metal silicide layer 12 on the source region, whereby the source region and the body region 5 are short-circuited. Further, the resistance of each region where the high melting point metal silicide layer 12 is formed is reduced.

Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. Figure 2
In FIG. 5, (a) is a top view, and (b) is a-
A cross-sectional view at a ′ and a cross-sectional view at bb ′ in FIG. To manufacture the semiconductor device of the present embodiment, first, as shown in FIG. 2A, an element isolation region I (6) is formed on the surface of an SOI substrate. The SOI substrate is, for example, SIMOX (separation by)
It can be formed by an implanted oxygen method or a bonding method. The SIMOX method is a method in which oxygen is ion-implanted with high energy into a silicon substrate and then a high-temperature heat treatment is performed to form a silicon oxide film inside the silicon substrate. In general, according to the SIMOX method, the variation in the thickness of the silicon layer can be reduced as compared with the bonding method in which two substrates are bonded and the surface is polished.

As shown in FIGS. 2B and 2C, a silicon layer including a body region 5 is formed on a silicon substrate 1 with a buried oxide film 2 interposed therebetween. The element isolation region 6 on the buried oxide film 2 is formed, for example, by LOCOS or ST.
I (shallow trench isolatio)
n). A p-type impurity is ion-implanted into the silicon layer other than the element isolation region 6. At this time, a well may be formed by ion-implanting impurities into the silicon substrate 1 under the buried oxide film 2. PMOS
In the case of (1), an n-type impurity is ion-implanted into the silicon layer other than the element isolation region 6 or into the lower silicon substrate 1.

Next, as shown in FIG. 3A, a gate electrode G (8) having a shape extending at one end is formed. As shown in FIGS. 3B and 3C, the gate electrode 8
Is formed on body region 5 via gate insulating film 7. As the gate insulating film 7, for example, a thermal oxide film formed on the surface of a silicon layer forming the body region 5 is used. Further, as the gate electrode G, for example, a polysilicon layer containing no impurity is formed by chemical vapor deposition (CVD).
Deposit by ical vapor deposition. Thereafter, using a resist as a mask, for example, reactive ion etching (RIE; reactive i) is performed.
By performing on etching, the gate electrode 8 and the gate insulating film 7 are formed.

Next, as shown in FIG. 4A, a resist PR (13) is formed so that an opening is formed on the body region excluding the potential extraction terminal portion. Using the resist PR as a mask, for example, arsenic (As) as a n-type impurity is ion-implanted at a high dose into the body region B except for the terminal portion. As a result, a source region S and a drain region D are formed. The gate electrode G is connected to the source region S at one end.
Since the shape is expanded to the side, no n-type impurity is ion-implanted below the gate electrode G, and the source region S and the drain region D do not have a symmetric structure with respect to the gate electrode G.

As shown in the sectional view of FIG. 4B, the source region 3 and the drain region 4 are formed in a self-aligned manner with respect to the gate electrode 8. On the other hand, the terminal portion of the body region is covered with the resist 13 as shown in the cross-sectional view of FIG. After the ion implantation of the n-type impurity, the resist PR is removed as shown in FIG.

Next, as shown in FIGS. 5B and 5C, a high melting point metal silicide layer 12 such as cobalt silicide or titanium silicide is formed on the surfaces of the source region 3, the drain region 4 and the gate electrode 8. To form In order to form the refractory metal silicide layer 12, first, a natural oxide film on the surface of the silicon layer or the gate polysilicon layer is removed by, for example, light etching using hydrofluoric acid. Subsequently, for example, cobalt is deposited to a thickness of about 10 nm by sputtering. Then, for example, RTA
(Rapid thermal annealing)
To form silicide on the silicon surface. Unreacted cobalt on the silicon oxide film can be removed using, for example, a solution containing sulfuric acid and aqueous hydrogen peroxide.

Thereafter, as shown in FIGS. 1C and 1D, a silicon oxide film, for example, is deposited as an interlayer insulating film 9 on the entire surface by CVD. Using a resist as a mask, for example, RIE is performed to form a contact hole in the interlayer insulating film 9 on the source region 3 and the drain region 4. Although not shown in the cross-sectional view, a contact hole for forming a gate contact GC is also formed in the interlayer insulating film 9 on the gate electrode 8.

For example, a tungsten plug is buried in the opening formed in the interlayer insulating film 9, and an upper wiring connected to the tungsten plug is formed. As a result, a source contact 10, a drain contact 11 and a gate contact are formed. Tungsten plugs
For example, it may be embedded in the contact hole via a barrier metal layer such as titanium (Ti). In addition, the upper wiring 1
A barrier metal layer may be formed between the layer 4 and the interlayer insulating film 9.

Through the above steps, the semiconductor device of the present embodiment is formed. In the method of manufacturing a semiconductor device according to the present embodiment, the body region 5 is made of n-type silicon and the source / drain regions are ion-implanted with, for example, BF ₂ as a p-type impurity to thereby form a p-channel MOS transistor (PMOS). Can be formed. In the case of forming a PMOS, one end of the gate electrode is extended to the drain region side, and a terminal portion of the body region is connected to the drain region.

(Embodiment 2) FIG. 6A is a top view of a semiconductor device of this embodiment, FIG. 6B is a cross-sectional view taken along aa 'of FIG. 6A, and FIG. ) Is b in FIG.
It is sectional drawing in -b '. In the semiconductor device of the present embodiment, the NMOS of the first embodiment is replaced with an LDD (lightly
The withstand voltage is improved by adopting a doped drain structure. As shown in FIG. 6A, a gate electrode G (8) has a sidewall SW made of an insulating film.
(15) is provided.

As shown in the sectional views of FIGS. 6B and 6C, a side wall 15 made of, for example, a silicon oxide film is formed on the side surface of the gate electrode 8. FIG. 6 (b)
As shown in FIG. 3, an LD containing an n-type impurity at a lower concentration than the source region 3 or the drain region 4 is provided below the sidewall 15 between the source region 3 and the drain region 4.
D region 16 is formed.

Hereinafter, a method of manufacturing the semiconductor device according to the present embodiment will be described. The method for manufacturing a semiconductor device according to the present embodiment includes:
The steps up to the step shown in FIG. 3 are common to the method of manufacturing the semiconductor device of the first embodiment. First, as shown in FIG. 2, a body region 5 and an element isolation region 6 are formed in a surface silicon layer of an SOI substrate. Subsequently, as shown in FIG.
And a gate electrode 8 are formed.

Next, as shown in FIG. 7A, a resist PR (17) is formed so that an opening is formed on the body region excluding the potential extraction terminal portion. As shown in FIG. 7B, for example, arsenic (As) is ion-implanted as an n-type impurity using the resist 17 as a mask. Thus, the LDD region 16 is formed. After that, the resist 17 is removed.

Next, as shown in FIG. 8A, a sidewall SW is formed on the side surface of the gate electrode G. In order to form the sidewall SW, a silicon oxide film is formed on the entire surface by, for example, CVD, and then etch back is performed. After that, open the body area except the terminal part,
The resist PR is formed again. As shown in FIG. 8B, for example, arsenic (As) is ion-implanted as an n-type impurity using the resist 13 as a mask. This allows
Source region 3 and drain region 4 having an n-type impurity concentration higher than LDD region 16 are formed in self-alignment with sidewall 15. Thereafter, as shown in FIG. 9A, the resist PR is removed.

Next, as shown in FIGS. 9B and 9C, the source region 3, the drain region 4 and the gate electrode 8 are formed.
A high melting point metal silicide layer 12 of, for example, cobalt silicide or titanium silicide is formed on the surface. The formation of the refractory metal silicide layer 12 can be performed in the same manner as in the first embodiment. The refractory metal silicide layer 12 on the source region 3 is connected to the refractory metal silicide layer 12 on the terminal of the body region 5. As a result, the source region 3 and the terminal portion of the body region 5 are short-circuited via the refractory metal silicide layer 12. Further, the refractory metal silicide layer 1
2 can be reduced in resistance.

According to the semiconductor device of this embodiment,
Since the sidewall 15 is formed, the refractory metal silicide layer 12 is not formed on the side surface of the gate electrode 8. Therefore, the refractory metal silicide layer 12 on the surface of the gate electrode 8 and the source region 3 or the drain region 4
Can be prevented from short-circuiting with the high-melting metal silicide layer 12 on the surface of the substrate.

Thereafter, for example, a silicon oxide film is formed on the entire surface as the interlayer insulating film 9, and the source contact 10, the drain contact 11, the upper wiring 14, and the like are formed in the same manner as in the first embodiment. (C)
The semiconductor device as shown in FIG.

According to the semiconductor device of the embodiment of the present invention, it is possible to reduce the gate-body capacitance and to reduce the resistance of the terminal portion of the body region. Further, according to the semiconductor device of the embodiment of the present invention, it is possible to prevent an increase in the element area and a significant layout change from the conventional semiconductor device. According to the method of manufacturing a semiconductor device according to the embodiment of the present invention, a MOS transistor having a small gate-body capacitance and a low-resistance terminal for extracting a body potential can be formed on an SOI substrate.

Embodiments of the semiconductor device and the method of manufacturing the same according to the present invention are not limited to the above description. For example, instead of using a single-layer polysilicon layer as the gate electrode 8, an electrode having a polycide structure in which, for example, a tungsten silicide layer is formed on the polysilicon layer can be used. Further, an offset insulating film can be formed over the gate electrode. In this case, the refractory metal silicide layer 12 is not formed on the gate electrode 8, but the refractory metal silicide layer 12 is formed above the terminal portions of the source region 3, the drain region 4 and the body region 5.
Source region 3 and body region 5 can be short-circuited via refractory metal silicide layer 12.

The layout pattern of the semiconductor device of the present invention can be applied not only to partially depleted MOS transistors but also to fully depleted MOS transistors. In the fully-depleted MOS transistor, the body potential is fixed to, for example, the source potential in the same manner as described above, thereby preventing a decrease in the source / drain breakdown voltage due to the parasitic bipolar transistor. In addition, various changes can be made without departing from the gist of the present invention.

[0063]

According to the semiconductor device of the present invention, the gate /
It is possible to reduce the capacitance between the bodies, reduce the element area, and reduce the resistance for taking out the body potential. According to the method for manufacturing a semiconductor device of the present invention, the gate-body capacitance is reduced, the element area is reduced, and the resistance for extracting the body potential is reduced without adding a manufacturing step to the conventional semiconductor device manufacturing method. It is possible to manufacture a reduced semiconductor device.

[Brief description of the drawings]

FIGS. 1A and 1B are plan views of a semiconductor device according to a first embodiment of the present invention, and FIG. 1C is a cross section taken along aa ′ of FIG. 1A. FIG. 1 (d) shows FIG.
It is sectional drawing in bb 'of (a).

FIG. 2A is a plan view illustrating a manufacturing step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
FIG. 2B is a cross-sectional view taken along line aa ′ of FIG.
FIG. 2C is a cross-sectional view taken along the line bb ′ of FIG.

FIG. 3A is a plan view showing a manufacturing step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention;
FIG. 3B is a cross-sectional view taken along aa ′ of FIG.
FIG. 3C is a cross-sectional view taken along the line bb ′ of FIG.

FIG. 4A is a plan view showing a manufacturing step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 4B is a cross-sectional view taken along line aa ′ of FIG.
FIG. 4C is a cross-sectional view taken along the line bb ′ of FIG.

FIG. 5A is a plan view showing a manufacturing step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG.
5B is a sectional view taken along a line aa ′ of FIG.
FIG. 5C is a cross-sectional view taken along the line bb ′ of FIG.

FIG. 6A is a plan view of a semiconductor device according to a second embodiment of the present invention, and FIG. 6B is a plan view of FIG.
FIG. 6C is a sectional view taken along line a ′ of FIG.
It is sectional drawing in b '.

FIG. 7A is a plan view illustrating a manufacturing step of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
FIG. 7B is a cross-sectional view taken along the line aa ′ of FIG.
FIG. 7C is a cross-sectional view taken along the line bb ′ of FIG.

FIG. 8A is a plan view illustrating a manufacturing step of a manufacturing method of a semiconductor device according to a second embodiment of the present invention, and FIG.
8B is a cross-sectional view taken along a line aa ′ of FIG.
FIG. 9C is a sectional view taken along line bb ′ of FIG.

FIG. 9A is a plan view illustrating a manufacturing step of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
9B is a cross-sectional view taken along a line aa ′ of FIG.
FIG. 10C is a cross-sectional view taken along the line bb ′ of FIG.

FIG. 10 is a plan view of a conventional semiconductor device.

FIG. 11 is a plan view showing a parasitic capacitance in the semiconductor device of FIG. 10;

FIG. 12 is a plan view of a conventional semiconductor device.

FIG. 13 is a plan view showing a parasitic capacitance in the semiconductor device of FIG. 12;

FIG. 14 is a plan view of a semiconductor device as a comparative example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate, 2 buried oxide film, 3 source region, 4 drain region, 5 body region, 6 element isolation region, 7 gate insulating film, 8 gate electrode, 9 interlayer insulating film, 10 ... Source contact, 11 ... Drain contact, 12 ... High melting point metal silicide layer, 13 ... Resist, 14 ... Upper layer wiring, 15 ... Side wall, 16 ... L
DD area, 17: resist.

Continued on the front page F-term (reference) 4M104 AA09 BB01 BB20 BB25 CC01 CC05 DD37 DD80 DD84 FF11 FF14 HH15 HH20 5F110 AA02 AA04 AA13 AA15 BB04 CC02 DD05 DD13 EE05 EE09 EE14 EE24 EE32 EE12 HM04 FF02 GG03 NN02 NN23 NN35 NN62 NN65 NN66 QQ17

Claims (8)

[Claims] A substrate, a buried insulating film formed on the substrate, a semiconductor layer formed on the buried insulating film, and a part of a first conductivity type body region formed on the semiconductor layer. A channel formation region, a second conductivity type source region and a drain region formed in the semiconductor layer with the channel formation region therebetween, a gate insulating film formed at least on the channel formation region, and the gate A gate electrode formed on an insulating film, a terminal part that is a part of the body region other than the lower part of the gate electrode, and is connected to only one of the source region and the drain region; A conductive layer formed to be connected to both the one region and the terminal portion, wherein the one region is compared to the other region not connected to the body region. It has a shape portion adjacent is partially defective in both the terminal portion and the channel formation region, a semiconductor device wherein the gate electrode has a shape covering the defect portion. 2. The semiconductor device according to claim 1, wherein said conductor layer includes a metal silicide layer formed on a surface of said semiconductor layer. 3. A side wall formed of an insulating film formed on a side surface of the gate electrode, and a second conductive type formed on the semiconductor layer below the side wall and having a lower concentration than the source region or the drain region. LDD containing light impurities (lightly
2. The semiconductor device according to claim 1, further comprising a doped drain region. 4. The one area has a pentagonal shape in which one of the rectangular corners is divided into the missing portion by a straight line when viewed from the top surface of the substrate, and the other area has a rectangular shape. 2. The semiconductor device according to claim 1, comprising: 5. A step of forming a semiconductor layer on a substrate via a buried insulating film, a step of forming a first conductivity type body region in the semiconductor layer, and a channel forming region which is a part of the body region. A step of forming a gate insulating film thereon; a step of forming a gate electrode on the gate insulating film with one end extended to one side; and a source of a second conductivity type in the semiconductor layer on both sides of the gate electrode. Forming a region and a drain region in a shape such that one region has a deficient portion in an extended portion of the gate electrode as compared with the other region; and a part of the body region excluding the lower portion of the gate electrode. Forming a conductive layer connected to both the one region and the terminal region connected to the one region and not connected to the other region on the semiconductor layer. The method of production. 6. The method according to claim 1, wherein forming the conductor layer includes forming a metal layer on the surface of the semiconductor layer, and reacting the metal layer by heat treatment to form a metal silicide layer. 6. The method for manufacturing a semiconductor device according to item 5. 7. The step of forming the source region and the drain region includes a step of covering at least the terminal portion with a resist, and a step of applying a second conductivity type impurity to the semiconductor layer using the resist and the gate electrode as a mask. The method of manufacturing a semiconductor device according to claim 5, further comprising: performing ion implantation; and removing the resist. 8. A step of covering at least the terminal portion with a first resist after the formation of the gate electrode, and using the first resist and the gate electrode as a mask to implant a second conductivity type impurity into the semiconductor layer. Ion implantation,
LDD (lightly doped drain) having an impurity concentration lower than that of the source region and the drain region.
in) a step of forming a region, a step of removing the first resist, and a step of forming a sidewall made of an insulating film on a side surface of the gate electrode, wherein the source region and the drain region are Forming, at least, a terminal portion covered with a second resist; ion-implanting a second conductivity type impurity into the semiconductor layer using the second resist and the sidewall as a mask; 6. The method for manufacturing a semiconductor device according to claim 5, comprising a step of removing the second resist.