JP2001094061A - Semiconductor intergrated-circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated-circuit device of an SOI struc ture which can reduce the chip area. SOLUTION: A resistance diffusion region 7 is formed inside a semiconductor substrate 1 under a first MOS transistor 4 and a second MOS transistor 5, so as to be isolated by an insulating film 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having an SOI structure.

[0002]

2. Description of the Related Art SOI (silicon on ins)
ulrator technology is a technology for manufacturing high-speed MOS circuits and CMOS circuits. According to such technology,
A layer of a semiconductor material such as silicon is deposited on the insulating layer, so that capacitor coupling between the semiconductor layer and the underlying insulating layer and the substrate is reduced. Field-effect transistors and other devices manufactured on thin semiconductor material layers are capable of high-speed switching operations. The SOI technique uses a semiconductor material layer 3 disposed on an insulating film 2 on a supporting bulk wafer 1 as shown in FIG. S as described above
The OI substrate is SIMOX (separation by
implanted oxygen) SOI substrate or B
E (bonded and etchback) SOI
One of the substrates. Generally, an SOI structure includes a buried oxide film, which is a silicon oxide film, and a single crystal silicon film on a single crystal silicon substrate.

FIG. 1 is a sectional view of a conventional semiconductor integrated circuit device having an SOI structure. An integrated circuit (CMOS inverter circuit) 10 is formed on an SOI substrate. A resistive diffusion region (resistor diffusion region) is formed in the substrate 1.
on) 7 is formed. A semiconductor integrated circuit device having a conventional SOI structure is disclosed in U.S. Pat. S. pat. No. 5,7
86,616 "SEMICONDUCTOR INTER
GRATED CIRCUIT HAVINGAN S
OI Structure, PROVIDED WIT
The resistance diffusion region 7 is formed by implanting impurities into the semiconductor substrate 1 and connected to the signal input terminal IN and the integrated circuit 10 through a metal contact.

[0004]

However, since the resistance diffusion region 7 is formed below the SOI substrate on which elements such as transistors, capacitors or diodes are not formed, the layout area of the semiconductor integrated circuit device is increased. It becomes a factor to make it.

[0005] The present invention has been made in view of the above points,
It is an object of the present invention to provide a semiconductor integrated circuit device capable of reducing a chip area.

[0006]

According to one aspect of the present invention, a semiconductor integrated circuit device includes an integrated circuit and a diffusion region.
The integrated circuit is formed on a semiconductor material layer formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween and on the semiconductor material layer. The diffusion region is formed on the semiconductor substrate below the integrated circuit with the second conductivity type. In a preferred form, the diffusion region is used as a resistor.

According to another feature of the present invention, a semiconductor integrated circuit device includes a semiconductor substrate, a semiconductor material layer, a MOS circuit, and a diffusion region. The semiconductor material layer is formed on the semiconductor substrate with an insulating layer therebetween. The MOS circuit is formed on and above the semiconductor material layer. The diffusion region is formed on the semiconductor substrate below the MOS circuit with the second conductivity type. As a preferred form,
The diffusion region is used as a resistor.

According to still another aspect of the present invention, a semiconductor integrated circuit device includes a semiconductor substrate, a semiconductor material layer, a first MOS transistor.
A transistor, a second MOS transistor, and a diffusion region. The semiconductor material layer is formed on the semiconductor substrate with an insulating layer therebetween. The first MOS transistor is formed on and above the semiconductor material layer, and has a gate, a source connected to the first voltage, and a drain connected to the signal output terminal. The second MOS transistor is also formed on and above the semiconductor material layer, and has a gate connected to the gate of the first MOS transistor, a drain connected to the drain of the first MOS transistor, and a source connected to the second voltage. The diffusion region is formed in the semiconductor substrate below the first and second MOS transistors, and one side is connected to a signal input terminal and the other side is commonly connected to gates of the first and second MOS transistors. In a preferred form, the diffusion region is used as a resistor.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to FIGS.

Referring to FIG. 2, a semiconductor integrated circuit device having a novel SOI structure according to an embodiment of the present invention is:
A semiconductor material layer formed on a semiconductor substrate with an insulating film interposed therebetween, and a semiconductor material layer and a MOS formed thereon;
And a resistance diffusion region formed in the semiconductor substrate below the MOS circuit. According to such a semiconductor integrated circuit device, the layout area of the semiconductor integrated circuit device can be reduced since the resistor is formed below the MOS circuit as compared with the conventional case where the resistor is formed in the semiconductor substrate on the side of the MOS circuit.

In the following description, an equivalent circuit diagram of the semiconductor integrated circuit device of FIG. 4 will be taken as an example for a more complete understanding of the present invention. In the following description, in the drawings, the same or similar reference numerals and symbols indicate the same or similar components as much as possible.

FIG. 2 is a vertical sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention. Referring to FIG. 2, a semiconductor integrated circuit device having an SOI structure includes a semiconductor substrate 1, which is a handle wafer, an insulating film 2, a semiconductor material layer 3, a gate electrode, a source region, and a drain region. 1st and 2nd MOS
It comprises transistors 4, 5 (integrated circuit 10) and resistance diffusion region 7.

A semiconductor material layer 3 is formed on a semiconductor substrate 1 with an insulating film 2 interposed therebetween, and gate electrodes 4a and 5a of the first and second MOS transistors 4 and 5 are formed on the semiconductor material layer 3 by a gate oxide film ( (Not shown).

At this time, the semiconductor substrate 1 is formed into an n-type or a p-type. The insulating film 2 functions as a buried oxide film of the SOI substrate. Source and drain regions (not shown) are formed in the semiconductor material layer 3 below both sides of the gate electrodes 4a and 5a.

The resistance diffusion region 7 is formed in the semiconductor substrate 1 below the first and second MOS transistors 4 and 5 with the insulating film 2 interposed therebetween.

The method of manufacturing a semiconductor integrated circuit device having the above-described SOI structure is as follows. In this example, a method for manufacturing a resistor connected between a CMOS inverter circuit and a signal input terminal IN will be described.

Referring to FIG. 2, first, an SOI substrate is prepared. At this time, as an SOI substrate, an SI is formed by injecting oxygen into the entire surface of a bulk (or a semiconductor substrate) and performing heat treatment.
After forming an oxide film on a MOX SOI substrate or bulk, an upper substrate is formed on the oxide film.
Con Direct Bonding (SOI) substrate or the like can be used. In the present invention, an SOI substrate having an insulating film (buried oxide film) 2 and a semiconductor material layer 3 formed on a semiconductor substrate 1 is prepared.

Next, the PMOS transistor 4 and the NMOS
A resistance diffusion region 7 is formed under the region where the transistor 5 is formed.
In order to form GaAs, low-concentration impurity ions such as P (phosphorus) are ion energy of 400 Kev and 5.0 × 10 ¹²
It is implanted into the semiconductor substrate 1 with a doping concentration of cm ³ (reference number 7a ′).

On the semiconductor material layer 3, a PMOS and an NMO
Gate electrodes 4a and 5a of the S transistor are formed, and source / drain regions (not shown) are formed by an ion implantation process.

The resistance diffusion region 7 is connected to the signal input terminal IN and the MOS.
In order to connect to the transistors 4 and 5, the insulating film 2 on the lower side of both sides of the MOS transistor is etched to form an opening 6. Then, a high concentration of impurity ions, for example, As (arsenic) is implanted into the semiconductor substrate 1 through the opening 6 at an ion energy of 60 KeV and a doping concentration of 5.0 × 10 ¹⁵ cm ³ (reference numeral 7b ′). Resistance is reduced.

Finally, after forming the intermediate insulating film 8, the resistance diffusion region 7, the MOS transistors 4, 5 and the power supply VD
D, metal contacts 9.1 for interconnection with VSS
1, 12, 13 are formed. That is, one of the high-concentration diffusion regions 7b 'in the resistance diffusion region 7 is connected to the signal input terminal IN, and the other is commonly connected to the gate electrodes 4a and 5a of the MOS transistors 4 and 5. In addition, PMO
The source of the S transistor 4 is connected to VDD, and the drain is connected to the signal output terminal OUT together with the drain of the NMOS transistor 5. Further, the source of the NMOS transistor 5 is connected to VSS.

FIG. 3 is a plan view of the semiconductor integrated circuit device according to the embodiment of the present invention, wherein a resistor is provided below the region where the gate electrodes 4a, 5a of the PMOS and NMOS transistors 4, 5 and the source and drain regions are formed. Diffusion area 7
It can be seen that is formed.

FIG. 4 is an equivalent circuit diagram of the semiconductor integrated circuit device of FIG. 3 according to the embodiment of the present invention. The resistor R is constituted by the resistance diffusion region 7 of FIG. 3, and the PMOS transistor 4 is the gate electrode of FIG. 4a and a semiconductor material layer 3 below both sides thereof
The NMOS transistor 5 includes a gate electrode 5a and a source / drain region in the semiconductor material layer 3 below both sides of the gate electrode 5a.

As described above, the semiconductor integrated circuit device according to the embodiment of the present invention has the resistance diffusion region formed at the lower portion, so that the layout area of the semiconductor integrated circuit device is smaller than that of the semiconductor integrated circuit device of FIG. Is greatly reduced.

Although the circuit according to the present invention has been described above, the above is only an example, and the present invention can be variously modified without departing from the technical idea of the present invention.

[0026]

As described above, according to the present invention, the layout area of the semiconductor integrated circuit device can be reduced by forming the resistance region below the integrated circuit formed on the SOI substrate.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device having an SOI structure according to the prior art.

FIG. 2 is a sectional view of a semiconductor integrated circuit device having an SOI structure according to the present invention.

FIG. 3 is a plan view of the semiconductor integrated circuit device of FIG. 2 as viewed from above.

FIG. 4 is an equivalent circuit diagram of the semiconductor integrated circuit device according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 Semiconductor material layer 4 PMOS transistor 5 NMOS transistor 4a, 5a Gate electrode 7 Resistance diffusion area 10 Integrated circuit

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 27/08 331 H01L 29/78 613A 29/786 626C

Claims (6)

[Claims] A semiconductor material layer formed on a semiconductor substrate of a first conductivity type with an insulating film interposed therebetween; an integrated circuit formed on the semiconductor material layer and an upper portion thereof; A semiconductor integrated circuit device comprising: a formed second conductivity type diffusion region. 2. The semiconductor integrated circuit device according to claim 1, wherein said diffusion region is used as a resistor. 3. A semiconductor substrate of a first conductivity type; a semiconductor material layer formed on the semiconductor substrate with an insulating film interposed therebetween; a MOS circuit formed on the semiconductor material layer and an upper portion thereof; A second conductive type diffusion region formed on a semiconductor substrate below the circuit. 4. The semiconductor integrated circuit device according to claim 3, wherein said diffusion region is used as a resistor. 5. A semiconductor substrate of a first conductivity type, a semiconductor material layer formed on the semiconductor substrate with an insulating film interposed therebetween, a semiconductor material layer formed on and above the semiconductor material layer, and a gate, a first
A first MOS transistor having a source connected to a voltage and a drain connected to a signal output terminal; a gate similarly formed on the semiconductor material layer and over the first MOS transistor, connected to a gate of the first MOS transistor; A second MO having a drain connected to the drain of the transistor and a source connected to the second voltage
An S transistor, and a second conductivity type formed in the semiconductor substrate below the first and second MOS transistors, one side being connected to a signal input terminal and the other side being commonly connected to gates of the first and second MOS transistors. A semiconductor integrated circuit device comprising: a diffusion region. 6. The semiconductor integrated circuit device according to claim 5, wherein said diffusion region is used as a resistor.