KR20010017814A - A semiconductor integrated circuit having a silicon on insulator structure - Google Patents
A semiconductor integrated circuit having a silicon on insulator structure Download PDFInfo
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- KR20010017814A KR20010017814A KR1019990033511A KR19990033511A KR20010017814A KR 20010017814 A KR20010017814 A KR 20010017814A KR 1019990033511 A KR1019990033511 A KR 1019990033511A KR 19990033511 A KR19990033511 A KR 19990033511A KR 20010017814 A KR20010017814 A KR 20010017814A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 239000012212 insulator Substances 0.000 title abstract description 3
- 229910052710 silicon Inorganic materials 0.000 title description 4
- 239000010703 silicon Substances 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 238000009792 diffusion process Methods 0.000 claims abstract description 33
- 239000000463 material Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- -1 As (Arsenic) Chemical class 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 집적 회로에 관한 것으로서, 더 구체적으로는 SOI 구조를 갖는 반도체 집적 회로에 관한 것이다.The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having an SOI structure.
SOI (silicon on insulator)기술은 고속 MOS 회로와 CMOS 회로들을 제조하기 위한 기술이다. 이런 기술에 따르면, 실리콘과 같은 반도체 물질층이 절연막 상에 증착되어 반도체 물질층과 그 하부의 절연막 및 기판 사이의 커패시터 커플링이 감소하게 된다. 얇은 반도체 물질층에 제조되는 전계 효과 트랜지스터들과 다른 소자들은 고속 스위칭 동작이 가능하다. SOI 기술은 지지 벌크 웨이퍼 (1)상의 절연막(2) 위에 배치되는 반도체 물질층(3)을 사용한다. 상술한 바와 같은 SOI 기판은 SIMOX(separation by implanted oxygen) SOI 기판 또는 BE(bonded and etchback) SOI 기판 중 어느 하나이다. 일반적으로, SOI 구조는 단결정 실리콘 기판에 실리콘 산화막인 베리드(buried) 산화막 위의 단결정 실리콘막을 포함한다.Silicon on insulator (SOI) technology is a technology for manufacturing high-speed MOS circuits and CMOS circuits. According to this technique, a layer of semiconductor material, such as silicon, is deposited on the insulating film to reduce capacitor coupling between the semiconductor material layer and the insulating film and substrate below it. Field effect transistors and other devices fabricated in a thin layer of semiconductor material enable fast switching operation. SOI technology uses a semiconductor material layer 3 disposed over an insulating film 2 on a supporting bulk wafer 1. The SOI substrate as described above is either a separation by implanted oxygen (SIMOX) SOI substrate or a bonded and etchback (BE) SOI substrate. In general, the SOI structure includes a single crystal silicon film on a buried oxide film which is a silicon oxide film on a single crystal silicon substrate.
도 1은 종래의 SOI 구조를 갖는 반도체 집적 회로의 단면도로서, SOI 기판 상에 집적 회로(CMOS 인버터 회로)가 형성되어 있고, 상기 집적 회로 (10)와 인접하여 반도체 기판 (1) 내에 저항 확산 영역 (resistor diffusion region)(7)이 형성되어 있다. 종래의 SOI 구조를 갖는 반도체 집적 회로는 U.S. Pat. No. 5,786,616 "SEMICONDUCTOR INTEGRATED CIRCUIT HAVING AN SOI STRUCTURE, PROVIDED WITH A PROTECTIVE CIRCUIT"에 개시되어 있다. 상기 저항 확산 영역 (7)은 반도체 기판 (1)에 불순물을 주입함으로써 형성되며, 금속 콘택을 통해 신호 입력단 (IN)과 집적 회로 (10)에 연결된다. 그러나 저항 확산 영역(7)은 트랜지스터, 커패시터 또는 다이오드 등과 같은 소자가 형성되어 있지 않은 SOI 기판 하부에 형성되기 때문에, 반도체 집적 회로의 레이아웃 면적을 증가시키는 요인이 된다.1 is a cross-sectional view of a semiconductor integrated circuit having a conventional SOI structure, in which an integrated circuit (CMOS inverter circuit) is formed on an SOI substrate, and a resistive diffusion region in the semiconductor substrate 1 is adjacent to the integrated circuit 10. (resistor diffusion region) 7 is formed. A semiconductor integrated circuit having a conventional SOI structure is U.S. Pat. No. 5,786,616 to "SEMICONDUCTOR INTEGRATED CIRCUIT HAVING AN SOI STRUCTURE, PROVIDED WITH A PROTECTIVE CIRCUIT." The resistive diffusion region 7 is formed by injecting impurities into the semiconductor substrate 1 and is connected to the signal input terminal IN and the integrated circuit 10 through a metal contact. However, since the resistive diffusion region 7 is formed under the SOI substrate where no devices such as transistors, capacitors, or diodes are formed, it becomes a factor for increasing the layout area of the semiconductor integrated circuit.
따라서, 본 발명의 목적은 상술한 제반 문제점을 해결하기 위해 제안된 것으로, 칩 면적을 줄일 수 있는 반도체 집적 회로를 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a semiconductor integrated circuit capable of reducing chip area.
도 1은 종래 기술에 따른 SOI 구조를 갖는 반도체 집적 회로의 단면도 및;1 is a cross-sectional view of a semiconductor integrated circuit having a SOI structure according to the prior art;
도 2는 본 발명에 따른 SOI 구조를 갖는 반도체 집적 회로의 단면도;2 is a cross-sectional view of a semiconductor integrated circuit having an SOI structure in accordance with the present invention;
도 3은 도 2의 반도체 집적 회로를 상부에서 바라본 평면도 및;3 is a plan view from above of the semiconductor integrated circuit of FIG. 2;
도 4는 본 발명의 실시예에 따른 반도체 집적 회로의 등가 회로도이다.4 is an equivalent circuit diagram of a semiconductor integrated circuit according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1 : 기판 2 : 절연막1 substrate 2 insulating film
3 : 반도체 물질층 4 : PMOS 트랜지스터3: semiconductor material layer 4: PMOS transistor
5 : NMOS 트랜지스터 4a, 5a : 게이트 전극5: NMOS transistor 4a, 5a: gate electrode
상술한 바와 같은 본 발명의 목적을 달성하기 위한 본 발명의 특징에 의하면, 반도체 집적 회로 장치는 집적 회로 및 확산층을 포함한다. 상기 집적 회로는 제 1 도전형의 반도체 기판 상에 절연막을 사이에 두고 형성된 반도체 물질층, 상기 반도체 물질층과 그 상부에 형성된다. 그리고 상기 확산층은 상기 집적 회로 하부의 반도체 기판에 형성된다.According to a feature of the present invention for achieving the object of the present invention as described above, a semiconductor integrated circuit device includes an integrated circuit and a diffusion layer. The integrated circuit is formed on a semiconductor material layer formed over an insulating film on a semiconductor substrate of a first conductivity type, the semiconductor material layer, and an upper portion thereof. The diffusion layer is formed on a semiconductor substrate under the integrated circuit.
바람직한 실시예에 있어서, 상기 확산층은 저항으로 사용된다.In a preferred embodiment, the diffusion layer is used as a resistor.
본 발명의 다른 특징에 의하면, 반도체 집적 회로 장치는 반도체 기판, 반도체 물질층, MOS 회로 및 확산층을 포함한다. 상기 반도체 물질층은 상기 반도체 기판 상에 절연막을 사이에 두고 형성된다. 상기 MOS 회로는 상기 반도체 물질층과 그 상부에 형성된다. 그리고 상기 확산층은 상기 MOS 회로 하부의 반도체 기판에 형성된 제 2 도전형의 확산층을 포함한다.According to another feature of the invention, a semiconductor integrated circuit device comprises a semiconductor substrate, a semiconductor material layer, a MOS circuit and a diffusion layer. The semiconductor material layer is formed on the semiconductor substrate with an insulating film therebetween. The MOS circuit is formed on and above the semiconductor material layer. The diffusion layer includes a second conductivity type diffusion layer formed on the semiconductor substrate under the MOS circuit.
바람직한 실시예에 있어서, 상기 확산층은 저항으로 사용된다.In a preferred embodiment, the diffusion layer is used as a resistor.
본 발명의 또 다른 특징에 의하면, 반도체 집적 회로 장치는 반도체 기판, 반도체 물질층, 제 1 MOS 트랜지스터, 제 2 MOS 트랜지스터 그리고 확산층을 포함한다. 상기 반도체 막은 반도체 기판 상에 절연막을 사이에 두고 형성된다. 제 1 MOS 트랜지스터는 상기 반도체 물질층과 그 상부에 형성되고, 전기적으로 신호 입력 단자에 연결되는 게이트, 제 1 전압에 연결되는 소오스 및 신호 출력 단자에 연결되는 드레인을 갖는다. 상기 제 2 MOS 트랜지스터는 제 1 MOS 트랜지스터의 게이트에 연결되는 게이트, 상기 제 1 MOS 트랜지스터의 드레인에 연결되는 드레인 및 제 2 전압에 연결되는 소오스를 갖는다. 그리고 상기 확산층은 상기 제 1 및 제 2 MOS 트랜지스터 하부의 반도체 기판 내에 형성되고, 일측이 상기 신호 입력 단자에 연결되고 타측이 상기 제 1 및 제 2 MOS 트랜지스터의 게이트들에 공통으로 연결된다.According to another feature of the invention, a semiconductor integrated circuit device comprises a semiconductor substrate, a semiconductor material layer, a first MOS transistor, a second MOS transistor and a diffusion layer. The semiconductor film is formed on a semiconductor substrate with an insulating film therebetween. A first MOS transistor is formed on the semiconductor material layer and above, and has a gate electrically connected to a signal input terminal, a source connected to a first voltage, and a drain connected to a signal output terminal. The second MOS transistor has a gate connected to the gate of the first MOS transistor, a drain connected to the drain of the first MOS transistor, and a source connected to the second voltage. The diffusion layer is formed in a semiconductor substrate under the first and second MOS transistors, one side of which is connected to the signal input terminal and the other side of which is commonly connected to the gates of the first and second MOS transistors.
바람직한 실시예에 있어서, 상기 확산층은 저항으로 사용된다.In a preferred embodiment, the diffusion layer is used as a resistor.
(실시예)(Example)
이하 본 발명에 따른 실시예를 첨부된 도면 도 2 내지 도 4를 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4.
도 2를 참조하면, 본 발명의 실시예에 따른 신규한 SOI 구조를 갖는 반도체 집적 회로는, 반도체 기판 상에 절연막을 사이에 두고 형성된 반도체 물질층과 상기 반도체 물질층과 그 상부에 형성된 MOS 회로 그리고 상기 MOS 회로 하부의 반도체 기판 내에 형성된 저항 확산 영역을 포함한다. 이러한 반도체 집적 회로에 의해서, 저항이 MOS 회로 측면의 반도체 기판 내에 형성되던 것에 비해 MOS 회로 아래에 형성되므로 반도체 집적 회로의 레이아웃 면적이 줄어들게 된다.Referring to FIG. 2, a semiconductor integrated circuit having a novel SOI structure according to an embodiment of the present invention includes a semiconductor material layer formed over an insulating layer on a semiconductor substrate, a MOS circuit formed on the semiconductor material layer, and an upper portion thereof. And a resistive diffusion region formed in the semiconductor substrate under the MOS circuit. By such a semiconductor integrated circuit, since the resistance is formed below the MOS circuit as compared with that formed in the semiconductor substrate on the side of the MOS circuit, the layout area of the semiconductor integrated circuit is reduced.
다음의 설명에서는 본 발명의 보다 철저한 이해를 제공하기 위해 도 4의 반도체 집적 회로의 등가 회로도를 예로 들어 한정되고 자세하게 설명된다. 이후의 설명에서 도면들 중 동일하거나 유사한 참조 번호 및 부호는 가능한한 동일하거나 유사한 구성 요소를 나타낸다.In the following description, the equivalent circuit diagram of the semiconductor integrated circuit of FIG. 4 is limited and described in detail in order to provide a more thorough understanding of the present invention. In the following description, the same or similar reference numerals and signs in the drawings represent the same or similar components as much as possible.
도 2는 본 발명의 실시예에 따른 반도체 집적 회로의 수직 단면도이다.2 is a vertical cross-sectional view of a semiconductor integrated circuit according to an embodiment of the present invention.
도 2를 참조하면, SOI 구조를 갖는 반도체 집적 회로는, 핸들 웨이퍼(handle wafer)인 반도체 기판 (1), 절연막 (2), 반도체 물질층 (3), 게이트 전극, 소오스 영역 및 드레인 영역을 각각 갖는 제 1 및 제 2 MOS 트랜지스터 (4, 5) 그리고 저항 확산 영역 (7)을 포함하여 구성된다.Referring to FIG. 2, a semiconductor integrated circuit having an SOI structure includes a semiconductor wafer 1, an insulating film 2, a semiconductor material layer 3, a gate electrode, a source region, and a drain region, each of which is a handle wafer. And first and second MOS transistors 4 and 5 having a resistive diffusion region 7.
상기 반도체 물질층 (3)은 상기 반도체 기판 (1) 상에 절연막 (2)을 사이에 두고 형성되고, 상기 제 1 및 제 2 MOS 트랜지스터 (4, 5)의 게이트 전극들 (5a, 4a)은 상기 반도체 물질층 (3) 상에 게이트 산화막(미도시됨)을 사이에 두고 형성된다.The semiconductor material layer 3 is formed on the semiconductor substrate 1 with an insulating film 2 interposed therebetween, and gate electrodes 5a and 4a of the first and second MOS transistors 4 and 5 are formed. It is formed on the semiconductor material layer 3 with a gate oxide film (not shown) interposed therebetween.
이때, 상기 반도체 기판 (1)은 n형 또는 p형으로 형성되고, 본 발명의 실시예에서는 p형으로 한정하여 상세히 설명한다. 상기 절연막 (2)은 SOI 기판의 베리드 산화막(buried oxide)으로 작용한다. 상기 소오스 영역 및 드레인 영역(미도시됨)은 상기 게이트 전극 (4a, 5a) 양측 하부의 반도체 물질층 (3)내에 형성된다.At this time, the semiconductor substrate 1 is formed of n-type or p-type, and in the embodiment of the present invention will be described in detail limited to p-type. The insulating film 2 serves as a buried oxide of the SOI substrate. The source region and the drain region (not shown) are formed in the semiconductor material layer 3 under both sides of the gate electrodes 4a and 5a.
상기 저항 확산 영역 (7)은 절연막 (2)을 사이에 두고 상기 제 1 및 제 2 MOS 트랜지스터 하부의 반도체 기판 (1) 내에 형성되어 있다.The resistive diffusion region 7 is formed in the semiconductor substrate 1 under the first and second MOS transistors with the insulating film 2 therebetween.
상술한 바와 같은 SOI 구조를 갖는 반도체 집적 회로의 제조 방법은 다음과 같다. 여기서, CMOS 인버터 회로 및 신호 입력단(IN) 사이에 연결되는 저항의 제조 방법을 설명한다.A method of manufacturing a semiconductor integrated circuit having the SOI structure as described above is as follows. Here, a method of manufacturing a resistor connected between the CMOS inverter circuit and the signal input terminal IN will be described.
다시 도 2를 참조하면, 먼저 SOI 기판이 준비된다. 이때, 상기 SOI 기판으로서, 벌크(또는 반도체 기판) 전면에 산소를 주입하고 열처리하여 형성한 SIMOX SOI 기판 또는 상기 벌크 상에 산화막을 형성한 후 상기 산화막 상에 상부 기판을 형성한 SDB(Silicon Direct Bonding) SOI 기판 등이 사용될 수 있다. 본 발명에서는 그 중 반도체 기판 (1)상에 절연막(베리드 산화막)(2) 및 반도체 물질층 (3)이 형성된 SOI 기판이 준비된다.Referring again to FIG. 2, first, an SOI substrate is prepared. In this case, as the SOI substrate, a SIMOX SOI substrate formed by injecting oxygen into a bulk (or semiconductor substrate) and heat-treated, or an SDB (Silicon Direct Bonding) in which an upper substrate is formed on the oxide film after an oxide film is formed on the bulk. ) SOI substrate and the like can be used. In the present invention, an SOI substrate having an insulating film (bury oxide film) 2 and a semiconductor material layer 3 formed thereon is prepared on the semiconductor substrate 1.
다음, PMOS 트랜지스터 (4)와 NMOS 트랜지스터 (5)가 형성될 영역 하부에 저항 확산 영역 (7)을 형성하기 위해 저농도의 불순물 이온 예를 들어, P(Phosphorous)가 400Kev의 이온 에너지와 5.0×1012㎤ 의 도핑 농도로 반도체 기판(1)에 주입된다(참조 번호 7b').Next, in order to form the resistive diffusion region 7 under the region where the PMOS transistor 4 and the NMOS transistor 5 are to be formed, a low concentration of impurity ions, for example, P (Phosphorous) has an ion energy of 400Kev and 5.0 × 10.12Cm 3 Is injected into the semiconductor substrate 1 at a doping concentration of (ref. 7b ').
상기 반도체 물질층 (3)상에 PMOS 및 NMOS 트랜지스터의 게이트 전극들 (4a, 5a)이 형성되고, 이온 주입공정에 의해 소오스/드레인 영역(미도시됨)이 형성된다.Gate electrodes 4a and 5a of PMOS and NMOS transistors are formed on the semiconductor material layer 3, and source / drain regions (not shown) are formed by an ion implantation process.
상기 저항 확산 영역 (7)을 상기 신호 입력단 (IN)과 상기 MOS 트랜지스터들 (4, 5)에 연결하기 위해 MOS 트랜지스터들 양측 하부의 절연막 (3)이 식각되어 오프닝 (6)이 형성된다. 상기 오프닝 (6)을 통해 고농도의 불순물 이온 예를 들어, As(Arsenic)가 60keV의 이온 에너지와 5.0×1015㎤의 도핑 농도로 반도체 기판(1)에 주입되어(참조 번호 7b') 후속 금속 콘택과의 저항이 줄어들게 된다.In order to connect the resistance diffusion region 7 to the signal input terminal IN and the MOS transistors 4 and 5, the insulating layer 3 on both sides of the MOS transistors is etched to form an opening 6. Through the opening 6, a high concentration of impurity ions, such as As (Arsenic), is implanted into the semiconductor substrate 1 at an ion energy of 60 keV and a doping concentration of 5.0 x 10 15 cm 3 (reference number 7b '). The resistance with the contact is reduced.
마지막으로, 상기 저항 확산 영역 (7), MOS 트랜지스터들 (4, 5) 및 전원들(VDD, VSS)과의 상호 연결을 위해 금속 콘택 (9, 10, 11, 12)이 형성된다. 즉, 저항 확산 영역 (7) 내의 고농도 확산 영역들 (7b')중 하나는 신호 입력단 (IN)에 연결되고 다른 하나는 상기 MOS 트랜지스터들 (4, 5)의 게이트들 (4a, 5a)에 공통으로 연결된다. 상기 PMOS 트랜지스터 (4)의 소오스는 VDD에 연결되고 드레인은 상기 NMOS 트랜지스터 (5)의 드레인과 함께 신호 출력단 (OUT)에 연결된다. 그리고 상기 NMOS 트랜지스터 (5)의 소오스는 VSS에 연결된다.Finally, metal contacts 9, 10, 11, 12 are formed for interconnection with the resistive diffusion region 7, the MOS transistors 4, 5 and the power supplies VDD, VSS. That is, one of the high concentration diffusion regions 7b 'in the resistance diffusion region 7 is connected to the signal input terminal IN and the other is common to the gates 4a and 5a of the MOS transistors 4 and 5. Is connected. The source of the PMOS transistor 4 is connected to VDD and the drain is connected to the signal output terminal OUT together with the drain of the NMOS transistor 5. The source of the NMOS transistor 5 is then connected to VSS.
도 3은 본 발명의 실시예에 따른 반도체 집적 회로의 평면도로서, PMOS 및 NMOS 트랜지스터들 (4, 5)의 게이트 전극들 (4a, 5a), 소오스 영역 및 드레인 영역들이 형성된 영역 하부에 저항 확산 영역 (7)이 형성되어 있음을 알 수 있다.3 is a plan view of a semiconductor integrated circuit according to an embodiment of the present invention, wherein a resistive diffusion region is formed below a region in which gate electrodes 4a and 5a, source and drain regions of PMOS and NMOS transistors 4 and 5 are formed. It can be seen that (7) is formed.
도 4는 본 발명의 실시예에 따른 도 3의 반도체 집적 회로의 등가 회로도로서, 저항 (R)은 도 3의 저항 확산 영역 (7a', 7b')으로 구성되고, PMOS 트랜지스터 (4)는 도 3의 게이트 전극 (4a)과 그 하부에 형성된 반도체 물질층 (3)으로 구성되고 그리고 NMOS 트랜지스터 (5)는 게이트 전극 (5a)과 그 하부에 형성된 반도체 물질층 (3)으로 구성된다.FIG. 4 is an equivalent circuit diagram of the semiconductor integrated circuit of FIG. 3 in accordance with an embodiment of the invention, wherein resistor R is comprised of resistive diffusion regions 7a ', 7b' of FIG. 3, and PMOS transistor 4 is shown in FIG. NMOS transistor 5 is composed of a gate electrode 4a and a semiconductor material layer 3 formed thereunder.
상기한 바와 같이, 본 발명에 따른 반도체 집적 회로는 하부에 형성되는 저항 확산 영역을 가짐으로써, 도 1의 반도체 집적 회로에 비해 반도체 집적 회로의 레이아웃 면적이 크게 감소된다.As described above, the semiconductor integrated circuit according to the present invention has a resistive diffusion region formed below, so that the layout area of the semiconductor integrated circuit is greatly reduced as compared with the semiconductor integrated circuit of FIG.
이상에서, 본 발명에 따른 회로의 구성을 상기한 설명 및 도면에 따라 도시하였지만 이는 예를 들어 설명한 것에 불과하며 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 다양한 변화 및 변경이 가능함은 물론이다.In the above, the configuration of the circuit according to the present invention is shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications are possible without departing from the technical spirit of the present invention.
이상과 같은 본 발명에 의하면, SOI 기판상에 형성된 집적 회로의 하부에 저항 영역을 형성함으로써, 반도체 집적 회로의 레이아웃 면적이 감소된다.According to the present invention as described above, by forming a resistance region under the integrated circuit formed on the SOI substrate, the layout area of the semiconductor integrated circuit is reduced.
Claims (6)
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|---|---|---|---|
| KR1019990033511A KR20010017814A (en) | 1999-08-14 | 1999-08-14 | A semiconductor integrated circuit having a silicon on insulator structure |
| JP2000245048A JP2001094061A (en) | 1999-08-14 | 2000-08-11 | Semiconductor intergrated-circuit device |
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| KR1019990033511A KR20010017814A (en) | 1999-08-14 | 1999-08-14 | A semiconductor integrated circuit having a silicon on insulator structure |
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| KR102282640B1 (en) * | 2014-11-24 | 2021-07-27 | 주식회사 키 파운드리 | Method for manufacturing of Semiconductor Device Having a Buried Magnetic Sensor |
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