KR102282640B1 - Method for manufacturing of Semiconductor Device Having a Buried Magnetic Sensor - Google Patents

Abstract

The present invention provides a method of manufacturing a semiconductor device having a magnetic sensor such that, in an SOI wafer using an SOI substrate, a sensing region is formed in a buried shape positioned on a hand wafer, and analog and digital circuit units are provided on the sensing region, and Accordingly, it is possible to manufacture a magnetic sensor with improved sensing capability and optimized than conventional ones.

Description

TECHNICAL FIELD [0001] Method for manufacturing of Semiconductor Device Having a Buried Magnetic Sensor

The present invention relates to a buried magnetic sensor, and more particularly, to a method of manufacturing a semiconductor device having a buried magnetic sensor in which a sensing region of the magnetic sensor (or Hall sensor) is disposed at the bottom of an analog and digital circuit.

As is known, a magnetic field sensing device is a device that detects the direction and magnitude of a magnetic field using the Hall effect, in which a voltage is generated in a direction perpendicular to the current and the magnetic field when a magnetic field is applied to a conductor through which a current flows. That is, in the magnetic field sensing element, in a state in which a magnetic field is applied, two opposite electrodes of the four electrodes provide current flow, and the remaining two opposite electrodes provide a hole generated in a direction perpendicular to the current flow. By providing a voltage, the Hall voltage is sensed to sense the direction and magnitude of the magnetic field.

And this magnetic field sensing element is applied to a magnetic sensor (or Hall sensor) such as a digital compass or eCompass that detects the earth's magnetic field and provides direction information.

Such a magnetic sensor provides a function to know the north and south, east and west orientations of the earth by applying the Hall effect of a magnetic field sensing element, and recently, it is installed and used in portable digital devices such as smartphones. . When used in portable digital devices, it is usefully used in map applications for the purpose of utilizing location information as well as the orientation of the earth using a mobile application (App).

However, in the magnetic sensor, analog and digital circuits are always used together in order to process the detection result of the magnetic field sensing device. The analog and digital circuits refer to various circuits for processing a signal sensed by a magnetic field sensing device.

As described above, the magnetic sensor is used together with analog and digital circuits for processing a signal output from the sensor, and the analog and digital circuits have been designed to be adjacent to the magnetic field sensing element in the horizontal direction. For example, a magnetic field sensing element is configured, and analog and digital circuits are positioned in a lateral direction of the magnetic field sensing element. This is because, on the semiconductor substrate, a sensing region for a magnetic sensor and an active region for forming analog and digital circuits are separately required.

As a result, there is a problem in that the size of the magnetic sensor itself cannot be reduced, which in turn causes a problem in that the overall size of an IC chip constituting the magnetic sensor cannot be reduced together.

This has recently made it difficult to develop products to make the size of various portable digital devices smaller. That is, unless the size of the magnetic sensor and various circuits is reduced by itself, there is a limit in reducing the size of the magnetic sensor chip included in the portable digital device due to the design and arrangement of the magnetic field sensing element and the analog/digital circuit as described above. In addition, if the size of the magnetic sensor is reduced, it is difficult to reduce it further because the sensitivity to the earth's magnetic field or magnetic force decreases.

Therefore, there is a need for a method of manufacturing a semiconductor device having a structure of a magnetic sensor having a high sensing capability while maximizing the area of the magnetic sensor by changing the positions of the magnetic field sensing device and various circuits.

US Patent No. 4,965,517 (October 23, 1990) US registered patent US 6,278,271 (2001. 08. 21) US registered patent US 6,545,462 (2003. 04. 08)

The present invention is to solve the above-described problem, and in order to secure the maximum area of the magnetic sensor, an SOI wafer is used and the sensing region is disposed in the lower region of the analog and digital circuits. To provide a method of manufacturing a semiconductor device having a.

According to a feature of the present invention for achieving the above object, the method comprising: preparing an SOI wafer having a handle wafer, an insulating layer, and an SOI layer in sequence; forming a sensing region of a first conductivity type on the handle wafer; and forming a circuit part on the SOI layer.

The method further includes forming a sensor contact connected to the sensing region through the SOI layer and the insulating layer.

It further includes; forming a semiconductor layer of the second conductivity type under the sensing region.

The forming of the sensor contact may include: forming an interlayer insulating film on the SOI layer; forming a trench exposing the sensing region; forming a heavily doped region of a first conductivity type in the exposed sensing region; and filling the trench with a conductive material.

forming a contact plug connected to the circuit unit; and forming a metal wire connecting the contact plug.

A semiconductor layer of a second conductivity type is further formed on the sensing region.

It further includes; forming a magnetic converging plate (IMC).

The circuit unit may include a low noise amplifier (LNA) for recognizing the voltage generated by the sensing region and outputting an output signal; an automatic gain controller (AGC) block amplifying the output signal; and an analog-to-digital converter (ADC) for converting the amplified output signal into a digital domain.

The sensing region is formed under the circuit unit.

According to another aspect of the present invention, the method comprising: forming a sensing region on a semiconductor substrate; forming an epitaxial layer on the sensing region; forming a plurality of sensor contacts connected to the sensing region on the epitaxial layer; forming a sensor circuit unit on the epitaxial layer; forming an interlayer insulating film on an upper surface of the epitaxial layer; forming a contact plug electrically connected to the circuit unit on the interlayer insulating layer; forming a metal wire connecting the contact plug and the sensor contact; and forming a magnetic converging plate on an upper surface or a rear surface of the P-type substrate.

The sensing region is formed under the circuit unit.

The forming of the sensing region on the semiconductor substrate includes forming a semiconductor layer above and below the sensing region.

The semiconductor layer above and below the sensing region is opposite to the conductivity of the sensing region.

According to the method of manufacturing a semiconductor device having a buried magnetic sensor according to the present invention configured as described above, the following effects are obtained.

First, in the present invention, a sensing region is formed in the handle wafer region under the insulating layer using an SOI wafer having a handle wafer, an insulating layer, and an SOI layer, and analog and digital circuits are positioned in the SOI layer above the sensing region. By doing so, it is possible to independently optimize the magnetic sensor area.

In addition, it is possible to implement a doping profile optimized for the sensing region without affecting the circuit portion, so that it is possible to manufacture a semiconductor device having a magnetic sensor with improved sensing capability compared to the related art.

In addition, since it does not overlap with the circuit part, there is an advantage of maximizing the sensing area.

In addition, a magnetic concentrator can be placed on the back side of the SOI wafer as well as on the magnetic sensor, which is advantageous in terms of design.

In addition, the present invention provides a narrow current path parallel to the surface of the semiconductor substrate by forming a P-type upper doping region and a P-type lower doping region in the N-type doped region of the semiconductor substrate. Therefore, it is possible to prevent current spread as much as possible, thereby improving the sensitivity of current detection. In addition, the current flowing between the electrodes can be improved regardless of various defects generated on the surface of the semiconductor substrate by the P-type upper doped region.

1 is a view showing a method of manufacturing a semiconductor device having a buried magnetic sensor according to a first embodiment of the present invention;
2 is a plan view of the embedded magnetic sensor manufactured in FIG. 1 ;
3 and 4 are views illustrating a method of manufacturing a semiconductor device having a magnetic sensor according to a second embodiment of the present invention;
5 is a view showing a method of manufacturing a semiconductor device having a magnetic sensor according to a third embodiment of the present invention;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention discloses a method of manufacturing a semiconductor device having a sensing region and a magnetic sensor, wherein the magnetic sensor has a silicon on insulator (SOI) substrate structure, and a parallel combination of an SOI and an integrated magnetic concentrator (IMC). structure, a parallel structure of an epitaxial layer (Epi) and a buried layer (NBL), a structure in which an epitaxial layer (Epi), a buried layer (NBL) and a deep trench isolation (DTI) structure are used together, an epi layer (Epi) ), a buried layer (NBL), and a magnetic converging plate (IMC), respectively, to construct a magnetic sensor based on the structure, while the analog/digital circuit is positioned above the sensing area and manufactured. In other words, it is possible to form a sensing element (sensing element) under the analog/digital circuit. The active area required by the analog/digital circuit and the active area occupied by the sensing element are separated above and below. Conventionally, it occupies as much active area as it is located on the same line. However, as in the present invention, when the circuit portion and the sensing area are formed by dividing the circuit portion and the sensing area with an insulating layer (box layer) therebetween using an SOI wafer, the area of the active area is reduced. There is an advantage of being reduced by half compared to the prior art.

In this embodiment, among the above structures, a manufacturing method using an SOI wafer and a manufacturing method of a semiconductor device having a buried magnetic sensor manufactured by growing an epitaxial layer on a non-SOI wafer will be described.

1 is a cross-sectional view illustrating a process for manufacturing a buried magnetic sensor based on an SOI wafer using a thick SOI layer, in particular, as a method of manufacturing a semiconductor device having a buried magnetic sensor according to a first embodiment of the present invention. A manufacturing method is demonstrated with reference to sectional drawing.

Referring to FIG. 1A , an SOI wafer 100 on which a buried magnetic sensor is to be configured is provided. The SOI wafer 100 includes a P-type silicon single crystal substrate (hereinafter referred to as a 'handle wafer') 101 used as a handle wafer, and a buried insulating layer ( Buried oxide) 102 and an SOI layer 104 formed of another silicon single crystal on the buried insulating layer 102 . Here, the SOI layer may include a layer in which an additional silicon epitaxial layer is formed on the SOI layer. In addition, the buried insulating layer or box layer 102 has a thickness of 0.1 μm to 1 μm, and the SOI layer 104 has a thickness of 0.1 μm to 0.5 μm.

As shown in FIG. 1B , a mask pattern 10 is formed on the SOI layer 104 . The mask pattern 10 is for forming a sensing region in the SOI layer 104 . Accordingly, the mask pattern 10 is provided in the remaining area except for the area where the magnetic sensing element is to be formed.

In FIG. 1C, an ion implantation process is performed. In the ion implantation, impurities having an N-type conductivity are first implanted in the upper direction of the SOI layer 104 . High ion implantation energy must be implanted to penetrate the SOI layer 104 and the buried insulating layer 102 to reach the handle wafer 101 . Then, an N-type doped region, that is, an N-type sensing region 106, is formed on the surface of the handle wafer 101 as a region into which N-type ions are implanted for a current path. The N-type sensing region 106 may be formed by a predetermined depth from the surface of the handle wafer 101 . Then, an impurity having a P-type conductivity type is ion-implanted into the lower portion of the N-type sensing region 106 to form a P-type doped region (referred to as a 'P-type lower doped region') deeper than the N-type sensing region 106 ( 108) may be formed. The length of the P-type lower doped region 108 is approximately the same as the length of the N-type sensing region 106 . Here, the regions of the N-type sensing region 106 and the P-type lower doped region 108 are not determined. This is because it is before the heat treatment and diffusion processes are performed.

The P-type lower doped region 108 cooperates with the P-type upper doped region described below to form a current path so that the current flows parallel to the surface of the handle wafer 101, and in particular, so that the current path is formed narrower. to make the current flow better. In other words, when only the N-type sensing region 106 is formed on the handle wafer 101 , a current flow may also occur in the downward direction of the handle wafer 101 in the N-type sensing region 106 . In this case, the amount of current may be reduced by diffusion through the entire area, thereby reducing the sensitivity of measuring the magnetic field strength. On the other hand, when both the P-type upper doped region and the P-type lower doped region 108 are formed in the N-type sensing region 106 , current flows between the regions, and the current loss to the handle wafer 101 is reduced by that amount, thereby reducing the current detection capability. can increase In that case, the performance improvement of the magnetic sensor can be expected.

The above-described P-type doped region (referred to as a 'P-type upper doped region') (not shown) may be additionally formed on the N-type sensing region 106 . The ion implantation energy of the P-type upper doped region is weaker than that of the P-type lower doped region 108 . The P-type upper doped region is formed to a predetermined depth on the surface of the handle wafer 101 , and is doped to be shallower than the N-type sensing region 106 . The P-type upper doping region offsets various defects that may occur in the non-uniformity of the surface of the handle wafer 101 or in the manufacturing process. Thus, the current path is induced to flow further inward from the surface of the handle wafer 101 . That is, the sensing region between the two P-type doped regions is formed apart from the oxide film and the silicon interface or the handle wafer surface, so that problems arising from the interface are eliminated, and the sensing capability is improved.

The mask pattern 10 is removed, and a heat treatment process is performed on the SOI layer 104 under a series of conditions. Then, the N-type sensing region 106 and the P-type lower doped region 108 located in the SOI wafer 100 are diffused, resulting in a state as shown in FIG. 1D . That is, the sensing region 110 is formed in the handle wafer 101 of the SOI wafer 100 while the N-type sensing region 106 and the P-type lower doped region 108 become the reference numerals 110 and 112 .

Next, as shown in FIG. 1E , an SI epitaxial layer 130 is formed on the SOI layer 104 . Therefore, it can be said that the first embodiment uses a thick SOI layer.

Subsequently, a trench isolation 132 passing through the silicon epitaxial layer 130 and the SOI layer 104 is formed as shown in FIG. 1F . The trench isolation 132 is formed by filling an insulating material in the trench formed by etching the silicon epitaxial layer 130 and the SOI 104 layer. Such trench isolation 132 is to prevent the circuit unit 140 existing around it and the sensor contacts 161 and 162 (see FIG. 1K ) to be described later from being physically attached to each other.

Referring to FIG. 1G , after the trench isolation 132 is formed, a process of forming the analog-digital circuit unit (hereinafter, referred to as a 'circuit unit') 140 is performed. The circuit unit 140 is located above the sensing region 110 . The circuit unit 140 processes the value sensed by the sensing region 110 , and substantially the sensing region 110 and the circuit unit 140 are combined to form a magnetic sensor. The circuit unit 140 is formed on the SOI layer 104 or the silicon epitaxial layer 130 with a buried insulating layer (Buried Oxide) 102 interposed therebetween. The circuit unit 140 includes a low-noise amplifier (LNA) that recognizes the voltage generated by the sensor and emits an output signal, an automatic gain controller (AGC) block that amplifies the output signal, and analog digital that converts the amplified output signal into a digital domain. Components such as a converter (ADC) and a controller may be included.

Referring to FIG. 1H , after the circuit unit 140 is formed, a first inter layer dielectric (ILD) 150 is deposited on the upper surface of the silicon epitaxial layer 130 .

Subsequently, a process of electrically connecting the sensing region 110 and the circuit unit 140 is performed. This is shown in FIG. 1I. In this view, the mask pattern 20 is formed on the first interlayer insulating layer 150 . The mask pattern 20 is provided in an area excluding the contact area. In this state, a plurality of trenches 151 , 152 , and 153 penetrating the first interlayer insulating layer 150 , the silicon epitaxial layer 130 , the SOI layer 104 , and the buried insulating layer 102 are formed. Two of the trenches 151 and 152 serve as trenches for the sensor contacts 161 and 162 connected to the N-type sensing region 110 . The N-type sensing region 110 is exposed by the trench formation. In addition, a heavily doped N-type region 113 is formed on the bottom surface of the trenches 151 , 152 and 153 for ohmic contact between the N-type sensing region 110 and the sensor contacts 161 , 162 , and 165 . The heavily doped N-type region 113 may be formed by ion-implanting an N-type dopant into the exposed N-type sensing region 110 .

Thereafter, the mask pattern 20 is removed and a heat treatment process is performed to diffuse the n-type dopant. Then, as shown in FIG. 1J, the trenches 151, 152, and 153 are further etched to form trenches 154, 155, and 156 that are deeper than the trench depth in FIG. 1I. Deeper trenches 154 , 155 , and 156 are formed while passing through the N+ doped region 113 . Then, a high concentration P-type doped region 114 is formed by ion-implanting a P-type dopant into end ends of the first trenches 154 to the third trenches 156 . The heavily doped P-type region 114 formed in FIG. 1J is to induce a current path to be formed in the lateral direction.

Subsequently, as shown in FIG. 1K , a conductive material, which is a conductive material, is filled in the first trench 154 to the third sensor contact 156 to the first sensor contact 161 , the second sensor contact 162 , and the third sensor contact 165 . ) to form As the filling material, tungsten (W), titanium (Ti) metal, titanium nitride film (TiN), or highly doped polysilicon is used.

The first sensor contact 161 and the second sensor contact 162 serve to connect the sensing region 110 and the circuit unit 140, and the third sensor contact 165 is formed to contact the P-type handle wafer. , used for grounding the P-type handle wafer. Therefore, the third sensor contact 165 becomes a ground contact. The sensor contact is formed through the buried insulating layer 102 , is connected to a metal wire disposed in a second interlayer insulating film to be described later, and reaches the sensing region 110 . Here, the above-described components, that is, the second interlayer insulating film, the metal wiring, and the heavily doped N-type region will be described below.

In FIG. 11 , a contact plug 166 for electrically connecting to the circuit unit 140 is formed via a metal wire. The contact plug 166 is also metallized by filling a metal material such as tungsten (W) or copper (Cu) therein.

Next, referring to FIG. 1M , a second interlayer insulating layer 170 is formed on the first interlayer insulating layer 150 . In the process of forming the second interlayer insulating film 170 , the process of forming the metal wiring 172 in the second interlayer insulating film 170 is also performed. The metal wiring 172 functions to electrically connect the circuit unit 140 and the contact plug 166 . Here, although the second interlayer insulating layer 170 is illustrated as only one layer, the present invention is not limited thereto, and a plurality of interlayer insulating layers may be sequentially deposited as an insulating layer. In addition, a plurality of metal wirings may be formed for each interlayer insulating layer.

Then, as shown in FIG. 1N , the second interlayer insulating layer 170 is etched to form a via VIA and a bonding pad 182 connected to the via is formed. A passivation layer 180 is formed on the bonding pad 182 .

In addition, a magnetic converging plate (IMC) 300 is further formed on the upper surface of the passivation layer 180 as shown in FIG. 1O . Alternatively, an integrated magnetic concentrator (IMC) 400 may be disposed on the rear surface of the P-type substrate. When it is located on the rear surface, it is very close to the sensing area 110 , so that it is possible to obtain an output signal with high sensitivity that has a smaller noise and a larger signal size. Here, the magnetic converging plate 400 bends the horizontal magnetic field to induce a vertical component entering the sensing region vertically. Therefore, the vertical component of the horizontal magnetic field can be detected in the sensing region. In addition, it provides the effect of amplifying the magnetic field of the region where the magnetic sensor (or Hall sensor) exists. The magnetic confinement plate 400 has a magnetic confinement plate having various shapes, such as a flat shape (planar-type), a non-planar shape, a curved shape, a conformal shape, and the like. do. Here, the conformal shape is formed in a shape that follows the shape of the insulating layer or passivation film under the magnetic converging plate.

In this way, while forming the magnetic field sensing elements 120 in the handle wafer 101, it is possible to provide the circuit unit 140 spaced apart thereon. Therefore, it is possible to independently implement a magnetic sensor having an optimal area. Therefore, the optimized sensor area can be independently implemented. In addition, the sensing region 110 and the circuit unit 140 are different active regions, that is, the sensing region 110 is formed in the active region within the handle wafer 101 , and the circuit unit 140 is formed by the SOI layer 104 or silicon. It is formed in the active area of ) of the epitaxial layer 130 . Therefore, each of the sensing region 110 and the circuit unit 140 has the advantage of independently optimizing doping profiles.

Meanwhile, FIG. 2 shows a plan view of the embedded magnetic sensor manufactured by the process of FIG. 1 described above.

In this view, four sensor contacts 160 , 161 , 162 , and 163 are formed, and an isolation region 132 surrounding the sensor contacts 160 , 161 , 162 and 163 exists. The four sensor contacts 160 , 161 , 162 , and 163 are electrically connected to the circuit unit 140 and also connected to the metal wiring 172 as described with reference to FIG. 1M . Two of the four sensor contacts sense the voltage change due to the Hall effect, and the other two are used to apply a current. In addition, four sensor contacts 160 , 161 , 162 , and 163 are disposed at corners of the N-type doped region 106 , and are in electrical contact with the N-type sensing region 110 of the sensing region 190 . . The remaining ground contacts 165 are used to apply a ground or other bias voltage of the P-type handle wafer.

Herein, the circuit unit 140 includes, in addition to the sensor circuit unit mentioned above, an active element, a passive element, etc., for example, a logic circuit, an analog circuit, a power, a hybrid circuit, an input/output circuit, a memory circuit, a DPS, a processor, etc. It may be formed on the sensing region.

3 is a view showing a part of a cross-sectional view of a process for explaining a process of manufacturing a magnetic sensor according to a second embodiment of the present invention, and FIG. 4 is a cross-sectional view of the embedded magnetic sensor manufactured by FIG. 3 .

The magnetic sensor of the second embodiment is manufactured using a thin SOI layer instead of the thick SOI layer described in the first embodiment.

Briefly describing the manufacturing process of the second embodiment, an N-type sensing region 210 and a P-type lower doped region 212 are formed in the SOI wafer 200 , and sensing is performed in the handle wafer 201 of the SOI wafer 200 . The formation of the region 210 is the same up to the process of FIG. 1D described in the first embodiment described above. However, as shown in FIG. 3 , a silicon epitaxial layer is not formed on the SOI layer 203 .

The trench isolation 220 is formed by filling an insulating material in the trench formed by etching the SOI layer 203 . In addition to the isolation 220 according to the trench process, it is also possible to form a LOCOS. Subsequent processes are performed in the same manner as in the subsequent process of FIG. 1G of the first embodiment. As such, the second embodiment is different from the first embodiment in that the silicon epitaxial layer is not formed on the SOI layer 203 constituting the SOI wafer 200, and thus only the SOI layer 203 is formed. It will be less thick. In a subsequent process, the circuit unit 230 spaced apart from the sensing element region 214 is formed on the SOI layer 203 . A cross-sectional view of the embedded magnetic sensor completed according to the manufacturing process of the second embodiment is shown in FIG. 4 .

After the isolation 220 is formed on the SOI layer 203 , the first sensor contact 240 and the second sensor contact 241 are formed. Therefore, as shown in FIG. 4 , the isolation 220 is formed in a shape in contact with the outer surfaces of the first sensor contact 240 and the second sensor contact 241 differently from the first embodiment.

As such, the second embodiment forms the isolation region 220 using a LOCOS process or a thin trench insulation (STI) process on the SOI MCD 203, so that the number of processes can be further reduced compared to the first embodiment. There will be.

5 is a cross-sectional view of a magnetic sensor according to a third embodiment of the present invention. The third embodiment is a structure using a non-SOI wafer that does not use an SOI wafer.

A P-type substrate 300 is provided as shown in FIG. 5A . Then, a screen oxide film is formed on the P-type substrate, and a mask pattern 30 is formed thereon. The mask pattern 30 is provided to form a sensing region in the P-type substrate. Therefore, the mask pattern 30 is provided in the remaining area except for the area where the magnetic sensing element is to be formed. An ion implantation process is performed. In the ion implantation process, impurities having an N-type conductivity are implanted into the N-conduction layer 310 and the lower portion of the N-type sensing region 310 , that is, a region deeper than the N-type sensing region 310 . This is a process of forming a P-type doped region (referred to as a 'P-type lower doped region') 312 by ion-implanting an impurity having a P-type conductivity into the . Here, a P-type doped region (referred to as a 'P-type upper doped region') may be formed on the N-type sensing region 310 .

Next, the mask pattern 30 is removed, and a P-type epitaxial layer 320 is formed as shown in FIG. 5B . The P-type epitaxial layer 320 is grown and formed to have a thickness approximately similar to the thickness of the P-type substrate 300 . In doing so, the sensing region 310 is formed between the P-type substrate 300 and the P-type epitaxial layer 320 .

Next, as shown in FIG. 5C , the sensor contacts 330 spaced apart from each other by a predetermined distance are formed in the P-type epitaxial layer 320 for contact with the sensing region. Here, the sensor contact 330 may be referred to as an N-type sinker. Therefore, the sensor contact 330 is formed as a high-concentration N-type region by an ion implantation method. Alternatively, it may be formed using high concentration N-type doped polysilicon. In this case, it may be formed by forming a trench and filling the trench with N-type doped polysilicon. Before filling the heavily doped N-type polysilicon, an LPCVD method of silicon oxide film may be first deposited. This is because, when the trench width is wide and only polysilicon is filled, a seam phenomenon may occur in the middle part. Alternatively, it may be formed by filling a metal layer such as tungsten.

Then, the circuit portion 340 is formed in the P-type epitaxial layer 320 between the sensor contacts 330 .

The circuit unit 140 includes a low-noise amplifier (LNA) that recognizes the voltage generated by the sensor and emits an output signal, an automatic gain controller (AGC) block that amplifies the output signal, and analog digital that converts the amplified output signal into a digital domain. Components such as a converter (ADC) and a controller may be included. When the circuit unit 340 is formed, a first inter layer dielectric (ILD) 350 is formed on the P-type epitaxial layer 330 as shown in FIG. 5D .

Then, as shown in FIG. 5E , a contact plug 360 is formed on the first interlayer insulating layer 350 . The contact plug 360 is for connecting the sensing region 310 and the circuit unit 340 , and the contact plug 360 is formed using a patterned mask pattern. Here, the contact plug 360 is formed to be electrically connected to the circuit unit 340 .

After the contact plug 360 is formed on the first interlayer insulating layer 350, the second interlayer insulating layer 370 and the passivation layer 380 described in the first embodiment are formed as shown in FIG. 5F. A process of forming the metal wiring 365 , the bonding pad 375 , and the like is performed. In addition, a magnetic converging plate (IMC) 900 formed on the upper surface of the passivation layer 380 is further formed as shown in FIG. 5G . Alternatively, a magnetic converging plate (IMC) 900 may be disposed on the rear surface of the P-type substrate. When positioned on the rear surface, it is very close to the sensing region 310 , so that a signal with high sensitivity having a smaller noise and a larger signal size can be obtained. Here, the magnetic converging plate 900 bends the horizontal magnetic field to induce a vertical component entering the sensing region vertically. Therefore, the vertical component of the horizontal magnetic field can be detected in the sensing region. In addition, it provides the effect of amplifying the magnetic field of the region where the magnetic sensor (or Hall sensor) exists.

As described above, in the third embodiment, a sensing region is formed between the P-type substrate 300 and the P-type epitaxial layer 320 .

As described above, the present invention forms a magnetic field sensing region inside a semiconductor substrate and improves the structure to position analog-digital circuits above the sensing region to secure a sensing area as much as possible while using a magnetic field capable of detecting a magnetic field. It can be seen that the basic technical gist is to provide a method for manufacturing a sensor.

Therefore, the sensor area is optimized, so that the size of the semiconductor chip or semiconductor die is not increased. In addition, the doping profile of the semiconductor layer used in the magnetic sensor can be adjusted independently. Because it is formed separately from the circuit part, it is possible. It can also more sensitively detect the Earth's magnetic field flowing above or below the substrate.

Although described with reference to the illustrated embodiments of the present invention as described above, these are merely exemplary, and those of ordinary skill in the art to which the present invention pertains can use various functions without departing from the spirit and scope of the present invention. It will be apparent that modifications, variations, and other equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: SOI wafer 101: handle wafer or P-type substrate
102: buried insulating layer or box layer (BOX layer)
104: SOI layer 110: N-type conductive layer
112: P-type lower doped region 113: High concentration N-type doped region
114: high concentration P-type doped region 130: silicon epitaxial layer
132; Isolation 140: circuit part
150: first interlayer insulating film
151, 152, 153, 154, 155, 156: trench for sensor contact
160, 161, 162, 163, 165: sensor contact
166: contact plug 170: second interlayer insulating film
180: passivation layer (passivation layer)
400, 900: Magnetic check-in plate (IMC)

Claims (14)

preparing an SOI wafer in which a semiconductor substrate, a buried insulating layer, and a silicon on insulator (SOI) layer are sequentially stacked;
forming a sensing region of a first conductivity type in the semiconductor substrate under the buried insulating layer;
forming a circuit part in the SOI layer on the buried insulating layer; and
and forming a sensor contact penetrating the buried insulating layer and connecting the sensing region and the circuit unit. delete The method of claim 1,
The method of manufacturing a semiconductor device having a magnetic sensor further comprising; forming a semiconductor layer of the second conductivity type under the sensing region. The method of claim 1,
The step of forming the sensor contact,
forming an interlayer insulating film on the SOI layer;
forming a trench exposing the sensing region;
forming a heavily doped region of a first conductivity type in the exposed sensing region; and
and filling the trench with a conductive material. The method of claim 1,
forming a contact plug connected to the circuit unit; and
The method of manufacturing a semiconductor device having a magnetic sensor further comprising; forming a metal wiring connecting the contact plug. 4. The method of claim 3,
A method of manufacturing a semiconductor device having a magnetic sensor, further forming a semiconductor layer of a second conductivity type on the sensing region. The method of claim 1,
A method of manufacturing a semiconductor device having a magnetic sensor further comprising; forming a magnetic converging plate (IMC). The method of claim 1,
The circuit unit may include a low noise amplifier (LNA) for recognizing the voltage generated by the sensing region and outputting an output signal;
an automatic gain controller (AGC) block amplifying the output signal; and
and an analog-to-digital converter (ADC) for converting the amplified output signal into a digital domain. The method of claim 1,
The sensing region is a method of manufacturing a semiconductor device having a magnetic sensor formed under the circuit portion. forming a sensing region on a semiconductor substrate;
forming a sensor circuit on the sensing region; and
Forming a sensor contact connecting the sensor circuit unit and the sensing region,
The sensing area is
N-type doped region; and
a P-type doped region formed deeper than the N-type doped region;
The P-type doped region is formed in the semiconductor substrate with a doping concentration higher than that of the semiconductor substrate. 11. The method of claim 10,
The sensing region is a method of manufacturing a semiconductor device having a magnetic sensor formed under the circuit portion. 11. The method of claim 10,
The step of forming a sensing region on the semiconductor substrate,
and forming a semiconductor layer on the sensing region. 13. The method of claim 12,
A method of manufacturing a semiconductor device having a magnetic sensor in which the semiconductor layer on the sensing region is opposite to the conductivity of the sensing region. 11. The method of claim 10,
forming an interlayer insulating film on an upper surface of the sensor circuit unit;
forming a contact plug electrically connected to the sensor circuit unit on the interlayer insulating layer;
forming a metal wire connecting the contact plug and the sensor contact; and
The method of manufacturing a semiconductor device having a magnetic sensor further comprising; forming a magnetic converging plate on the upper surface or the rear surface of the semiconductor substrate.

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