JP4542736B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device that uses a bulk semiconductor to achieve miniaturization and high performance of a transistor. In place Related.
[0002]
[Prior art]
Currently, as a transistor suitable for miniaturization and high performance, a MISFET in which a channel region is fully depleted (Fully Depleted) using an SOI (Silicon On Insulator) substrate is being researched and developed in various places. Hereinafter, this MISFET is referred to as FD-SOIFET. This element is basically configured with a low impurity concentration and thickness necessary for complete depletion of the silicon layer on the oxide film to be the channel region.
[0003]
In the FD-SOIFET, the vertical electric field from the gate electrode is partially supported by the buried oxide film at the bottom of the channel region, and the vertical electric field applied to the channel region is reduced accordingly. As a result of the relaxation of the vertical electric field in the channel region, there is an advantage that the carrier mobility of the channel region is increased and a high current driving capability can be obtained.
[0004]
However, FD-SOIFET has many disadvantages when further miniaturization is considered.
For example, in order to suppress the short channel effect, it is necessary to use a very thin silicon layer SOI substrate. When a thin silicon layer is used, the parasitic resistance increases, and the upper and lower channel regions are higher than silicon. In other words, since the oxide film is surrounded by an oxide film having a low thermal conductivity, the conduction of heat generated in the self-heating region in the vicinity of the drain is poor and the performance is greatly deteriorated. In addition, there is a problem that the quality of the SOI substrate and the reliability of the gate insulating film are difficult and the plasma damage is large. One of the disadvantages is that SOI substrates are currently expensive.
[0005]
On the other hand, attempts have been made to solve the above-mentioned disadvantages of FD-SOIFETs while exhibiting the same effects as FD-SOIFETs using bulk semiconductors. Specifically, when the channel region is a p-type layer, n of a low impurity concentration that is depleted by a built-in potential below the channel region. ^- P / n with mold layer ^- / P structure has been proposed to realize a pseudo SOIFET ((1) T. Mizuno et al,: 1991 Symp. On VLSI Tech. P.109 (1991), (2) M.Miyamoto et al ,: IEDM Tech. Dig. p.411 (1998), (3) Ishii, Miyamoto: JP-A-7-335837).
[0006]
[Problems to be solved by the invention]
However, the conventionally proposed pseudo SOIFET still has many problems to be solved, and it is difficult to obtain sufficient performance in the submicron range. That is, in the pseudo SOIFETs shown in documents (1) to (3), the depth (thickness) of the channel region is deeper than the depth of the source and drain diffusion layers. This is a great hindrance in suppressing the short channel effect when further miniaturized. Further, if the semiconductor layer in the channel region is a low impurity concentration layer necessary for realizing a fully depleted element, punch-through becomes a problem when the gate length (channel length) becomes as short as submicron. In order to prevent punch-through, a complicated drain structure as shown in documents (2) and (3) is required.
[0007]
Further, in the structures shown in documents (2) and (3), the bottom of the source and drain diffusion layers formed by counter doping is n ^- It reaches the p-type layer below the mold layer. For this reason, the junction capacitance of the source and drain is large, and high-speed operation becomes difficult.
Further, in documents (2) and (3), p / n of the channel region ^- Only the ion implantation method is considered as a method for obtaining the / p structure. However, p / n is actually only by the ion implantation method. ^- In order to obtain the / p structure, there is a limit to reducing the impurity concentration in the channel region and reducing the film thickness.
[0008]
The present invention has been made in consideration of the above-described circumstances, and is a semiconductor device having a transistor that can be miniaturized and improved in performance with a simpler structure. Place It is intended to provide.
[0009]
[Means for Solving the Problems]
A semiconductor device according to the present invention is formed so as to oppose a semiconductor substrate, a gate electrode formed on a surface of the semiconductor substrate via a gate insulating film, and a channel region directly below the gate electrode across the semiconductor substrate. A source and drain diffusion layer composed of a low-resistance region and an extension region having a lower impurity concentration and shallower than the low-resistance region formed so as to extend from the low-resistance region to the channel region side; A first impurity doped layer of the first conductivity type formed in the channel region between the drain diffusion layers, and a second impurity doped layer of the second conductivity type formed below the first impurity doped layer And a first conductivity type third impurity doped layer formed under the second impurity doped layer, wherein the first impurity doped layer has a junction depth of the source and drain. It is set to be equal to or shallower than that of the extension region of the diffusion layer, and the second impurity doped layer has an impurity concentration so as to be completely depleted by a built-in potential generated between the first and third impurity doped layers. The thickness is set.
[0011]
According to the present invention, an FET using a bulk semiconductor is formed by forming a three-layer structure of pnp (or npn) directly under a gate electrode so that an intermediate layer thereof is completely depleted by a built-in potential, thereby realizing a pseudo SOIFET. Can be obtained. In particular, by forming the first semiconductor layer serving as the channel region in the three-layer structure extremely thin, the short channel effect when miniaturized can be suppressed, and the punch-through resistance can be increased. .
Further, by forming the diffusion depth of the source / drain diffusion layer shallower than the junction surface of the second semiconductor layer and the third semiconductor layer, the junction capacitance and junction leakage of the source / drain can be suppressed to a small value.
[0012]
In the present invention, for example, the impurity concentration and thickness of the first semiconductor layer are set so as to be completely depleted when the channel inversion layer is formed. Thereby, a fully depleted FET is obtained. Alternatively, the impurity concentration and thickness of the first semiconductor layer can be set so as to be partially depleted when the channel inversion layer is formed, thereby obtaining a partially depleted FET.
[0013]
In the present invention, the three-layer structure directly under the gate electrode may be selectively formed only in the region directly under the gate electrode.
Moreover, in this invention, it can also be set as the structure where the 4th semiconductor layer of the 1st conductivity type was embedded immediately under the extended area | region of a source and drain diffused layer, and, thereby, higher punch through tolerance can be acquired.
Furthermore, in the present invention, it is preferable that the low resistance regions of the source and drain diffusion layers protrude above the gate insulating film position by selective epitaxial growth. As a result, a source / drain diffusion layer having a shallow diffusion depth can be formed.
[0014]
When the pseudo SOI FET according to the present invention is a fully depleted FET, the gate electrode is preferably formed of a metal electrode having a work function necessary for obtaining a desired threshold voltage. In the case of a partially depleted FET, a polycrystalline silicon gate can be used.
[0015]
The semiconductor device according to the present invention further opposes a semiconductor substrate, a gate electrode formed on a surface of the semiconductor substrate via a gate insulating film, and the semiconductor substrate with a channel region directly below the gate electrode interposed therebetween. Formed Low Resistance region and , A source and drain diffusion layer composed of an extension region having a lower impurity concentration and shallower than the low resistance region formed so as to extend from the low resistance region to the channel region side, and between the source and drain diffusion layers A first conductivity type first impurity doped layer formed in the channel region; a second conductivity type second impurity doped layer formed under the first impurity doped layer; and the second impurity A third impurity doped layer of the first conductivity type formed under the doped layer, wherein the first impurity doped layer has a junction depth deeper than that of the extension region of the source and drain diffusion layers The impurity concentration and thickness are set so as to be selectively formed in a state and partially depleted when the channel inversion layer is formed, and both ends of the second impurity doped layer are the source and drain diffusion layers. The impurity concentration and thickness are set so as to be selectively formed in contact with the extension region and to be completely depleted by a built-in potential generated between the first and third impurity doped layers. And
As such a structure, the first semiconductor layer is surrounded by a depletion layer formed between the source and drain extension regions and a second semiconductor layer that is completely depleted, and is in a floating state. Then, a partially depleted FET is obtained.
[0016]
The semiconductor device according to the present invention further includes a gate between the semiconductor substrate, the first source and drain diffusion layers formed on the semiconductor substrate and spaced apart from each other, and the first source and drain diffusion layers of the semiconductor substrate. A first transistor having a first gate electrode formed through an insulating film; a second source and drain diffusion layer formed on the semiconductor substrate and spaced apart from each other; and the second source of the semiconductor substrate And a second transistor having a second gate electrode formed through a gate insulating film between the drain diffusion layer, and the first transistor is disposed between the first source and drain diffusion layers. A first conductivity type first impurity doped layer formed in the channel region; a second conductivity type second impurity doped layer formed under the first impurity doped layer; And a serial third impurity doped layer of the first conductivity type formed below the second impurity doped layer, and The source and drain diffusion layers of the first transistor are formed on the semiconductor substrate so as to face each other with the channel region immediately below the gate electrode interposed therebetween, and from the low resistance region to the channel region side. An extension region having a lower impurity concentration and shallower than the low resistance region formed to extend, and The first impurity doped layer has a junction depth of the first source / drain diffusion layer. Extended area Impurity concentration and thickness are set to be completely depleted or partially depleted when the channel inversion layer is formed. Of the first transistor The second impurity-doped layer has a depth of junction with the third impurity-doped layer deeper than that of the first source / drain diffusion layer, and the first and third impurity-doped layers. The impurity concentration and the thickness are set so as to be completely depleted by a built-in potential generated between and.
[0017]
According to the present invention, an LSI using a pseudo SOIFET that can be miniaturized and suppress the short channel effect can be obtained as the first transistor. For example, if the second transistor is a bulk FET having a bulk layer of the first conductivity type that is an impurity doped layer deeper than the second source and drain diffusion layers in a portion immediately below the second gate electrode of the semiconductor substrate, An integrated structure of a pseudo SOIFET (fully depleted element or partially depleted element) and a bulk FET is obtained.
If the second transistor is a pseudo SOI FET having the same structure as that of the first transistor, a combination in which one of the first and second transistors is a fully depleted element and the other is a partially depleted element can be obtained.
[0018]
The method of manufacturing a semiconductor device according to the present invention includes a step of epitaxially growing a first semiconductor layer not doped with impurities on a semiconductor substrate having a first impurity doped layer of the first conductivity type on at least the surface, Forming a second conductivity type second impurity doped layer in contact with the first impurity doped layer by implanting ions into the first semiconductor layer; and performing ion implantation on the surface portion of the first semiconductor layer. Forming a first conductivity type third impurity doped layer in contact with the second impurity doped layer; forming a gate electrode on the third impurity doped layer through a gate insulating film; and A junction surface of the third impurity doped layer and the second impurity doped layer in a state of being self-aligned with the gate electrode on the semiconductor substrate Form an extended area that is equal to or deeper than And having a junction depth shallower than the junction surface of the second impurity doped layer and the first impurity doped layer. In other words, the extension region and the low resistance region are formed by forming a low resistance region having a higher impurity concentration than the extension region. Forming a source and drain diffusion layer. The second impurity doped layer is formed with an impurity concentration and thickness that are completely depleted by a built-in potential between the first and third impurity doped layers. It is characterized by that.
[0019]
The method of manufacturing a semiconductor device according to the present invention also includes a step of epitaxially growing a first semiconductor layer not doped with impurities on a semiconductor substrate having a first impurity doped layer of the first conductivity type on at least the surface, Forming a second conductivity type second impurity doped layer in contact with the first impurity doped layer by implanting ions into the first semiconductor layer; and impurities doped on the second impurity doped layer A step of epitaxially growing a second semiconductor layer not formed, a step of ion-implanting the second semiconductor layer to form a third impurity doped layer of a first conductivity type in contact with the second impurity doped layer, Forming a gate electrode on the third impurity doped layer via a gate insulating film, and in a state of being self-aligned with the gate electrode on the semiconductor substrate; Bonding surface of the impurity-doped layer and the second impurity doped layer Form an extended area that is equal to or deeper than And having a junction depth shallower than the junction surface of the second impurity doped layer and the first impurity doped layer. In other words, the extension region and the low resistance region are formed by forming a low resistance region having a higher impurity concentration than the extension region. Forming a source and drain diffusion layer. The second impurity doped layer is formed with an impurity concentration and thickness that are completely depleted by a built-in potential between the first and third impurity doped layers. It is characterized by that.
[0020]
According to the manufacturing method of the present invention, by using epitaxial growth and ion implantation, a shallow channel region semiconductor layer can be formed with a low impurity concentration of a pseudo SOIFET. In the manufacturing method of the present invention, the step of forming the source and drain diffusion layers is preferably a step of forming an extended region deeper than the third impurity diffusion layer by performing ion implantation using the gate electrode as a mask, and a side wall of the gate electrode. Forming a sidewall insulating film on the gate electrode, and performing ion implantation using the gate electrode and the sidewall insulating film as a mask, having a higher impurity concentration than the extension region, deeper than the extension region, and a second impurity diffusion layer And a step of forming a low resistance region shallower than the bonding surface of the first impurity diffusion layer.
[0021]
In the manufacturing method of the present invention, the step of forming the element isolation insulating film may be performed prior to the epitaxial growth step of the semiconductor layer, or may be performed after forming the three-layer structure of the channel region. In particular, if the latter is used, it is possible to prevent a short circuit between adjacent element regions when epitaxial growth is performed after element isolation.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, n-channel MISFETs are all shown, but it goes without saying that the present invention can be similarly applied to p-channel MISFETs in which the conductivity type of each part is reversed.
[0023]
[First Embodiment]
FIG. 1 shows a cross-sectional structure of a MISFET according to the first embodiment.
A p-type layer 2 is formed on the surface portion of the silicon substrate 1 by well ion implantation or the like, and a low impurity concentration n is formed thereon. ^- A mold layer 3 and a p-type layer 4 serving as a channel region are formed. These p / n ^- In the / p junction structure, at least the upper p-type layer 4 and the n below it ^- As will be described later, the mold layer 3 is formed by using an epitaxial growth process and an ion implantation process in combination.
[0024]
A gate electrode 6 is formed on the p-type layer 4 serving as a channel region via a gate insulating film 5. The gate electrode 6 is mainly composed of a metal electrode 6a having a predetermined work function, and a polycrystalline silicon electrode 6b is overlaid thereon.
[0025]
The source / drain diffusion layer 7 is formed by ion implantation using the sidewall insulating film 8 provided on the sidewall of the gate electrode 6 and the gate electrode 6 as a mask. ⁺ N-type ion implantation using the gate electrode 6 as a mask before forming the low-resistance region 7a of the mold and the sidewall insulating film 8 ⁺ The low-resistance region 7a is formed so as to extend from the low-resistance region 7a to the channel region, and the n-type expansion region 7b is shallower and has a lower impurity concentration than the low-resistance region 7a. The low resistance region 7 a is formed so as to protrude upward from the position of the gate insulating film 5. As will be described later, this structure is obtained by performing selective epitaxial growth after forming the gate electrode 6. By using this structure, the bottom junction surface of the low resistance region 7a does not reach the p-type layer 2, that is, n ^- It is located inside the mold layer 3.
[0026]
P / n under the gate electrode ^- N of / p junction structure ^- The impurity concentration and thickness of the mold layer 3 are set so that the mold layer 3 is completely depleted by the built-in potential between the upper and lower p-type layers 4 and 2. As a result, the transistor of this embodiment becomes a pseudo SOIFET similar to the SOI structure in which the buried oxide film is provided under the channel region. Hereinafter, this transistor is an FET using silicon on the depletion layer ( S ilicon O n De pletion L ayer FET In this sense, it is called “SODELFET”.
[0027]
The impurity concentration and thickness of the p-type layer 4 serving as the channel region are selected so that the p-type layer 4 is completely depleted when the channel inversion layer is formed. As a result, a fully depleted element, that is, an FD-SODELFET is obtained. In particular, the p-type layer 4 needs to be sufficiently thin in order to suppress the short channel effect, and the junction depth (n ^- The position of the junction surface with the mold layer 3) is the same as or shallower than that of the source and drain extension regions 7b.
The example of FIG. 1 shows a case where the junction depth of the p-type layer 4 is shallower than that of the source and drain extension regions 7b.
[0028]
FIG. 3 shows the relationship between the thickness of the p-type layer 4 in the channel region and the threshold voltage roll-off value δVth (the difference between the threshold voltage in the short channel and the threshold voltage in the long channel). The impurity concentration of 4 is shown as a parameter. As shown in FIG. 13, the threshold voltage roll-off value δVth is known to increase as the gate length Lg (that is, the channel length) decreases. The data in FIG. ^- The impurity concentration of the mold layer 3 is 1E16 / cm ^Three This is a calculation result when the gate oxide film thickness is 3 nm and the power source is Vdd = 1.2V. For comparison, FIG. 3 shows SOIFET data, and the data surrounded by a broken line shows the case of a normal bulkFET using uniformly doped p-type bulk silicon.
[0029]
FIG. 3 shows that as the thickness of the p-type layer 4 becomes smaller, the roll-off value δVth of the threshold voltage approaches zero and the short channel effect is suppressed. This is the same effect as that of SOIFET. By thinning the channel region, the two-dimensional effect of the potential distribution along the drain shape is weakened, and the threshold voltage is increased only by the one-dimensional potential distribution in the vertical direction. This is to be decided.
[0030]
FIG. 3 also shows that for the same δVth, the p-type layer 4 may be thicker in the SODELFET according to this embodiment than in the SOIFET. This means that a MISFET can be made without forcibly forming a thin film, and that variations in threshold voltage due to variations in the thickness of the p-type layer 4 can be reduced. It shows that it is advantageous for device manufacturing.
[0031]
However, the above effect depends on the impurity concentration of the p-type layer 4. As shown in FIG. 3, the impurity concentration of the p-type layer 4 is 1E17 / cm. ^Three If it is more than about, the effect of suppressing the short channel effect by thinning the film is almost lost, and the effect cannot be expected unless the film is considerably thinned. This is a result of the elongation of the depletion layer immediately below the channel being reduced by thinning the film. Therefore, it is necessary to optimize the impurity concentration and thickness of the p-type layer 4 serving as the channel region.
[0032]
In addition, by selecting the impurity concentration and thickness of the p-type layer 4 serving as the channel region and the work function of the gate electrode 6, the p-type layer 4 may be partially depleted when the channel inversion layer is formed. it can. This results in partial depletion ( P artly
D PD-SODELFET which is an element of the obtained) is obtained.
[0033]
N need to be fully depleted by built-in potential ^- The mold layer 3 also needs to be optimized in impurity concentration and thickness. n ^- This is because if a part of the mold layer 3 remains without being depleted, the source and the drain are short-circuited to increase the leakage current. On the other hand, this n ^- The thickness of the mold layer 3 determines the degree of relaxation of the vertical electric field in the channel region, and in order to keep the carrier mobility in the channel region large, n ^- It is preferable that the mold layer 3 has a certain thickness.
[0034]
FIG. 4 shows this n ^- The relationship between the thickness of the mold layer 3, δVth indicating the short channel effect, and carrier mobility (electron mobility μe) is shown. As shown, n ^- As the mold layer 3 becomes thicker, the electron mobility μe increases, but δVth also increases. That is, the suppression of the short channel effect and the improvement of carrier mobility are in a trade-off relationship.
[0035]
N which is a low resistance region of the source and drain ⁺ The junction depth of the mold layer 7a is n as described above. ^- It is set shallower than the junction surface between the mold layer 3 and the p-type layer 2. As a result, n ⁺ Compared to the case where the mold layer 7a is formed to a depth reaching the p-type layer 2, the junction capacitance and the junction leakage of the source and drain are suppressed to a small level, and a high punch-through breakdown voltage can be obtained even at a low threshold voltage. The effect can be expected. Further, since the junction capacitance of the source and drain is reduced, the transistor can be operated at high speed.
[0036]
P / n as above ^- In order to optimize the impurity concentration distribution and thickness of the / p structure, it is necessary to optimize the process conditions. According to the inventor's process simulation, p / n ^- It has been found that it is difficult to form a three-layer structure of / p only by an ion implantation process as in the prior art. That is, the p-type layer 2 of FIG. ^Three If an impurity concentration is to be formed, it must be performed with a large dose and high acceleration energy, and the tail of the impurity distribution in the depth direction is greatly expanded. Then, a low impurity concentration n is further implanted into the surface portion of the formed p-type layer 2 by ion implantation. ^- Even if the layer 3 and the p-type layer 4 are to be formed, it is far from the desired impurity profile.
[0037]
Therefore, in the manufacturing process of the present invention, the p-type layer 4 which becomes the channel region in FIG. ^- For the mold layer 3, an epitaxial growth layer is used. Specifically, p / n in FIG. ^- An example of a manufacturing process for obtaining the / p junction structure will be described below.
[0038]
5A to 5D show p / n including an element isolation step in consideration of application to a specific LSI. ^- 1 shows an example of a manufacturing process for obtaining a / p junction structure. First, as shown in FIG. 5A, a laminated mask of a buffer oxide film 21 and a silicon nitride film 22 is formed on the surface of the silicon substrate 1, a groove is formed in the element isolation region by RIE, and an element isolation insulating film is formed in this groove. 23 is embedded.
[0039]
Thereafter, the silicon nitride film 22 and the buffer oxide film 21 are removed, and boron (B) ion implantation is performed to form the p-type layer 2 as shown in FIG. 5B. Specifically, boron (B) is accelerated at a voltage of 20 keV and a dose of 5 × 10. ¹³ / Cm ² Ion implantation. An undoped silicon layer 10 is epitaxially grown on the p-type layer 2 to a thickness of, for example, 80 nm.
[0040]
Next, as shown in FIG. 5C, arsenic (As) ions are implanted into the silicon layer 10 to obtain n ^- The mold layer 3 is formed. As ion implantation conditions are, for example, an acceleration voltage of 20 keV and a dose of 5 × 10. ¹¹ / Cm ² And Subsequently, as shown in FIG. 5D, B ion implantation is performed, and n ^- A p-type layer 4 serving as a channel region is formed on the surface portion of the mold layer 3. The B ion implantation conditions are, for example, an acceleration voltage of 5 keV and a dose amount of 6 × 10. ¹¹ / Cm ² And
[0041]
6A to 6E show p / n ^- In this example, two-stage epitaxial growth is used to form a / p junction structure. FIG. 6A shows the same element isolation step as FIG. 5A. After element isolation, as shown in FIG. 6B, a p-type layer 2 is formed on the surface of the silicon substrate 1 by B ion implantation, and then an undoped silicon layer 10 is epitaxially grown thereon. Then, as shown in FIG. 6C, As ion implantation is performed on the silicon layer 10 to obtain n ^- The mold layer 3 is formed. Subsequently, as shown in FIG. 6D, epitaxial growth is performed again, and n ^- An undoped silicon layer 11 is formed on the mold layer 3. Subsequently, as shown in FIG. 6E, B ion implantation is performed on the silicon layer 11 to form a p-type layer 4 serving as a channel region.
[0042]
FIG. 2 shows the p / n formed by the above process. ^- The impurity profile of / p junction structure is shown. N with low impurity concentration and thickness required for complete depletion by combining epitaxial growth processes ^- The mold layer 3 and the p-type layer 4 can be formed.
[0043]
As described above, the element isolation step is performed using p / n. ^- What is performed before forming the / p structure is p / n due to heat in the element isolation step. ^- This is preferable in preventing re-diffusion of impurities having a / p structure. However, in this process, when the element isolation region is narrow, there is a possibility that the silicon layer of the adjacent element region is connected on the element isolation region in the epitaxial growth process of the silicon layer. In order to prevent such a situation reliably, p / n ^- A device isolation step may be performed after the / p structure is formed.
[0044]
In the case of having such an element isolation step, a specific SODELFET integration step will be described with reference to FIGS. P-type layer 2 and n on the silicon substrate 1 shown in FIG. ^- The mold layer 3 and the p-type layer 4 are formed by a combination of the epitaxial growth process and the ion implantation process described with reference to FIGS. 5A to 5D or FIGS. 6A to 6E before the element isolation process. P / n like this ^- As shown in FIG. 7, a mask formed of a buffer oxide film 21 and a silicon nitride film 22 is patterned in the transistor region on the substrate on which the / p structure is formed, and an element isolation trench is formed to a depth reaching the p-type layer 2 by RIE. And an element isolation insulating film 23 is embedded therein.
[0045]
Next, as shown in FIG. 8, a gate oxide film 5 is formed, and a gate electrode 6 is formed. The gate electrode 6 is a laminated electrode of a metal electrode 6a having a work function necessary for obtaining a predetermined threshold voltage and a polycrystalline silicon electrode 6b. This laminated electrode is patterned using the silicon nitride film 24 as a mask. Then, As ion implantation is performed using the gate electrode 6 as a mask to form an n-type layer to be a source / drain extension region 7b. The extension region 7 b has a junction depth deeper than that of the p-type layer 4. However, the junction depth of the extension region 7 b may be the same as that of the p-type layer 4.
[0046]
Next, as shown in FIG. 9, a sidewall insulating film made of the silicon nitride film 25 is formed on the sidewall of the gate electrode 6. Then, as shown in FIG. 10, the silicon surfaces of the source and drain regions are exposed, and a silicon layer 26 is formed thereon by selective epitaxial growth. This is because the p-type layer 2 and n are compared with the diffusion depth of the high-concentration source and drain regions to be formed next. ^- This is to keep the joint surface position of the mold layer 3 deep.
[0047]
Then, as shown in FIG. 11, As ion implantation is performed, and the source and drain n ⁺ A mold low resistance region 7a is formed. As described above, the diffusion depth of the low resistance region 7 a is set so as not to reach the p-type layer 2. Thus, the SODELFET is completed.
After that, as shown in FIG. 12, an interlayer insulating film 27 is deposited, contact holes necessary for this are formed, and contact plugs 28 such as W are embedded. Thereafter, although not shown, a metal wiring is formed on the interlayer insulating film 27.
[0048]
As described above, in the SODELFET according to this embodiment, the junction depth of the p-type layer 4 in the channel region is formed shallower than that of the source / drain extension region 7b, and the bottom surface of the source / drain low resistance region 7a. But n ^- N to be located in mold 3 ^- The thickness of the mold layer 3 is set relatively large. Thereby, the high carrier mobility of the channel region is ensured by the effect of the vertical electric field relaxation, and the short channel effect can be sufficiently suppressed even in the submicron region. And these effects are p / n ^- A / p junction structure can be obtained only by combining an epitaxial growth process. Further, the bottom surface of the low resistance region 7a of the source and drain is completely depleted by a built-in potential. ^- Since it is in the mold layer 3 and is not in contact with the p-type layer 2, the junction capacitance is small, high-speed operation is possible, and a high punch-through breakdown voltage is obtained.
[0049]
In the case of this embodiment, it is also important to use the metal electrode 6a for the gate electrode 6 in order to realize a fully depleted element and set the threshold voltage to an optimum condition. Specifically, TiN, WN or the like is used as the metal electrode 6a. As the metal electrode 6a having two work functions, (TiN, WN), (W, WN) or the like, which is a combination of two kinds of materials, is used. That is, a desired threshold voltage can be obtained by using the metal electrode 6a having an appropriate work function according to the required threshold voltage.
[0050]
On the other hand, when forming a partially depleted element, a desired threshold value can be obtained by using a polycrystalline silicon electrode as the gate electrode 6.
[0051]
In the above embodiment, in order to further improve the carrier mobility in the channel region, it is also effective to use a SiGe strain alloy layer or a Si / SiGe strain alloy layer as the p-type layer 4. As a result, a SODELFET having a higher current driving capability is obtained. The same applies to the following embodiments.
[0052]
[Second Embodiment]
In the first embodiment, p / n ^- Even if the impurity concentration and thickness of the / p junction structure are optimized, when the gate length Lg is 50 nm or less, the punch-through phenomenon between the source and the drain cannot be ignored.
[0053]
FIG. 14 shows the SODELFET structure of the second embodiment corresponding to FIG. 1 that enables reliable punch-through prevention in consideration of such circumstances. 1 is different from FIG. 1 in that a p-type layer 9 which is a halo region is buried immediately below the source / drain extension region 7b. Others are the same as in the first embodiment, and an FD-SODELFET can be obtained by setting the impurity concentration and thickness of the p-type layer 4. If the impurity concentration of the p-type layer 4 is set higher, a PD-SODELFET can be obtained.
[0054]
Conventionally, a method using oblique ion implantation has been proposed in order to increase the impurity concentration in the central portion of the channel region for the purpose of preventing punch-through. However, in the case of the present invention, increasing the impurity concentration in the central portion of the channel region is an obstacle to realizing high carrier mobility by relaxing the electric field in the direction perpendicular to the substrate. Therefore, in order to obtain the structure of FIG. 14, the p-type layer 9 is formed immediately below the extension region 7b by vertical ion implantation using the gate electrode 6 as a mask.
[0055]
In the method of forming the halo region by oblique ion implantation, in the case of an LSI in which the gate electrodes are arranged at a fine pitch, there are elements that cannot be ion-implanted due to the shadow of the adjacent gate electrode, and therefore the elements that do not improve the short channel effect. Will appear. On the other hand, if the p-type layer 9 which is a halo region is formed by ion implantation in the vertical direction as described above, the device structure shown in FIG. be able to. That is, it becomes possible to suppress the short channel effect and to guarantee the punch-through breakdown voltage when miniaturized.
[0056]
In the embodiments described so far, the description has been given focusing on only one element region. In the case of making an LSI in which SODELFETs having the same element structure are integrated, the above-mentioned p / n ^- The / p structure may be uniformly formed by epitaxial growth and ion implantation over the entire surface of the substrate. However, by using selective ion implantation, p / n for each channel region of each element. ^- A / p junction structure can also be made.
[0057]
[Third Embodiment]
FIG. 15 shows p / n by selective ion implantation. ^- The structure of the SODELFET according to the embodiment in which the / p junction structure is selectively formed in the region immediately below the gate electrode is shown in correspondence with FIG. Unlike FIG. 1, the As ion implantation is selectively performed only on the portion of the epitaxially grown undoped silicon layer 10 where the channel region is to be formed. ^- A mold layer 3 is formed. Therefore, the bottom surface of the extension region 7b of the source / drain diffusion layer 7 is n. ^- The bottom surface of the low resistance region 7a is located inside the undoped silicon layer 10 in contact with the mold layer 3.
[0058]
Similarly, the p-type layer 4 serving as the channel region can be formed by selective B ion implantation.
In this way, n ^- By forming the mold layer 3 only immediately below the channel region, the bottom surfaces of the low resistance regions 7a of the source and drain are located inside the undoped (i) silicon layer 10 and the junction capacitance of the source and drain can be further reduced. It becomes possible.
[0059]
The embodiments so far have mainly described the FD-SODELFET which is a fully depleted element. Therefore, the threshold voltage is determined by the work function of the gate electrode, and the degree of freedom of adjustment is small. However, in the case of LSI, it is generally desired to improve performance by optimizing circuit design by incorporating MISFETs having different threshold voltages. For this purpose, it may be inconvenient if only a fully depleted device is used.
[0060]
On the other hand, if the selective ion implantation method described in the third embodiment is used, a plurality of MISFETs with different threshold voltages are integrated by varying the impurity concentration and thickness of the channel region. Can do. Such an embodiment will be described next.
[0061]
[Fourth embodiment]
FIG. 16 shows a structure in which an FD-SODELFET and a bulkFET are integrated. The FD-SODELFET has the structure described in the third embodiment. Explaining this according to the manufacturing process, as described in the manufacturing process of the first embodiment, first, the undoped silicon layer 10 is epitaxially grown on the silicon substrate 1 on which the p-type layer 2 is formed. Thereafter, the element isolation insulating film 30 is embedded in the element isolation region by STI. However, the p-type layer 2 may be formed by selectively ion-implanting only in the SODELFET region without being formed on the entire surface of the substrate.
[0062]
Thereafter, in the region of the FD-SODELFET, n ions are implanted by the same selective ion implantation as described in the fourth embodiment before the gate electrode 6 is formed. ^- A mold layer 3 and a p-type layer 4 are sequentially formed. In the bulkFET region, a p-type layer 31 is formed to a depth reaching the p-type layer 2 by another selective ion implantation process for the undoped silicon layer 10 formed by epitaxial growth. Further, channel ion implantation is performed as necessary. Thereafter, the gate electrode 6 is formed in each element region, and the source / drain extension region 7b and the low-resistance region 7a are simultaneously formed.
As a result, FD-SODELFETs and bulkFETs having different threshold voltages can be integrated.
[0063]
[Fifth Embodiment]
FIG. 17 shows a structure in which a PD-SODELFET is integrated together with the FD-SODELFET, in which the channel region is not completely depleted even when the channel inversion layer is formed. The FD-SODELFET is formed by the same process as that of FIG. For PD-SODELFET, n-ion implantation conditions different from those of FD-SODELFET ^- A mold layer 3a and a p-type layer 4a are sequentially formed. However, PD-SODELFET n ^- Mold layer 3a and n on the FD-SODELFET side ^- The same conditions as the mold layer 3 may be used. At least the p-type layer 4a of the PD-SODELFET is formed thicker with a higher impurity concentration than the p-type layer 4 of the FD-SODELFET.
[0064]
In the case of FIG. 17, the p-type layer 4a is formed deeper than the diffusion depth of the source / drain extension region 7b and shallower than the low resistance region 7a. The p-type layer 4a and n ^- The mold layer 3a is selectively formed immediately below the channel region, and n ^- Both end portions of the mold layer 3a are in contact with the extended region 7b.
[0065]
PD / SODELFET p / n ^- The impurity concentration distribution of the / p structure portion is shown in FIG. 18, for example, in comparison with FIG. 2 of FD-SODEL. The boron concentration of the p-type layer 4a is increased by an order of magnitude compared to the case of FIG. Thereby, a PD-SODELFET having a threshold voltage higher than that of the FD-SODELFET and in which the p-type layer 4a is partially depleted when the channel inversion layer is formed is obtained. At this time, the p-type layer 4a has a depletion layer between the expansion region 7b and n which is completely depleted. ^- A floating p-type layer is surrounded by the mold layer 3a.
[0066]
FIG. 19 shows the results obtained by calculating the drain voltage Vd-drain current Id characteristics of the PD-SODELFET described above using the gate voltage Vg as a parameter. The gate length is Lg = 70 nm, the power supply voltage is Vdd = 1 V, and the off current is Ioff = 22.5 nA / μm. As is apparent from the figure, a kink characteristic is obtained in which the drain current Id rises rapidly from the middle of the drain voltage Vd. This kink characteristic is a characteristic peculiar to a PD-SODELFET obtained by apparently lowering the threshold voltage as a result of partial depletion of the p-type layer 4a. Specifically, this kink characteristic is obtained when the threshold voltage is apparently lowered when holes generated by impact ionization are accumulated in the p-type layer 4a when a certain drain voltage is exceeded.
[0067]
FIG. 20 shows the potential Vb of the body region (p-type layer 4a) when the gate voltage is fixed to Vg = 1V and the drain voltage Vd is changed with time as shown by the broken line in the PD-SODELFET. This change is shown by using the thickness of the epitaxially grown silicon layer 10 as a parameter. The body potential Vb changes following the drain voltage Vd, which indicates that the p-type layer 4a is substantially floating.
[0068]
[Sixth Embodiment]
FIG. 21 shows a structure in which PD-SODELFET and bulkFET are integrated. The channel body structures of the PD-SODELFET and the bulkFET are the same as in the embodiment of FIG. 16, but the PD-SODELFET is formed by optimally setting the impurity concentration of the p-type layer 4. In the case of a PD-SODELFET, a polycrystalline silicon electrode can be used as the gate electrode 6. In FIG. 21, both PD-SODELFET and bulkFET are polycrystalline silicon gates. In general, when a bulk FET uses a metal electrode, the threshold becomes too high. According to this embodiment, it is possible to obtain a high current driving capability by setting the bulkFET as a low threshold value.
[0069]
Note that the FD-SODELFET and PD-SODELFET in FIGS. 16, 17, and 21 have a structure in which the p-type layer 9 is embedded as a halo region immediately below the source / drain extension region 7b, as in the embodiment of FIG. It may be used.
[0070]
Next, a preferred circuit example in which the FD-SODELFET or PD-SODELFET according to the present invention is combined with a bulkFET will be described.
[0071]
[Seventh embodiment]
FIG. 22 shows a NAND gate including n-channel transistors QN1 to QN3 connected in series and p-channel transistors QP1 to QP3 connected in parallel. Each of n-channel transistors QN1 to QN3 has a gate connected to the input terminal, and is connected in series between the output terminal and the reference potential terminal. The p-channel transistors QP1 to QP3 are connected in parallel between the power supply terminal and the output terminal, and each gate is connected to the corresponding input terminal. In such a circuit, when a normal MISFET is used, the vertically stacked transistors QN1 to QN3 are subjected to different substrate biases, and the threshold voltage is apparently different.
[0072]
Therefore, the FD-SODELFET or the PD-SODELFET having the structure shown in FIG. 1 or the PD-SODELFET shown in FIG. On the other hand, p-channel bulkFETs having the same structure as the bulkFET shown in FIG. 16 and having a small leakage due to the parasitic bipolar transistors are used for the p-channel transistors QP1 to QP3. Thereby, operational stability and a high noise margin can be obtained.
[0073]
[Eighth Embodiment]
FIG. 23 shows a dynamic domino circuit. N-channel transistors QN11 to QN13 connected in parallel between nodes N1 and N2 are switching elements whose gates are input terminals A, B, and C, respectively. A precharge p-channel transistor QP11 whose gate is controlled by a precharge signal PRE is provided between the node N1 and the power supply terminal. An activation n-channel transistor QN14 driven by a clock CK is provided between the node N2 and the reference potential terminal. The node N1 is connected to the output terminal OUT via the inverter INV. A p-channel transistor QP12 controlled by the voltage of the output terminal OUT is further provided between the node N1 and the power supply terminal Vdd.
[0074]
In a dynamic circuit driven by such a clock, high speed operation becomes difficult if the capacitance of the node N1 is large. Also, if the source and drain junction capacitances of the transistors QN11 to QN13 are large, the node N1 when the precharge transistor QP11 and the clock transistor QN14 are off and the inputs of A, B, and C are “H”. Are accumulated, and the potential of the node N1 that should hold the “H” level = Vdd is greatly reduced below Vdd. Conversely, when the capacitance is small, the noise margin is lowered. Therefore, it is necessary to optimize the capacitance of the node N1 in relation to the driving capability of the transistors QN11 to QN13.
[0075]
Therefore, for example, FD-SODELFET or PD-SODELFET having the structure shown in FIG. 1 that can keep the capacitance of the node N1 relatively small is used for the transistors QN11 to QN13. A bulk FET having the same structure as the bulk FET shown in FIG. 16 is used for the transistors QN14, QP11, and QP12.
[0076]
Thereby, a circuit capable of high-speed operation can be obtained without reducing the noise margin. That is, when the dynamic circuit of FIG. 23 is configured using only bulk FETs, the capacitance of the node N1 becomes large and it is difficult to charge and discharge it at high speed. However, the transistors N111 to QN13 include the node N1. By using a SODELFET that can keep the capacitance of the capacitor relatively small, high-speed operation becomes possible. Further, the potential to be held at the node N1 can be reliably held.
[0077]
On the other hand, if all of the dynamic circuits in FIG. 23 are configured by SODELFETs, the body region is in a floating state, resulting in a parasitic bipolar transistor effect, and the amount of charge that can be stored in the node N1 is reduced. Deteriorate. Therefore, by using SODELFETs for the transistors QN11 to QN13 and using bulkFETs for the other parts, it is possible to optimize the noise margin and high speed performance that are in a trade-off relationship.
[0078]
Also, differential amplifiers are often used for analog circuits, memory sense amplifier circuits, and the like. For example, in a differential amplifier composed of two CMOS circuits, it is important that the threshold values of the two CMOS circuits are aligned. However, in the case of the SODELFET according to the present invention, since the channel body region is floating, the threshold value may be shifted due to the influence of the past history, and the threshold values of the two CMOS circuits may always be made uniform. It is not easy. Accordingly, in the LSI using the SODELFET according to the present invention, it is preferable to selectively use a differential FET such as a bulkFET.
[0079]
In the LSI using the FD-SODELFET according to the present invention, p / n ^- It is also effective to provide a substrate bias application circuit that selectively applies a substrate bias for adjusting the threshold voltage to the lower p-type layer when the / p structure is provided separately for each element. In particular, as shown in FIG. 14, for the FD-SODELFET in which the p-type layer 9 which is a halo region is formed under the source / drain extension region 7b, by applying a bias to the p-type layer 2, It has been confirmed that the threshold can be adjusted. FIG. 24 shows the drain current Id-gate voltage Vg characteristics when the substrate bias voltage Vsub applied to the p-type layer 2 is changed for the FD-SODELFET shown in FIG. From this characteristic, if the p-type layer 2 is provided separately for each element and a substrate bias application circuit is connected thereto, an LSI in which FD-SODELFETs having different threshold voltages are integrated can be obtained.
[0080]
[Ninth Embodiment]
The NAND gate circuit of FIG. 22 and the dynamic domino circuit of FIG. 23 can be configured by a combination of SOIFET and bulkFET using a partial SOI substrate. FIG. 25 shows an integrated structure of SOIFET and bulkFET using a partial SOI substrate. The partial SOI substrate has an SOI region in which an insulating film 102 such as a silicon oxide film is embedded under a thin silicon layer 103 on the silicon substrate 101, and a bulk region in which an insulating film is not embedded.
[0081]
An SOIFET is formed in the silicon layer 103 in the SOI region of such a partial SOI substrate. The SOIFET has a gate electrode 202 formed on the silicon layer 103 with a gate insulating film 201 interposed therebetween. The source / drain diffusion layer 203 is formed to a depth reaching the insulating film 102. When the silicon layer 103 is thin, the SOIFET becomes a fully depleted element.
[0082]
In the bulk region, an n-type (or p-type) well 301 is formed, a gate electrode 303 is formed on the well 301 via a gate insulating film 302, and a source / drain diffusion layer 304 is formed.
[0083]
The n-channel transistors QN1-Q3 of the NAND gate circuit of FIG. 22 are formed by the SOIFET of FIG. The p-channel transistors QP1-QP3 are formed by the bulk FET of FIG. As a result, high stability and a high noise margin can be obtained for the same reason as described in the seventh and eighth embodiments.
[0084]
The n-channel transistors QN11 to QN13 of the dynamic domino circuit of FIG. 23 are formed by the SOIFET of FIG. The p-channel transistors QP11 and QP12 and the n-channel transistor QN14 are formed by the bulk FET of FIG. Accordingly, high-speed operation can be performed without reducing the noise margin for the same reason as described in the eighth embodiment.
[0085]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a semiconductor device having a transistor that can be miniaturized and improved in performance with a simpler structure using a bulk semiconductor.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a structure of a SODELFET according to an embodiment of the present invention.
FIG. 2 is a diagram showing an impurity concentration distribution in a depth direction of a channel region of the SODELFET.
FIG. 3 is a diagram showing a relationship between a threshold voltage roll-off value δVth and a p-type layer thickness of a SODELFET according to the present invention in comparison with an SOIFET.
FIG. 4 shows a threshold voltage roll-off value δVth and electron mobility μe and n of a SODELFET according to the present invention; ^- It is a figure which shows the relationship with a mold layer thickness.
FIG. 5A shows the p / n of the SODELFET of the same embodiment. ^- It is sectional drawing which shows the element isolation process in the manufacturing process which obtains / p structure.
FIG. 5B is a cross-sectional view showing a p-type layer ion implantation step and a silicon layer epitaxial growth step in the same manufacturing step.
FIG. 5C shows n in the same manufacturing process. ^- It is sectional drawing which shows a type | mold layer ion implantation process.
FIG. 5D is a cross-sectional view showing a p-type layer ion implantation step in the same manufacturing step.
FIG. 6A shows the p / n of the SODELFET of the same embodiment. ^- It is sectional drawing which shows the element isolation process in the other manufacturing process for obtaining / p structure.
FIG. 6B is a cross-sectional view showing a first silicon layer epitaxial step in the same manufacturing step.
FIG. 6C shows n in the same manufacturing process. ^- It is sectional drawing which shows a layer ion implantation process.
FIG. 6D is a cross-sectional view showing a second silicon layer epitaxial step in the same manufacturing step.
FIG. 6E is a cross-sectional view showing a p-layer ion implantation step in the same manufacturing step.
FIG. 7 shows p / n in a manufacturing process for integrating the SODELFET according to the embodiment; ^- FIG. 6 is a cross-sectional view showing a / p structure forming step and an element isolation step.
8 is a cross-sectional view showing a gate electrode formation step and a source / drain extension region formation step in the same manufacturing process; FIG.
FIG. 9 is a cross-sectional view showing a gate sidewall insulating film forming step in the same manufacturing step.
FIG. 10 is a cross-sectional view showing a selective epitaxial growth step of source and drain regions in the same manufacturing step.
11 is a cross-sectional view showing a process of forming a source / drain low resistance region in the same manufacturing process; FIG.
FIG. 12 is a cross-sectional view showing an interlayer insulating film and contact plug formation step in the same manufacturing step.
FIG. 13 is a diagram showing a relationship between a gate length and a threshold voltage roll-off value.
FIG. 14 is a cross-sectional view showing the structure of a SODELFET according to another embodiment.
FIG. 15 is a cross-sectional view showing the structure of a SODELFET according to another embodiment.
FIG. 16 is a cross-sectional view showing an integrated structure of an FD-SODELFET and a bulk FET.
FIG. 17 is a cross-sectional view showing an integrated structure of an FD-SODELFET and a PD-SODELFET.
FIG. 18 is a diagram showing a channel region impurity concentration distribution of the PD-SODELFET of FIG. 17;
19 is a diagram showing drain voltage-drain current characteristics of the PD-SODELFET of FIG.
20 is a diagram showing the drain voltage dependence of the body potential of the PD-SODELFET of FIG.
FIG. 21 is a cross-sectional view showing an integrated structure of a PD-SODELFET and a bulk FET according to another embodiment.
FIG. 22 is a diagram showing a preferred circuit example to which the present invention is applied.
FIG. 23 is a diagram showing another circuit example preferable for applying the present invention.
FIG. 24 is a diagram showing the effect of applying a substrate bias to the FD-SODELFET according to the present invention.
FIG. 25 is a diagram showing an integrated structure of SOIFETs and bulk FETs according to another embodiment.
[Explanation of symbols]
1 ... silicon substrate, 2 ... p-type layer, 3 ... n ^- Type layer, 4 ... p-type layer (channel region), 5 ... gate insulating film, 6 ... gate electrode, 6a ... metal electrode, 6b ... polycrystalline silicon electrode, 7 ... source, drain diffusion layer, 7a ... low resistance region, 7b: extended region, 8 ... sidewall insulating film, 10, 11 ... silicon layer (epitaxial growth layer).

Claims (2)

A semiconductor substrate;
A gate electrode formed on the surface of the semiconductor substrate via a gate insulating film;
A low resistance region formed so as to face the semiconductor substrate with a channel region directly below the gate electrode interposed therebetween, and a lower impurity concentration than the low resistance region formed so as to extend from the low resistance region to the channel region side A source and drain diffusion layer of the second conductivity type composed of a shallow extension region;
A first impurity doped layer of a first conductivity type formed in the channel region between the source and drain diffusion layers;
A second impurity doped layer of a second conductivity type formed under the first impurity doped layer;
A third impurity doped layer of the first conductivity type formed under the second impurity doped layer,
The first impurity doped layer is selectively formed with a junction depth deeper than that of the extension region of the source and drain diffusion layers, and is partially depleted when the channel inversion layer is formed. Concentration and thickness are set,
The second impurity doped layer is selectively formed so that both ends thereof are in contact with the extended regions of the source and drain diffusion layers, and the built-in potential generated between the first and third impurity doped layers. An impurity concentration and a thickness are set so as to be completely depleted by the semiconductor device. The first impurity doped layer is surrounded by a depletion layer formed between the extension regions of the source and drain diffusion layers and the second impurity doped layer that is completely depleted, and is in a floating state. The semiconductor device according to claim 1.

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