JP4921345B2 - Solid-state imaging device and camera - Google Patents

Description

  The present invention relates to a solid-state imaging device and a camera including the solid-state imaging device.

  Conventionally, a CCD is often used as a solid-state imaging device because of its good SN ratio. However, on the other hand, so-called amplification type solid-state imaging devices have been developed which have the advantages of low power consumption and ease of use. An amplification type solid-state imaging device is a device that guides signal charges accumulated in a photodiode to a control electrode of a transistor provided in a pixel, amplifies an output corresponding to the amount of signal charge from the main electrode of the transistor, and outputs the amplified signal. . In particular, a so-called CMOS sensor using a MOS transistor as a transistor has a good matching with the CMOS process, and the drive circuit and the signal processing circuit can be made on-chip, and therefore, development is focused on.

  FIG. 5 is a circuit diagram showing a typical example of a CMOS sensor pixel, in which 1 is a unit pixel, 2 is a photodiode for storing signal charges generated by incident light, and 3 is a signal charge amount. Amplifying MOS transistor that outputs the amplified signal output, 4 is a floating diffusion (hereinafter referred to as FD) region that receives the signal charge and is connected to the gate electrode of the MOS transistor 3, and 5 is a signal charge accumulated in the photodiode 2 in the FD region 4. Is a MOS transistor for resetting the FD region 4, 7 is a MOS transistor for selecting an output pixel, and 8 is a pulse applied to the gate of the MOS transistor 5 to perform a charge transfer operation. Control line 9 for controlling, reset operation by applying a pulse to the gate of MOS transistor 6 A control line 10 for controlling, a control line for applying a pulse to the gate of the MOS transistor 7 to control the selection operation, and 11 a power supply wiring, the drain of the amplifying MOS transistor 3 and the reset MOS transistor 6 The power source potential is supplied to them. Reference numeral 12 denotes an output line for outputting an amplification signal of the selected pixel, 13 denotes a MOS transistor that operates as a constant current source and forms a source follower in cooperation with the amplification MOS transistor 3, and 14 denotes a MOS transistor 13 constant. This is a wiring for supplying a potential for current operation to the gate electrode of the MOS transistor 13. The pixels 1 arranged in a two-dimensional matrix form a pixel region of a two-dimensional solid-state imaging device. In the matrix configuration, the output line 12 is a common line of pixels in each column, control lines 8, 9, Reference numeral 10 denotes a common line for pixels in each row, and only the pixels in the row selected by the control line 10 are signal-outputted to the output line 12.

  Next, the operation of the pixel will be briefly described. For the pixels in the row where the selection MOS transistor is turned on by the control line 10, a pulse is first applied to the control line 9, and the FD region 4 is reset. Since the amplifying MOS transistor 3 and the constant current MOS transistor 13 form a source follower, an output potential corresponding to the reset potential appears on the output line 12. Next, when the signal charge accumulated in the photodiode is transferred to the FD region 4 by applying a pulse to the control line 8, the potential of the FD region 4 changes by a voltage corresponding to the amount of signal charge. The potential change appears on the output line 12 as well. Since the reset potential appearing on the output line 12 includes noise such as variations in threshold voltage values of the amplifying MOS transistor 3 and reset noise when the FD region 4 is reset, the potential change corresponding to the signal charge amount is included. Is a signal that does not contain noise. In the two-dimensional CMOS sensor, a readout circuit for removing this noise and extracting only a signal is connected to the output line 12. In this readout circuit, the above-mentioned noise is removed by a clamp circuit, and the noise and noise + pure signal are held separately, and the noise is eliminated by guiding them to the differential amplifier at the final stage during horizontal scanning readout, etc. Several configurations have been proposed, but they are not directly related to the present invention and will not be described in detail.

  Next, FIG. 6 shows a cross-sectional structure of a pixel photodiode and an amplification MOS transistor. In the figure, 15 is an N-type semiconductor substrate, 16 is a P-type well, 17 is an N-type semiconductor region formed in the well 16, and a photodiode is formed by 16 and 17. Signal electrons generated by the incident light are accumulated. Reference numerals 18 and 19 are formed in the well 16, respectively, N-type semiconductor regions serving as the drain and source of the amplifying MOS transistor 3, 20 the gate electrode of the amplifying MOS transistor 3, and 21 for element isolation commonly referred to as LOCOS. A thick oxide film 22, a channel stopper of a P-type semiconductor layer that is directly under the LOCOS 21 and has the same conductivity as the well 16, 11 is a drain wiring connected to the drain 18, and 23 is a source wiring connected to the source 19. The signal electrons stored in the region 17 are transferred to the FD 4 during the transfer operation, and the N-type impurity concentration in the region 17 is set so that the region 17 is depleted immediately after the transfer.

FIG. 7 of Patent Document 1 discloses a solid-state imaging device in which a p-type buried layer is formed at a predetermined depth from an n-type substrate, and a photoelectric conversion unit is formed on the upper n-type substrate.
JP 2000-150848 A

  However, the conventional CMOS sensor has a problem that so-called 1 / f noise is generated from the amplifying MOS transistor 3 and the noise of the sensor increases. The amplifying MOS transistor 3 is generally operated as a source follower. However, since the potential of the well 16 is fixed to a constant value, the gain during the source follower operation is reduced due to the back gate bias effect. There was a problem that the signal became small. Furthermore, the signal electrons generated below the photodiode are not necessarily absorbed by the photodiode, but are also absorbed by the FD section 4 and the N-type source / drains of the MOS transistors 3, 6 and 7 in the pixel. Is done. As described above, there is a problem that the signal electrons are absorbed by other than the photodiode and the sensitivity is lowered.

  Further, in the pixel structure disclosed in Patent Document 1, since the amplification MOS transistor provided in the pixel is formed in a well having a conductivity type opposite to the source and drain of the amplification MOS transistor, the substrate bias effect is achieved. Cannot be made small enough. Therefore, the gain of the source follower operation cannot be increased.

  Accordingly, an object of the present invention is to provide an amplification type solid-state imaging device having a higher gain and higher sensitivity than conventional amplification type solid-state imaging devices.

  According to a first aspect of the present invention, unit pixels including a photodiode and a first conductivity type amplifying MOS transistor that receives and amplifies a signal charge generated by the photodiode at a gate are arranged on a semiconductor substrate. In the solid-state imaging device, the photodiode includes a first semiconductor region of the first conductivity type and a light receiving surface of the photodiode as a reference from below the first semiconductor region to below the amplification MOS transistor. A second semiconductor region of a second conductivity type that extends, and the source and drain regions of the amplification MOS transistor have the same conductivity type as the source and drain regions, compared to the source and drain regions The source and drain regions of the amplification MOS transistor are disposed in a third semiconductor region having a low impurity concentration. And the second semiconductor region below the amplifying MOS transistor, and at least below a part of the source and drain regions and below the gate of the amplifying MOS transistor. A fourth semiconductor region of the type, and at least during the amplification operation of the amplification MOS transistor, the third semiconductor region is located between the source region and the drain region and above the fourth semiconductor region. The semiconductor region is depleted.
  According to a second aspect of the present invention, a unit pixel including a photodiode and a first conductivity type amplifying MOS transistor that receives and amplifies a signal charge generated in the photodiode at a gate is output to a semiconductor substrate. In the arranged solid-state imaging device, the amplification MOS transistor has a first conductivity type that is the same conductivity type as the source and drain regions of the amplification MOS transistor, and has an impurity concentration lower than that of the source and drain regions. A second semiconductor region of a second conductivity type is disposed at least below the gate of the amplification MOS transistor and below the source and drain regions, and is disposed in the first semiconductor region; Below the gate of the amplifying MOS transistor, the gate insulating film of the amplifying MOS transistor and the first semiconductor region A third semiconductor region of the first conductivity type having an impurity concentration higher than that of the first semiconductor region is disposed in a region in contact with the interface between the source region and the source region, and at least during the amplification operation of the amplification MOS transistor The first semiconductor region is depleted in a region between the drain region and above the second semiconductor region.

  At this time, at least the semiconductor directly under the gate of the amplification MOS transistor reaches the second P-type semiconductor, or the third N-type introduced near the semiconductor interface immediately below the gate. A semiconductor and the first N-type semiconductor are formed. Between the channel of the amplifying MOS transistor and the second P-type semiconductor layer is an N-type semiconductor layer with a low first impurity concentration, the amplifying MOS transistor operates as a source follower, and the source potential is Depletion occurs when a reverse bias is applied to the P-type semiconductor layer potential. Since the capacitance between the channel of the amplification MOS transistor and the second P-type semiconductor layer is reduced by the presence of such a depletion layer having a certain width, the amplification MOS transistor due to the substrate bias effect. Fluctuations in the threshold voltage can be suppressed to a small level, and a decrease in gain during source follower operation can be suppressed. In addition, since the substrate bias effect is small, the effect of pushing carriers flowing through the channel of the amplification MOS transistor to the interface is small, and 1 / f noise generated during the source follower operation can be suppressed to a small value. Further, the second P-type semiconductor layer also serves as a potential barrier that prevents signal electrons generated by light from being absorbed by the source and drain of the N-type MOS transistor around the photodiode, and is absorbed by the photodiode. Can increase the sensitivity of the signal electrons.

  According to the first embodiment of the present invention, it is possible to provide a CMOS solid-state imaging device with low noise, high gain, and high sensitivity.

  Further, according to the second embodiment of the present invention, in addition to the effects of the first embodiment, a further inexpensive CMOS solid-state imaging device can be provided.

(First embodiment)
FIG. 1 is a cross-sectional view of a part of a pixel that best represents the features of the present invention, and shows the cross-sectional structure of a photodiode, an amplifying MOS transistor, and an element isolation portion. The same members are denoted by the same reference numerals and description thereof is omitted. Reference numeral 24 in FIG. 1 denotes an upper portion of an N-type well or N substrate 15. Reference numeral 25 denotes a P-type layer between the N substrate 15 and the N layer 24, and a photodiode is formed by the N-type layer 24 and the P-type layer 25. The impurity concentration of the N layer 17 is set higher than the impurity concentration of the N layer 24, and signal electrons gather at 17. 26 is at least immediately below the gate portion of the N-type MOS transistor in the pixel, and is a P-type semiconductor layer formed deeper than the source and drain, and 27 is more impurity than 24 formed in the channel portion of the amplifying MOS transistor 3. This is an N-type semiconductor layer having a high concentration. The P-type semiconductor layer 26 is provided immediately below at least part of the source and drain regions in order to electrically isolate the N-type semiconductor 24 forming the photodiode from the source and drain of the N-type MOS transistor in the pixel. Is also formed.

  The potential situation during operation of the amplification MOS transistor 3 in the pixel structure as shown in FIG. 1 will be described with reference to FIG. FIG. 2 shows the potential in the depth direction including the gate of the amplifying MOS transistor 3. The horizontal direction is the depth direction, the vertical direction is the potential, and the higher potential is on the lower side. The number indicating each location is the same as the number in FIG. 1, and 28 is a gate oxide film. When the MOS transistor 3 operates as a source follower, it is assumed that there is no influence of the fixed charges in the gate oxide film 28. The potentials of the respective parts constituting the MOS transistor 3 are the drain 18, source 19, and P-type semiconductor layer 26 in order of increasing potential. However, if the source potential is higher than the gate potential, the potential of the channel portion through which carriers flow is higher than that of the gate. Therefore, as shown in FIG. 2, the highest potential in the channel portion is slightly higher than the silicon interface. A so-called buried channel is formed as it enters the silicon. The channel 27 and the P-type semiconductor layer 26 are in a reverse bias state. In the present invention, the N-type semiconductor layer 24 having a low impurity concentration between 26 and 27 is depleted. Therefore, compared with the case where the channel is formed in the P-type semiconductor layer, the capacitance of the channel-P-type semiconductor substrate, that is, the channel-P-type semiconductor layer 26 in FIG. Even if a reverse bias as described above is applied, the effect of pushing the electrons in the channel toward the interface is small, and a buried channel state as shown in FIG. 2 can be realized.

As a specific structural example, the impurity concentration of the N-type silicon semiconductor region 24 is 10 ¹⁵ / cm ³ , the junction depth of the drain 18 and the source 19 of the amplification MOS transistor 3 is 0.4 μm, P-type The semiconductor layer 26 is formed at a depth of 1.0 μm from the semiconductor interface such that the junction depth on the interface side is at a peak of impurity concentration of 1.2 μm, and the N semiconductor layer 27 is 2 × impurity concentration. A gate oxide film formed of 10 ¹⁶ / cm ³ and a junction depth of 0.2 μm and formed of a silicon oxide film has a thickness of 150 mm. If the P-type semiconductor layer 26 is at a potential of 0V and the source potential becomes 1V or higher when the MOS transistor 3 operates as a source follower, the semiconductor region between the N semiconductor layer 27 and the P-type semiconductor layer 26 where the channel is formed 24 is depleted. At this time, the capacitance between the N-type semiconductor layer 27 and the P-type semiconductor layer 26 is about 1/17 of the gate oxide film capacitance and can be ignored. Next, assuming that fixed charges in the gate oxide film are not considered, the N-type semiconductor layer 27 is depleted when it becomes approximately 1 V higher than the potential of the gate 20. Therefore, in the source follower operation in which current flows through a channel formed in the N-type semiconductor layer 27, for example, the source potential is maintained at 0.7V higher than the potential of the gate 20. The channel formed at this time is in the N-type semiconductor layer 27 inside the silicon interface. If the potential of the gate 20 is 0.3 V or higher, the source potential is 1 V or higher, and the semiconductor region 24 between the N-type semiconductor layer 27 and the P-type semiconductor layer 26 in which the channel is formed becomes depleted. Thus, a source follower operation is realized in which the influence of the back gate bias effect is small and the relative relationship with the channel potential and the channel depth are not significantly affected even when the potential of the gate 20 varies.

  In such a buried channel MOS transistor, since the influence of traps existing at the interface with respect to channel electrons is suppressed, 1 / f noise can be reduced as compared with the surface channel MOS transistor. Further, the threshold potential of the amplifying MOS transistor has a small back gate effect, so that the source potential dependency is small, and the gain when the source follower operation is performed becomes high. Furthermore, since the P-type semiconductor layer 26 is also formed below the source and drain of the in-pixel MOS transistor, it acts as a potential barrier for the signal electrons generated in the N-type semiconductor layer 24 by light incidence. It is prevented from being absorbed by the source and drain of the MOS transistor. Therefore, the probability that photogenerated electrons are absorbed by the electron storage layer 17 of the photodiode portion is increased, and the sensitivity can be increased. Therefore, it is possible to provide a CMOS solid-state image pickup device with low noise, high gain, and high sensitivity as compared with the conventional CMOS solid-state image pickup device.

(Second embodiment)
FIG. 3 is a cross-sectional view of a pixel for explaining the second embodiment of the present invention. In this figure, the same members as those in FIG. 1 are given the same numbers, but in FIG. 3, there is no N-type semiconductor layer 27 in FIG. Therefore, when the source follower operation is performed, the degree of embedding of the channel formed in the amplification MOS transistor is weaker than that of the first embodiment and is close to the surface channel, but no impurity ions are introduced into the channel portion. / F Channels causing noise and defects at the silicon interface are few. The substrate bias effect is small as in the first embodiment. Therefore, the 1 / f noise is small and the gain of the source follower operation is high as compared with the N-type MOS transistor having the normal structure formed in the P-type semiconductor layer. Although the sensitivity of the photodiode is the same as in the first embodiment, there is no process step for forming the N-type semiconductor layer 27, so that a CMOS solid-state imaging device to which this embodiment is applied is provided at a lower cost. be able to.

  As for the MOS transistors other than the amplification MOS transistors in the first and second embodiments, the breakdown voltage between the source and the drain is improved in the N-type semiconductor layer 24 from the silicon interface immediately below the gate to the P-type semiconductor layer 26. Therefore, a structure in which a P-type semiconductor layer is introduced may be employed, or the same structure as that of the amplification MOS transistor may be employed. In addition, although the P-type semiconductor layer 26 in the first and second embodiments is formed as a single layer, a single or a plurality of P-type semiconductor layers are provided between the P-type semiconductor layer 25 and the P-type semiconductor layer 26. The structure may be formed to further strengthen the electrical continuity between the P-type semiconductor layer 25 and the P-type semiconductor layer 26. Further, a so-called embedded photodiode in which a P-type semiconductor layer is formed at the semiconductor interface portion of the N-type layer 17 where signal electrons are accumulated may be used.

  A structure in which all the N-type and P-type polarities in the description of the present invention are reversed may be used.

(Third embodiment)
Based on FIG. 4, an embodiment in which the solid-state imaging device of the present invention is applied to a still video camera will be described in detail.

  FIG. 4 is a block diagram showing a case where the solid-state imaging device of the present invention is applied to a “still video camera”.

  In FIG. 4, 101 is a barrier that serves as a lens protect and main switch, 102 is a lens that forms an optical image of a subject on a solid-state imaging device (solid-state imaging device) 104, and 103 is a variable for changing the amount of light passing through the lens 102. 104, a solid-state imaging device 104 for capturing an object imaged by the lens 102 as an image signal, 106 an A / D converter for performing analog-digital conversion of an image signal output from the solid-state imaging device 104, 107 Is a signal processing unit that performs various corrections on the image data output from the A / D converter 6 and compresses the data. 108 is a solid-state imaging device 4, an imaging signal processing circuit 105, an A / D converter 106, and signal processing. The timing generator 109 outputs various timing signals to the unit 107, and 109 is an overall control for controlling various operations and the entire still video camera. An arithmetic unit 110, a memory unit for temporarily storing image data, 111 an interface unit for recording or reading on a recording medium, and 112 a semiconductor memory for recording or reading image data A removable recording medium 113 is an interface unit for communicating with an external computer or the like.

Next, the operation of the still video camera at the time of shooting in the above configuration will be described.
When the barrier 101 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 106 is turned on.

  Then, in order to control the exposure amount, the overall control / arithmetic unit 109 opens the aperture 103, and the signal output from the solid-state image sensor 104 is converted by the A / D converter 106 and then sent to the signal processing unit 107. Entered.

  Based on this data, exposure calculation is performed by the overall control / calculation unit 109.

  The brightness is determined based on the result of the photometry, and the overall control / calculation unit 109 controls the aperture according to the result.

  Next, based on the signal output from the solid-state image sensor 104, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 109. Thereafter, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts.

  When the exposure is completed, the image signal output from the solid-state imaging device 104 is A / D converted by the A / D converter 106, passes through the signal processing unit 107, and is written in the memory unit by the overall control / calculation unit 109.

  Thereafter, the data stored in the memory unit 110 is recorded on a removable recording medium 112 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 109.

  Further, the image processing may be performed by directly entering the computer or the like through the external I / F unit 113.

  The present invention can be used in a camera that captures images.

1 is a cross-sectional structure diagram of a pixel for explaining a first embodiment of the present invention. It is a potential diagram at the time of pixel operation for explaining the first embodiment of the present invention. It is sectional drawing of the pixel for demonstrating 2nd embodiment of this invention. It is a block diagram which shows the structure of the still video camera by 3rd embodiment of this invention. It is a circuit diagram of the conventional pixel. It is a cross-sectional structure diagram of a conventional pixel.

Explanation of symbols

1 pixel 2 photodiode 3 amplification MOS transistor 4 floating diffusion 5 signal charge transfer MOS transistor 6 reset MOS transistor 7 selection MOS transistor 8 gate control line 9 gate control line 10 gate control line 11 power supply line 12 pixel output line 13 Constant current supply MOS transistor 14 Gate control line 15 Semiconductor substrate 16 Semiconductor well 17 Photodiode region 18 Drain region 19 Source region 20 Gate 21 Element isolation region 22 Channel stopper 23 Wiring 24 N-type semiconductor layer 25 P-type semiconductor layer 26-type semiconductor Layer 27 N-type semiconductor layer 104 Solid-state imaging device (solid-state imaging device)

Claims (6)

A photodiode, in the solid-state imaging device unit pixel is an array on a semiconductor substrate including a first conductivity type amplifying MOS transistor for outputting a signal charge generated by the photodiode is amplified by receiving a gate,
The photodiode includes a first semiconductor region of a first conductivity type, said photodiode second conductivity type extending to below the amplifying MOS transistor from the lower side of the first semiconductor region, based on the light receiving surface of the A second semiconductor region, and
The source and drain regions of the amplifying MOS transistor are disposed in a third semiconductor region having the same conductivity type as the source and drain regions and a lower impurity concentration than the source and drain regions,
It is between the second semiconductor region in the lower of the source and drain regions and the amplifying MOS transistor of the amplifying MOS transistor, at least a portion of the lower and the amplifying MOS transistor of the source and drain regions beneath the region of the gate of the fourth semiconductor region of the second conductivity type is disposed,
At least during the amplification operation of the amplification MOS transistor, the third semiconductor region is depleted in the region between the source region and the drain region and above the fourth semiconductor region.
A solid-state imaging device. In the solid-state imaging device according to claim 1, wherein a lower gate of the amplifying MOS transistor, the third of said source and drain regions are disposed in the amplifying MOS transistor and the gate insulating film of the amplifying MOS transistor A solid-state imaging device, wherein a fifth semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region is disposed in a region in contact with the interface with the semiconductor region.   3. The solid-state imaging device according to claim 2, wherein the amplification MOS transistor has a buried channel. A photodiode, in the solid-state imaging device unit pixel is an array on a semiconductor substrate comprising an amplifying MOS transistor of a first conductivity type and outputting the amplified received in the gate of the signal charge generated by the photodiode,
The amplification MOS transistor has a first conductivity type that is the same conductivity type as the source and drain regions of the amplification MOS transistor, and is disposed in a first semiconductor region having a lower impurity concentration than the source and drain regions. Has been
A lower gate of at least the amplifying MOS transistor, a second semiconductor region of a second conductivity type disposed below said source and drain regions,
In the region below the gate of the amplification MOS transistor and in contact with the interface between the gate insulating film of the amplification MOS transistor and the first semiconductor region, the impurity concentration higher than that of the first semiconductor region is provided. A third semiconductor region of one conductivity type is disposed;
During amplification operation of at least the amplifying MOS transistor, said first semiconductor region in the upper region of the second semiconductor region a between the source region and the drain region are you depleted,
A solid-state imaging device.   5. The solid-state imaging device according to claim 4, wherein the amplification MOS transistor has a buried channel.   A camera comprising the solid-state imaging device according to claim 1.