JP2002151599A - Semiconductor integrated circuit device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve noise characteristics of a semiconductor integrated circuit device with an analog/digital coexisting. SOLUTION: The gate insulation film 3 of MSI.FETQ constituting the analog circuit of the analog/digital coexisting circuit is constituted of an acid nitride film and at least one MIS.FETQ constituting the analog circuit is turned to a structure provided with a depression type buried channel layer 5b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly, to a so-called analog / digital device in which an analog circuit and a digital circuit are mixed on the same semiconductor chip (hereinafter simply referred to as a chip). The present invention relates to a technique effective when applied to a semiconductor integrated circuit device having a mixed circuit.

[0002]

2. Description of the Related Art With the rapid progress of microfabrication technology, 1
The number of elements that can be mounted on a chip is steadily expanding. For this reason, a system composed of a plurality of chips is replaced with a system LSI (Layer) composed of one chip.
(rge scale integrated circuit) or system-on-chip. Under these circumstances, development and manufacture of the analog / digital mixed circuit have been advanced.

The analog / digital mixed circuit studied by the present inventors is, for example, a general signal processing LSI used for a video camera, a digital still camera, and the like.
It is mainly composed of an insulated gate field effect transistor (hereinafter simply referred to as a field effect transistor).

By the way, the gate length and the gate insulating film thickness of the field effect transistor tend to be reduced as the degree of device integration of the system LSI is improved. Therefore, in order to avoid such a problem, a gate insulating film of the field effect transistor is formed of an oxynitride film.

[0005]

However, in the technique of forming the gate insulating film of the field effect transistor constituting the mixed analog / digital circuit with an oxynitride film,
The present inventor has found the following problems.

That is, when the gate insulating film is formed of an oxynitride film, the hot carrier phenomenon and the impurity penetration phenomenon can be suppressed or prevented. However, the interface state of the gate insulating film increases and 1 / f noise (low noise) occurs. Frequency noise) increases.
This 1 / f noise does not cause much problem in a digital circuit, but there is a problem in an analog circuit that its noise characteristic is greatly deteriorated.

For example, a problem arises in a first stage amplifier and an operational amplifier for amplifying a signal from a CCD (Charge Coupled Device) of a video camera or a digital still camera.
It is necessary to reduce f noise. Also, for example, a case where a microprocessor or the like has a built-in voltage controlled oscillator (VCO) as a reference for the oscillation frequency, or a case where a phase locked loop (PLL) for adjusting the phase of the oscillation frequency of the VCO to an external clock is formed. Also, a problem due to 1 / f noise occurs. If the 1 / f noise of the transistor used in the VCO is large, there arises a problem that the phase of the clock frequency is fluctuated by the noise. Further, as an example of an analog / digital mixed circuit in which 1 / f noise is a problem, there is a radio frequency (RF) signal processing chip such as a mobile phone. The baseband signal is processed by a digital circuit, and the RF section is also the same CMOS (Complementary MO).
S) Noise is a problem when designing circuits with devices.
For example, a VCO that oscillates an RF band signal is one example. If 1 / f noise is present, phase noise, which is a problem in the VCO, is degraded, and problems such as insufficient separation from adjacent channels required for mobile communication occur. Therefore, there is a problem that it is difficult to apply the technology in which the gate insulating film is formed of the silicon oxynitride film to an analog / digital mixed circuit.

The present inventors have also investigated known examples based on the results of the present invention from the viewpoint of an analog / digital mixed circuit and hot carriers. As a result, for example,
Japanese Patent Application Publication No. 0-77533 discloses a technique in which a gate insulating film is formed separately for an analog circuit and a digital circuit. Also, for example, in Japanese Patent Application Laid-Open No. 7-32220,
A structure is disclosed in which a digital circuit is a surface channel and an analog circuit is a buried channel.

An object of the present invention is to provide a technique capable of improving the noise characteristics of a semiconductor integrated circuit device having an analog / digital mixed circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the present invention, a gate insulating film of a plurality of field effect transistors forming an analog circuit and a digital circuit formed on the same semiconductor substrate is formed of an oxynitride film, and at least one of the analog circuits is formed. The field effect transistor is a depletion type, and a buried channel layer is provided in a channel forming region.

Further, in the present invention, the predetermined field-effect transistor is constituted by an N-channel type field-effect transistor, the gate electrode is N-type, and the buried channel layer is N-type.

Further, according to the present invention, in the semiconductor integrated circuit device having the analog circuit and the digital circuit, the electric field effect of the at least one depletion type buried channel layer in which a negative gate bias is particularly applied to a circuit for which noise generation is to be suppressed. Even when using transistors,
Since the enhancement type field effect transistor is combined, it is possible to prevent power loss at the time of no signal or standby of the circuit.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the present invention in detail,
The meaning of the terms in the present application is as follows.

1. Oxynitride film: A film structure in which a predetermined amount of nitrogen exists at an interface between a semiconductor substrate and a gate insulating film.

2. Surface channel: a structure in which a channel current flows on the surface of a semiconductor substrate when a gate voltage is applied to a transistor under circuit operating conditions.

3. Buried channel: A structure in which a channel current flows on the surface of a semiconductor substrate and inside the semiconductor substrate when a gate voltage is applied to a transistor under circuit operating conditions.

4. Enhancement transistor: A transistor having a structure in which a channel is formed between a source and a drain and a channel current flows only when a voltage higher than a threshold value is applied between the gate and the source. Normally, the channel current does not flow, and the switch characteristic is an off state.

[5] Depletion type transistor: A transistor having a structure in which current flows between the source and the drain even when the gate voltage is zero.

In the following embodiments, where necessary for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments, but unless otherwise specified, they are not irrelevant to each other. One has a relationship with some or all of the other, such as modified examples, details, and supplementary explanations.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), the number is particularly limited and is limited to a specific number in principle. Except in some cases, the number is not limited to the specific number, and may be more than or less than the specific number.

Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified, and when it is deemed essential in principle. Needless to say, there is nothing.

Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the constituent elements, etc., unless otherwise specified, and unless otherwise apparently in principle, it is considered that they are substantially the same. And those similar or similar to the shape or the like. This is the same for the above numerical values and ranges.

In all the drawings for describing the present embodiment, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

Further, in the present embodiment, a MISFET (Metal Insula
tor Semiconductor Field Effect Transistor)
S is abbreviated, P-channel MIS-FET is abbreviated as PMIS, and N-channel MIS-FET is abbreviated as NMIS.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Embodiment 1) First, before describing this embodiment, problems in an example of an analog / digital mixed circuit studied by the present inventors will be described with reference to FIGS. 37 and 38.

A CMIS (Complementary) for a video camera or a still camera including a 10-bit A / D converter in which an analog circuit and a digital circuit are mixed on the same chip.
MIS) A / D (A / D)
A tailing noise and a horizontal noise were generated in an image subjected to (nalog-to-Digital) conversion. As a result of analyzing the cause by the present inventors, 1/1 / MIS of the amplifier circuit constituting the analog circuit was found.
It was found that f noise (low frequency noise) was the cause. This is because, in the miniaturized CMIS process, the oxynitride film is used for the gate insulating film of the MIS to prevent hot carriers and the like, the level of the interface of the gate insulating film increases, and 1 / f
This is probably because noise increases.

FIG. 37 shows the amount of oxynitridation of the gate insulating film obtained by the present inventors, the hot carrier lifetime, and
6 is a graph showing a relationship with / f noise intensity. FIG. 37
From this, it can be seen that increasing the amount of oxynitridation of the gate insulating film improves the hot carrier lifetime, but increases 1 / f noise. That is, in an analog / digital mixed circuit, there is a conflicting demand between measures for miniaturization (measures against hot carriers) and reduction of 1 / f noise, and it is an issue to solve this.

FIG. 38 schematically shows the cause of the 1 / f noise. On the semiconductor substrate 60, a surface channel type MISQ60 is formed. Reference numeral 61 denotes a gate insulating film made of an oxynitride film, 62 denotes a gate electrode, 63 denotes a source, 64 denotes a drain, 65 denotes a surface channel layer, Ce1 denotes a flow of electrons flowing through the surface channel layer 65, and Ce2 denotes a scattering of the electrons. , Te are the semiconductor substrate 60 and the gate insulating film 61.
2 shows electrons trapped near the interface with. 1 /
The f noise is generated when electrons flowing on the surface of the semiconductor substrate 60 undergo modulation such as scattering Ce2 due to electrons Te trapped near the interface between the gate insulating film 61 and the semiconductor substrate 60.

In order to solve this problem, it is possible to separately form gate insulating films for the analog circuit and the digital circuit, but the process becomes complicated and the manufacturing time and cost are increased. Further, in a CMIS device having a technique different from that of the present invention but having only an analog circuit, a PMI
Since 1 / f noise of S is 1 digit smaller than that of NMIS, PMIS is applied to the input differential pair such as CMIS operational amplifier.
There are technologies that use devices. Also, mobile phones such as GSM and Bluetooth, where phase noise is important,
h) and other RF (Radio Frequency) band oscillation circuits (VC
O) is realized by CMIS.
There is a technique using only MIS for a circuit. These have a certain effect when the gate insulating film is a wet oxide film that has not been subjected to nitriding treatment. However, when a gate insulating film is subjected to nitriding treatment in an analog / digital mixed circuit as in the technique of the present invention, 1 / f noise is reduced by one digit or more compared to a wet oxide film not subjected to nitriding treatment.
Unless any measures are taken, it is difficult to solve the problem of significantly deteriorating the noise characteristics in the analog circuit section.

Next, an embodiment of the present invention will be described. From the viewpoint of improving the hot carrier breakdown voltage in a digital circuit, it is essential to use an oxynitride film, so it is assumed that an oxynitride film is used as the gate insulating film. In order to reduce 1 / f noise in analog circuits, considering the vertical structure of the MIS, if the channel through which the current flows is made not at the interface of the gate insulating film but at a deep portion, the effect of the interaction between the current and the interface will be obtained. 1 / f noise can be reduced.

Therefore, in the present embodiment, the following is performed. In an analog / digital mixed circuit, a gate insulating film of a MIS constituting an analog circuit and a digital circuit is formed of an oxynitride film. For the MIS which causes 1 / f noise in the analog circuit, a buried channel structure can be used by ion implantation, and a MIS having a surface channel structure can be used for other MIS. By doing so, it is possible to achieve both miniaturization measures such as hot carrier measures and the problem of 1 / f noise. Further, since only the channel implantation is used, the manufacturing process is not complicated. Therefore, the development and manufacturing time of a semiconductor integrated circuit device having an analog / digital mixed circuit can be shortened. Further, it is possible to promote the cost reduction of a semiconductor integrated circuit device having an analog / digital mixed circuit. Hereinafter, a specific configuration of the present embodiment will be described in detail.

FIG. 1 is a diagram showing the buried channel structure and the reason why 1 / f noise is reduced in the buried channel structure. The MISQ is formed on the semiconductor substrate 1. This MISQ is formed by a pair of semiconductor regions 2 for source and drain formed on the semiconductor substrate 1.
And a gate insulating film 3 and a gate electrode 4.
The gate insulating film 3 is made of the above oxynitride film. here,
The gate insulating film 3 is formed, for example, by performing a nitriding process on a silicon oxide film. A surface channel layer 5a is formed below the gate electrode 4 in the surface layer of the semiconductor substrate 1, and a buried channel layer 5b is formed deeper than the surface channel layer 5a. The symbol Ce3 indicates the flow of electrons flowing through the buried channel layer 5b.

In such a buried channel structure, compared with a surface channel type MIS, electrons as carriers flow in a state of spreading in the depth direction. Carriers that flow deeper from the surface of the semiconductor substrate 1 are less likely to be modulated by the trapped electrons Te. Therefore, the rate of modulation can be reduced in terms of the total current, so that 1 /
f noise can be reduced.

FIG. 2 shows NMISQ according to the present embodiment.
FIG. 3 is a cross-sectional view of a main part showing a structure of an N buried channel.
A buried channel type NMISQN is formed in the P-type well layer PWL formed on the semiconductor substrate 1. Reference numeral 2n indicates an N ⁺ -type semiconductor region for the source and drain of the NMISQN, and reference numeral 5N indicates an N-type channel layer. The N-type channel layer 5N has the surface channel layer 5a and the buried channel layer 5b.

The feature of this structure is that the N-type channel layer 5N
Is N-type despite being NMISQN. The gate electrode 4 having the NMIS buried channel structure has both an N-type and a P-type.
When the gate electrode 4 is a P-type, the threshold voltage of the NMISQN is positive, that is, the enhancement-type NMISQN
become. On the other hand, when the gate electrode 4 is N-type,
The threshold voltage of QN is negative, that is, a depletion-type MIS. This embodiment relates to a case where a depletion-type MIS in which the gate electrode 4 is an N-type is used for an analog circuit portion.

FIG. 3A is an enlarged sectional view of a main part of the semiconductor substrate 1 in a region A of FIG. FIG. 3 (a)
FIG. 3 (b) shows the impurity concentration distribution. FIG. 3 shows parameters characterizing the embedded channel structure of the NMISQN of FIG. The parameters that characterize the structure of the buried channel of NMISQN are the concentration Nd of the N-type channel layer 5N, the concentration Xjd of the N-type channel layer and the concentration Na of the P-type well layer PWL.

FIGS. 4 to 8 show the operation of the buried channel structure of the NMISQN in the state of the region A (FIG. 4A).
FIG. 2 is a diagram showing the potential distribution (potential distribution (b) in each drawing).

In the figure, Xs is the surface depletion layer width, Xc is the conduction layer width in the N-type channel layer, Xn is the depletion layer width in the N-type channel layer,
Xp is the width of the depletion layer in the P-type well layer. The N-type channel layer width Xjd is equal to Xs + Xc + Xn. When the gate voltage is zero, a conduction layer in the N-type channel layer exists between the depletion layer in the N-type channel layer and the surface depletion layer, and a current flows in this portion (FIG. 4). As the gate voltage is increased to the negative side, the surface depletion layer becomes wider, the conduction layer in the N-type channel layer disappears, and the device turns off (FIG. 5). FIG. 6 shows FIG.
This is the case where the gate voltage is zero, as in the case of FIG. In this state, when a positive gate voltage is applied, the surface depletion layer becomes narrower,
Eventually, it completely disappears (FIG. 7). When the gate voltage is further increased, an N-type strong inversion layer is formed on the surface, and most of the current flows on the surface (FIG. 8).

Next, FIG. 9 to FIG. 12 are energy band diagrams showing physical phenomena which give a limiting condition to a parameter characterizing the structure of the NMISQN buried channel. CB indicates a conduction band, VB indicates a valence band, and Eg indicates an energy gap. FIG.
1, the symbol TL in FIG. 12 indicates an inter-band tunnel leak, and the symbol Ψsmax indicates the maximum value of the potential Ψs.

When the gate voltage is applied to the negative side in the flat band state (FIG. 9), the surface band is bent, and a surface depletion layer is formed (FIG. 10). Further, the gate voltage is increased to the negative side, and the valence band VB on the surface is increased.
Reaches a position equal to the conduction band CB of the conduction layer in the N-type channel layer, electrons e1 of the valence band VB are transferred to the conduction band CB,
The band-to-band tunnel starts, and the NMISQN cannot be turned off (FIG. 11). In order to turn off the NMISQN without causing a band-to-band tunnel leak current, it is necessary to eliminate the conduction layer in the N-type channel layer below a gate voltage at which a band-to-band tunnel occurs (FIG. 12). This condition provides one constraint on the parameters that characterize the structure of the NMISQN embedded channel. This condition is called a first condition. When the first condition is expressed by a specific expression, it is expressed by the following expression (1) or expression (2). here,
Wd can be expressed by the following equation (3), and ψbi can be expressed by the following equation (4). In the formula, q is an elementary charge, ε is a dielectric constant of silicon,
k is Boltzmann's constant, T is temperature, and ni is the intrinsic carrier concentration.

[0044]

(Equation 1) FIG. 13 and FIG. 14 are schematic diagrams for giving a restriction condition for the structural parameter defined by the resistance condition of the N-type channel layer 5N. FIG. 13 is a diagram showing a state of an electron flow Ce between the source semiconductor region 2Ns and the drain semiconductor region 2Nd. The region where electrons flow (that is, the N-type channel layer 5N) can be regarded as a cubic conductive layer as shown in FIG. The symbol L is a dimension in the direction along the electron flow Ce in the conductive layer, and indicates the length of the conductive layer. The symbol W is a dimension in a direction intersecting the electron flow Ce, and indicates the width of the conductive layer. Reference symbol D indicates the depth of the conduction layer, and the conduction layer width Xc in the N-type channel layer.
(= Xjd-Xn). The resistance value (sheet resistance) of this conductive layer needs to be smaller than the value specified by the circuit performance. This condition is called a second condition. When the second condition is expressed by a specific expression, it is expressed by the following Expression (5) or Expression (6). Here, μ is the mobility of electrons in silicon, and Ron is the maximum resistance value defined by the circuit performance.

[0045]

(Equation 2) According to equations (5) and (6), the N-type channel layer width Xjd
Needs to satisfy the following equation (7).

[0046]

(Equation 3) FIG. 15 illustrates the conditions to be satisfied by the N-type channel layer width Xjd represented by the equation (7). The above first condition C
1 indicates an upper limit defined in the cut-off condition of the MIS. The second condition C2 indicates a lower limit (Ron = 1 Ωcm) defined by the resistance value. Further, condition C3
Indicates conditions for forming the N-type channel layer 5N. FIG. 16 is a diagram showing the result of verifying the validity of the above equation (7) by device simulation. The white circles indicate normal operation, the black squares indicate punch-through, and the black triangles indicate threshold voltages Vth> −0.8. As shown in FIG. 16, it can be seen that the normally operating structure obtained from the device simulation shows a good match with the condition represented by the equation (7).

FIG. 17 is a diagram for explaining a range of a gate voltage for realizing a state where 1 / f noise is suppressed. This FIG.
Are MIs with depletion-type buried channels
The current value and the transconductance (gm) value with respect to the gate voltage of S are shown. The symbol SCA indicates the region of the surface channel layer 5a.

A current starts to flow when the gate voltage is, for example, about -1.0 V (threshold voltage), and the transconductance (gm) increases almost linearly with the gate voltage. When the gate voltage is, for example, 0.7 V or more, the increase in the transconductance (gm) starts to be suppressed, and when the gate voltage is, for example, 1.2 V or more, the transconductance (gm) decreases. This is because the ratio of the MIS flowing on the surface of the semiconductor substrate in the total current increases due to the increase in the gate voltage, and the mobility deteriorates due to the increase in the scattering of the surface of the semiconductor substrate 1. It is. In other words, in the non-transconductance (gm) degraded region GmA of FIG. 17, it means that the ratio of the surface current to the total current is small. Therefore, 1
The range of the gate voltage at which the MIS can be operated with the / f noise suppressed is the non-transconductance (g
m) Degraded area GmA. In the present embodiment, by using the depletion type, the non-transconductance (gm) degraded region GmA, that is, the range in which the transconductance (gm) linearly increases, and the range just before shifting to the surface channel ( Hereinafter, the region G in FIG.
mA is referred to as “operating region”). Specifically, the following is performed. That is, basically, a thin and wide N-type channel layer 5 is formed by implanting, for example, phosphorus or arsenic into the channel formation region of NMISQN in the semiconductor substrate 1. And NMISQ
The work function difference ΦMS between the gate electrode 4 and the semiconductor substrate 1 (p-type well layer PWL) is increased by using the N gate electrode 4 as an N type. By thus increasing the work function difference ΦMS, the range of the electric field exerted on the semiconductor substrate 1 can be increased in the depth direction of the semiconductor substrate 1 even with a small gate voltage. Therefore, the NMIS QN can be of a depletion type while the threshold voltage of the NMIS QN is lowered so as not to be excessively lowered, and the operating region of the NMIS QN can be widened.

FIG. 18 shows the relationship between the gate voltage and the current of a MIS having an enhancement type surface channel. The surface channel type MIS has a higher transconductance (gm) than the buried channel MIS.
Unsaturated region (region corresponding to operation region GmA in FIG. 17)
When operating in this region, it is difficult to obtain a sufficient drive current as seen in the buried channel type NMISQN.

The limiting conditions for the parameters characterizing the structure of the embedded channel shown in the above equations (1) to (7) can be further simplified by introducing approximations. The approximation to be introduced is that the concentration of the N-type channel layer 5N is equal to the concentration of the P-type well layer PWL (the following equation (8)).

[0051]

(Equation 4) Also, it is sufficient that the resistance value specified by the circuit is smaller than infinity (the following equation (9)).

[0052]

(Equation 5) From the above equation (8), the following equation (10) is obtained.

[0053]

(Equation 6) Here, the WA of the above equation (10) is given by the following equation (11).

[0054]

(Equation 7) By the approximations shown in the above equations (8) and (10),
The above equations (3) and (4) are approximated as in the following equations (12) and (13), respectively. In summary, the N-type channel layer width Xjd needs to satisfy Expression (14).

[0055]

(Equation 8) FIG. 19 is a diagram illustrating the above equation (14) obtained by approximation. In FIG. 19, Wa is the width of the depletion layer 6 formed by the junction between the source semiconductor region 2Ns and the P-type well layer PWL. According to the above equation (14), N
The type channel layer width Xjd must be larger than 0.7 times and smaller than 1.7 times the width Wa of the depletion layer 6 formed by the junction between the source semiconductor region 2Ns and the P-type well PWL. . If the N-type channel layer width Xjd is 0.
If it is smaller than 7 Wa, the resistance R becomes high and a current cannot be sufficiently supplied. On the other hand, the N-type channel layer width Xjd
Is larger than 1.7 Wa, cutoff cannot be performed, and a leak current flows even when the gate voltage is set to zero.

FIG. 20 is a diagram showing the electron concentration obtained by device simulation. As shown in FIG. 20, in the NMISQN having the buried channel structure, it can be seen that as the gate voltage increases, the ratio of electrons flowing on the surface increases.

Next, a specific configuration example of the analog / digital mixed circuit of the present embodiment will be described. FIG. 21 is a plan view of a chip having the mixed analog / digital circuit.

The chip 1C has, as a main element, a semiconductor substrate 1 made of, for example, a plane rectangular silicon single crystal, and has a main surface (device formation surface) on an analog circuit area AA.
And a digital circuit area DA. The case where an analog circuit such as an amplifier circuit having a differential pair is formed in the analog circuit area AA is illustrated. In the present embodiment, only a part of the MIS constituting the analog circuit has a depression type buried channel structure. That is, all the MISs constituting the analog circuit
Is not a depletion-type buried channel, but a MIS in which 1 / f noise is a problem is used as the depletion-type buried channel. Here, the input N, which is a differential pair of a differential amplifier constituting an analog circuit, is used.
MISQN has the above-described depression type buried channel structure, and other NMISQNA and PMISQ
PA has an enhancement type surface channel structure.

By doing so, both the measures for miniaturization (improvement of hot carrier resistance) as described above and the 1 / f noise countermeasures in the analog circuit can be achieved, and the following effects can be obtained.

In other words, the depletion type is difficult to turn off when the circuit is on standby, so that if all the MISs of the analog circuit are depletion type, the circuit design may be difficult. In this embodiment, the depletion type is not used. Since it is used only for a part, the above-mentioned effect can be obtained without impairing the easiness of circuit design.

Further, by using NMISQN for the input of the amplifier circuit, the mobility of the carrier can be relatively increased, and the mutual conductance (gm) can be increased.
It is possible to realize a high-speed and high-bandwidth amplifier circuit. In addition, NMISQN has a smaller short channel effect and higher output resistance than PMIS, so that the gain of the amplifier circuit can be sufficiently improved. Further, the threshold voltage can be stabilized. However, the analog circuit to which the present invention is applied is not limited to an amplifier circuit. This structure is also effective when, for example, an oscillation circuit or the like is formed in the analog circuit area AA. This is because 1 / f noise caused by using an oxynitride film as the gate insulating film of the MIS constituting the oscillator circuit also causes a problem. The configuration of the oscillation circuit will be described later.

Further, a case is exemplified where a digital circuit having a logic gate circuit such as an inverter circuit INV is formed in the digital circuit area DA. The digital circuit is not limited to the one including the inverter circuit, and can be variously changed. For example, a NAND circuit, a NOR circuit, an AND circuit, or N
Other logic gate circuits such as an OR circuit may be formed.

Such an analog circuit and a digital circuit are constituted by, for example, a CMIS circuit. However,
The circuit is not limited to the CMIS circuit, and for example, a so-called Bi-CMIS (Bipolar Complementary MIS) circuit in which a bipolar transistor and a CMIS circuit are mixed may be used. In a product using a Bi-CMIS circuit, since the operation speed is improved and the channel length of the MIS of the digital circuit is reduced, it is considered that the oxynitriding of the gate insulating film is indispensable. Therefore, if no measures are taken, a problem of 1 / f noise in an analog circuit occurs. According to the present embodiment, since such a problem can be avoided, even in a mixed analog / digital circuit having a Bi-CMIS circuit, compatibility between miniaturization and reduction of 1 / f noise in the analog circuit can be achieved. Is possible.

In the vicinity of the long side of the main surface of the chip 1C, a plurality of bonding pads BP are formed along the long side.
Are arranged side by side. This bonding pad BP
Are electrically connected to the analog / digital mixed circuit and constitute connection terminals between the analog / digital mixed circuit and external devices.

Next, the vertical structure of the analog / digital mixed circuit will be described with reference to FIG. FIG. 22 is a sectional view of a main part of FIG.

On the main surface (device formation surface) side of the semiconductor substrate 1, a P-type well layer PWL and an N-type well layer NWL are formed. The P-type well layer PWL contains, for example, boron. Further, the N-type well layer NWL includes
For example, it contains phosphorus or arsenic.

In the isolation region of the semiconductor substrate 1, for example, a trench-type isolation portion (trench isolation) 7 is formed. The isolation portion 7 is formed by burying an insulating film such as a silicon oxide film in a groove extending in the thickness direction of the semiconductor substrate 1 from the main surface of the semiconductor substrate 1. Note that the separation unit 7 is provided with a LOCOS (Local Oxid
(Siliconization of Silicon) method.

On the main surface of the semiconductor substrate 1, the NMIS QN, QN
A, QND and PMISQPA, QPD are formed.

The NMISQN of the analog circuit has a depression type buried channel structure as described above. In addition, NMISQNA and PM
ISQPA has an enhancement-type surface channel structure. Further, the digital circuits NMISQND and PMISQPD have an enhancement type surface channel structure. NMISQND of digital circuit
The channel length of PMISQPD is the shortest, for example, about 0.35 μm.

The gate electrodes 4 of these NMIS QN, QNA, QND and PMISQPA, QPD
Made of polycrystalline silicon. In this case, the work function difference Φ
As for MS, NMIS QN, QNA, and QND side
It becomes larger than the ISQPA and QPD sides. Thus, each NMIS QN, QNA, QND and PMISQPA,
By making the gate electrode 4 of the QPD the same, the manufacturing process of a semiconductor integrated circuit device having an analog / digital mixed circuit can be simplified. Therefore, the development and manufacturing period of the semiconductor integrated circuit device can be shortened. Further, cost can be reduced.

The gate electrode 4 may have a so-called polycide structure in which a silicide layer such as cobalt silicide or tungsten silicide is provided on an N-type polycrystalline silicon film. In addition, the gate electrode 4 may have a so-called polymetal structure in which a metal film such as tungsten is provided on an N-type polycrystalline silicon film via a barrier layer such as tungsten nitride or titanium nitride. Further, the gate electrode 4 may be formed of a single metal film. In this case, to form an N-type gate, for example, aluminum (Al), tantalum (Ta),
Molybdenum (Mo), titanium (Ti), hafnium (H
f), tantalum nitride (TaN) or niobium (Nb) may be used. When a middle gap gate is used, for example, tungsten (W), ruthenium (R
u), cobalt (Co), chromium (Cr) or palladium (Pd) may be used.

Here, the structure in which the gate electrode 4 is formed by the ordinary photolithography technique and the dry etching technique is illustrated, but the invention is not limited to this. For example, a structure in which a gate electrode is formed by a so-called damascene method in which a groove is formed in an interlayer insulating film provided on the main surface of the semiconductor substrate 1 and a conductive film is embedded in the groove. Note that a sidewall 8 is formed on a side surface of the gate electrode 4. The sidewall 8 is made of, for example, a silicon oxide film.

The gate insulating films 3 of these NMIS QN, QNA, QND and PMISQPA, QPD are made of oxynitride films. Here, the gate insulating film 3 is formed by, for example, performing a nitriding process on a silicon oxide film. Thereby, these NMIS QN, QNA, QND
In addition, in the PMISQPA and QPD, particularly, in the gate insulating film 3 of the NMISQND and the PMISQPD of the digital circuit having a relatively short channel length and a relatively high operation speed, the generation of the interface state can be suppressed.
Since the number of trapped electrons in the gate insulating film 3 can also be reduced, the hot carrier resistance can be improved.

As a modified example of the oxynitride film of the gate insulating film 3, for example, a structure in which a silicon nitride film is laminated on a thin silicon oxide film may be adopted. Also in this case, the hot carrier resistance can be improved.

Further, instead of the oxynitride film, the gate insulating film 3 may be formed of another dielectric film such as a silicon nitride film (SiN), a high dielectric film or a ferroelectric film. In this case as well, the hot carrier resistance can be improved, but 1 / f on the analog circuit side due to the increase in the interface state.
Since it is considered that noise becomes apparent, it is preferable to apply the structure of the present invention. Examples of the high dielectric substance include a tantalum pentoxide film (Ta ₂ O ₅ ) having a relative dielectric constant of 20 or more, alumina (Al ₂ O ₃ ), hafnium oxide (HfO), zinc oxide (ZnO), and a dielectric constant of 20 or more. BST over 100
((Ba, Sr) TiO ₃ ). Examples of the ferroelectric film include PZT, PLT, PLZT, SBT, and Pb containing a perovskite structure in a ferroelectric phase at room temperature.
There are TiO ₃ , SrTiO ₃ and BaTiO ₃ . These dielectric films are preferably used in combination when the gate electrode 4 is composed of only a metal film. When these dielectric films are used, in addition to the above-described effects, since the dielectric constant is higher than that of the silicon oxide film, the capacitance required by the MIS can be obtained with a thickness larger than that of the silicon oxide film.
The effect is obtained.

A pair of semiconductor regions 2N for the source and the drain of the NMISQN which need to take measures against 1 / f noise of the analog circuit are formed in the P-type well layer PWL.
This semiconductor region 2N contains, for example, phosphorus or arsenic. The N-type channel layer 5N is formed in the channel region between the pair of semiconductor regions 2N (when not operating). The N-type channel layer 5N has the surface channel layer and the buried channel layer. This N-type channel layer 5N contains, for example, phosphorus or arsenic. The impurity concentration of the N-type channel layer 5N is the same as the impurity concentration of the semiconductor substrate 1 (that is, the P-type well layer PWL).
, Or slightly higher, but lower than the impurity concentration of the source and drain semiconductor regions 2N. In the present embodiment, the N-type channel layer 5
The impurity concentration of N is, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / c.
m ³ .

In the analog circuit, a pair of semiconductor regions 2NA for the source and the drain of the NMISQNA which do not particularly require the 1 / f noise countermeasure are provided with a P-type well layer PWL.
Is formed. This semiconductor region 2NA also contains, for example, phosphorus or arsenic. The channel region sandwiched between the pair of semiconductor regions 2NA is P-type (during non-operation). In addition, a pair of semiconductor regions 2PA for the source and the drain of the PMISQPA that do not particularly require the 1 / f noise countermeasure are formed in the N-type well layer NWL. The semiconductor region 2PA contains, for example, boron. The channel region sandwiched between the pair of semiconductor regions 2PA is N-type (when not operating).

On the other hand, in a digital circuit, NMISQ
A pair of semiconductor regions 2N for source and drain of ND
D is formed in the P-type well layer PWL. This semiconductor region 2ND also contains, for example, phosphorus or arsenic. The channel region sandwiched between the pair of semiconductor regions 2ND is P-type (when not operating). Also, PMI
A pair of semiconductor regions 2PD for the source and the drain of the SQPD are formed in the N-type well layer NWL. The semiconductor region 2PD contains, for example, boron. The channel region sandwiched between the pair of semiconductor regions 2PD is N-type (when not operating).

Semiconductor regions 2N, 2NA, 2 of NMIS QN, QNA, QND and PMISQPA, QPD
In PA, 2ND, and 2PD, the impurity concentration in the region close to the channel (the region below the sidewall 8) is relatively lower than that in the region away from the channel (the region without the sidewall 8). This makes it possible to suppress generation of hot carriers.

On the main surface of such a semiconductor substrate 1, an interlayer insulating film 9 made of, for example, a silicon oxide film is deposited. In the interlayer insulating film 9, the semiconductor regions 2N, 2N
Contact holes 10 reaching A, 2PA, 2ND, and 2PD are formed. The electrode wiring 11 formed on the interlayer insulating film 9 is electrically connected to the semiconductor regions 2N, 2NA, 2PA, 2ND, 2PD through the contact holes 10. The electrode wiring 11 is made of, for example, aluminum, an aluminum alloy, tungsten, or the like.

Next, an example of a method of manufacturing the above semiconductor integrated circuit device will be described with reference to FIGS. Note that FIG.
3 to 26 are main-portion cross-sectional views of an analog circuit and a digital circuit during a manufacturing process of the semiconductor integrated circuit device.

First, as shown in FIG.
After the formation of the groove-shaped separation portion 7 in the separation region on the main surface side, the P-type well layer PWL and the N-type well layer NWL are formed using different masks. Subsequently, as shown in FIG.
A photoresist pattern 12a is formed on the main surface of the semiconductor substrate 1 by a normal photolithography technique so that a region for forming a buried channel of an analog circuit is exposed and the other region is covered. For example, phosphorus or arsenic is ion-implanted into a region of the semiconductor substrate 1 exposed from the substrate. The dose of the impurity ions at this time is, for example, 1 × 10 ¹² to 1 × 10 ¹³ / cm ^−2.
It is about. The ion implantation energy is
For example, about 40 keV, and for arsenic, for example, about 80 keV. This is an impurity introduction step for forming the N-type channel layer 5 of NMISQN required to reduce 1 / f noise in an analog circuit. Then, after removing the photoresist pattern 12a, each of the NMIS QNA and QND and the PMISQPA and Q other than the NMISQN which performs the 1 / f noise countermeasure of the analog circuit.
Impurities for adjusting the threshold voltage are ion-implanted into the PD. In this case, the dose of the impurity, the implantation energy, and the like are determined according to the threshold voltage of each MIS.

Next, as shown in FIG. 25, after a gate insulating film made of, for example, a silicon oxide film is formed on the main surface of the semiconductor substrate 1 by the same oxidation method as that for forming a normal gate insulating film. For example, N
Heat treatment is performed in an atmosphere such as O (nitrogen oxide) or N ₂ O (nitrous oxide) to form the gate insulating film 3 and the semiconductor substrate 1.
Segregates nitrogen at the interface with (oxynitride film). Thereby, hot carriers can be suppressed, and the reliability of the extremely thin gate insulating film 3 can be improved. The method of forming the oxynitride film is not limited to this, and can be variously changed. For example, after forming a gate insulating film made of a silicon oxide film, nitrogen is implanted by an ion implantation method and heat treatment is performed. Insulating film 3 and semiconductor substrate 1
Nitrogen may be segregated at the interface with.

Next, for example, an N-type polycrystalline silicon film is deposited on the main surface of the semiconductor substrate 1 and then patterned by ordinary photolithography and dry etching to form a gate electrode 4. . Subsequently, an impurity (eg, phosphorus or arsenic) for forming an NMIS and an impurity (eg, boron) for forming a PMIS are separately ion-implanted into the semiconductor substrate 1 using the gate electrode as a mask and the photoresist pattern as a mask. I do. This is a step for forming a semiconductor region having a relatively low impurity concentration on the end side of the gate electrode 4. Thereafter, an insulating film made of, for example, a silicon oxide film is deposited on the main surface of the semiconductor substrate 1 by a CVD method or the like, and is etched back by anisotropic dry etching, as shown in FIG. A sidewall 8 is formed on a side surface of the gate electrode 4.

Then, using the gate electrode 4 and the side wall 8 as a mask and using a photoresist pattern as a mask, an impurity for forming an NMIS (for example, phosphorus or arsenic) and an impurity for forming a PMIS (for example, boron ) Are separately implanted. This is a process for forming the source and drain semiconductor regions of each MIS. Thereafter, a semiconductor integrated circuit device having an analog / digital mixed circuit shown in FIG. 22 is manufactured through a normal wiring forming process.

(Embodiment 2) In this embodiment, a case where the present invention is applied to an operational amplifier (differential amplifier) circuit in an analog circuit of, for example, a mixed analog / digital circuit will be described.

FIG. 27A shows an operational amplifier circuit OPA1 of an analog circuit in a mixed analog / digital circuit. The input stage of the operational amplifier OPA1 has PMISQPA1, QP of the same type as the PMISQPA.
A2 and an NMISQN of the same type as the NMISQN.
1, QN2 and NM of the same type as the NMIS QNA
ISQNA1. The output stage is provided with the P
It has a PMISQPA3 of the same type as the MISQPA and an NMISQNA2 of the same type as the NMISQNA. Two NMIS QNs are differential input transistors. PMISQPA1 and QPA2 constitute a current mirror load (active load).

As described above, in the present embodiment, the NMI is added to the input differential pair of the operational amplifier circuit OPA1 in the input stage.
The use of NMISs QN1 and QN2 having the same type of depletion type buried channel as SQN makes it possible to use 1
/ F noise (here, input noise) can be reduced. In addition, since it is partially used, easiness of circuit design can be ensured. In addition, as in the first embodiment, an oxynitride film is used for the gate insulating film of the MIS constituting this circuit (an analog circuit and a digital circuit). Therefore, particularly, hot carrier resistance in a digital circuit can be improved, and both the improvement of the operation speed and the improvement of the reliability can be ensured as in the first embodiment.

In the buried channel (N-type channel layer 5N) of such NMISs QN1 and QN2, the channel current flows a little deeper than the boundary between the gate insulating film 3 and the semiconductor substrate 1 as described above. Therefore, the possibility that the carriers (electrons) in the channel and the traps in the gate insulating film interact with each other is low, and 1 / f noise can be reduced.
However, this will also be described later with reference to the threshold voltage Vth.
Becomes approximately 0 V or a negative voltage. Therefore, the gate bias voltage (Vbn) becomes a voltage lower than a voltage near the normal (1/2) Vdd. In some cases around 0V,
Or it becomes a negative voltage. The negative voltage can be generated by, for example, a charge pump circuit like a general back gate voltage generation circuit, or can be used for a circuit by receiving a negative power supply voltage from the outside. However, when a negative voltage is used for the circuit, the potential of the semiconductor substrate 1 (p-type well layer PWL)
Must be biased to the lowest voltage used in the circuit. This is because it is necessary to maintain the electrical separation of the potential of the semiconductor region such as the source and drain of the MIS by a reverse bias. Here, Vdd indicates a power supply voltage.

The range of the gate bias voltage will be described in detail. The upper limit of the gate bias voltage Vg is determined by the input differential pair NMISQN of the operational amplifier circuit OPA1.
1, QN2 needs to be biased into the saturation region. The NMISs QN1 and QN2, which are input differential pairs of the operational amplifier circuit OPA1, need to be biased to a saturation region in order to increase mutual conductance (gm). That is, the following relational expression needs to be established between the gate bias Vgs of NMIS QN1 and QN2, the threshold voltage Vth, and the drain-source voltage Vds.

Vds> Vgs−VthD (15) When this condition is rewritten with the absolute value Vd of the drain voltage and the absolute value Vg of the gate voltage, Vd> Vg−VthD (16) On the other hand, PMISQPA1 is applied to the drain voltage Vd (node N1) of NMISQN1 from the circuit of FIG.
There is an upper limit voltage determined by That is, the voltage of the node N1 is as follows.

[0092]

(Equation 9) Therefore, the right side of the expression (17)> (16) needs to be satisfied.

Here, betap is the conductance parameter of PMIS, W is the channel width of the transistor, L is the channel length of the transistor, and I is the current flowing through this transistor.

[0094]

(Equation 10) Therefore,

[0095]

[Equation 11] Is the upper limit of the gate voltage Vg. As specific examples of the voltage, Vdd = 3.0 V, Vthp = 0.5 V, X =
Assuming that 0.3 V and VthD = -1.0 V, 3.0 V-0.5 V-0.3 V + (-1.0 V) = 1.
2V> Vg, and the upper limit of the voltage is lower than the normal bias (1/2) Vdd = 1.5V.

The lower limit of the gate bias voltage Vg is determined by the condition that the NMIS QNA1 for the constant current source below the NMISs QN1 and QN2 of the input differential pair is biased in the saturation region. VdsNMISQNA1> Vgs-Vth = Vbn-Vth (20) On the other hand, the gate bias Vg of NMISQN1 and QN2 is
It is as follows.

[0097]

(Equation 12) This equation (21) determines the lower limit of Vg. Here, Z in the above equation is the effective gate bias voltage of the input differential pair. As a specific example of the voltage, VthD = −1.0 V, X = 0.
Assuming that 3V, (Vbn-Vth) = 0.3V, Vg> -1.0V + 0.3V + 0.3V = -0.4V, which is a negative gate bias voltage.

From the above, as a specific example of the voltage, the threshold voltage VthD of the buried channel type MIS = −1.0
In the case of V, if the power supply voltage is 3.0 V, -0.4 V
It is necessary to apply a gate bias in a voltage range of <Vg <1.2 V. An appropriate bias voltage is a threshold voltage VthD
And needs to be determined by equations (19) and (21). For example, when VthD = −2.2 V, which is considerably negative, Equation (19) = 0 V and Equation (21) = − 1.6 V
(−1.6 V <Vg <0 V), and it is necessary to apply a negative input gate bias voltage. If Vg is in the positive bias voltage range, there is no problem with the circuit. However, if it is desired to apply a negative bias, create a voltage with a negative voltage generator such as a substrate bias generator or externally supply a negative power supply voltage. Can be solved.

On the other hand, in the above example, the effective gate bias was assumed to be 0.3 V. However, in order to obtain a sufficient drain current with the buried channel transistor, for example, Vth
When D = −1.0 V, the effective gate bias voltage is set to 1.
It is necessary to apply about 2V. Equation (21) at this time
Is Vg> −1.0V + 1.2V + 0.3V = 0.5
V, and the circuit can be designed within the range of the positive gate bias. Therefore, if a device is formed in this way, a circuit can be designed with only a positive gate bias, and there is an advantage that a circuit can be easily formed because a negative voltage generating circuit is not required.

FIG. 27 (b) shows an example of a switched capacitor circuit (capacitive feedback type differential amplifier circuit) to which the operational amplifier circuit OPA1 of FIG. 27 (a) is applied. In the figure, a triangle symbol indicates an operational amplifier circuit OPA1 in which the input differential pair shown in FIG. 27A is a buried channel type NMIS QN1, QN2.

As calculated above, the gate bias voltage Vbn = Vg of the differential input transistor of the operational amplifier needs to be set in the range of the equations (19)-(21). In the switched capacitor circuit, the switches SW1 and SW2 are closed during the clock cycle Φ1, and the NMISQ of the input differential pair is closed.
At the same time as setting the bias voltages of N1 and QN2 to Vbn, the voltage difference between the input voltage Vin1 and the bias voltage Vbn is stored in the capacitor C1. During the next clock cycle φ2, the switches SW1 and SW2 are opened, the switch SW3 is closed, another input voltage Vin2 is applied, and the voltage difference Vi is applied.
n1-Vin2 is amplified at the capacitance ratio C1 / C2 and appears at the output. The amplification gain (gain) is determined by the capacitance ratio C1 / C2. Even if the input bias voltage Vbn of the amplifier is negative, both the input side circuit and the output side circuit can be set to arbitrary voltages due to capacitive coupling. Therefore, there is no problem if this circuit is directly connected to the circuits before and after.

However, when it is necessary to set the input bias voltage of the amplifier to a voltage lower than the ground voltage, P
In order to prevent the N-junction from being forward-biased in any case, the substrate bias Vbb needs to be pulled to a negative voltage and made more negative than the smallest voltage generated in the circuit.

Here, an example is shown in which the circuit of FIG. 27A is used for a switched capacitor circuit. However, as long as the bias condition does not cause a problem (it does not become negative), the circuit may be used as a normal continuous-system amplifier. it can. Also in this case, the 1 / f noise in the amplifier can be reduced.

(Embodiment 3) In this embodiment, a case where the present invention is applied to another amplifier circuit in an analog circuit of, for example, an analog / digital mixed circuit will be described.

FIG. 28A shows a fully differential amplifier circuit OP.
A2 is shown. This circuit is a fully differential type circuit and has differential input and differential output. The input differential pair in which 1 / f noise is a problem has the NM
ISQN1 and QN2 are used. Therefore, as in the first and second embodiments, the 1 / f noise in the analog circuit can be reduced. Other NMIS QNA1 to QNA5
And PMISQPA1-QPA6 are respectively NMISQNA and PMISQ described in the first embodiment.
It has the same structure as PA. In addition, as in the first embodiment, an oxynitride film is used for the gate insulating film of the MIS constituting this circuit (an analog circuit and a digital circuit). Therefore, similarly to the first and second embodiments, it is possible to secure both the operation speed and the reliability particularly in the digital circuit.

The rest is the same as an amplifier circuit called a normal current mirror cascode amplifier. That is, the output stage comprises NMIS QNA2, QNA3 and PMISQP
The current mirror cascode amplifier is composed of A3 and QPA4.

FIG. 28B shows a switched capacitor amplifier circuit using the fully differential amplifier circuit OPA2 of FIG. As in the case of FIG. 27B described in the second embodiment, an appropriate input bias voltage Vbn is reset and used during the clock cycle Φ1. Both inputs are biased to Vbn for a fully differential circuit. The output is reset to the common mode voltage Vcm. Similarly to the circuit of FIG. 27B, even if the input bias voltage Vbn of the amplifier is negative, both the input side circuit and the output side circuit can be set to arbitrary voltages due to capacitive coupling. Therefore, there is no problem if this circuit is directly connected to the circuits before and after. Note that C3 to C6 indicate capacitance.

(Embodiment 4) In the present embodiment, a case where the present invention is applied to still another amplifier circuit in an analog circuit of, for example, an analog / digital mixed circuit will be described.

FIG. 29A shows a fully differential amplifier circuit OPA3 similar to that of the third embodiment. This is a so-called folded cascode type (inverted cascode type) amplifier, which can lower the power supply voltage Vdd and increase the voltage utilization rate. Since the NMIS QN1 and QN2 are used for the input differential pair in which 1 / f noise is a problem as in the second and third embodiments, the same effects as in the first to third embodiments can be obtained. . Other NMIS QNA1 to QNA5 and PMISQPA2
To QPA6 are the same as in the third embodiment. Also,
Here, too, the MIS that constitutes the analog / digital mixed circuit
Since the oxynitride film is used as the gate insulating film, the same effects as those of the first to third embodiments can be obtained.

Here, the PMISQPA3 functions as a constant current source. Also, NMISQN2 and PMISQPA
Reference numeral 4 denotes a pair of transistors connected in inverted cascode, PMISQPA4 is a gate-grounded transistor, and NMISQN2 functions as a source-grounded transistor. PMISQPA4 and NMISQNA3 are 2
It operates as a constant current source.

FIG. 29B shows a switched capacitor amplifier circuit using this fully differential amplifier circuit OPA3. This switched capacitor amplifier circuit is substantially the same as that of the third embodiment shown in FIG.

(Embodiment 5) In this embodiment, a case where the present invention is applied to another amplifier circuit in an analog circuit of, for example, an analog / digital mixed circuit will be described.

FIG. 30A shows a fully differential amplifier circuit OPA4 similar to the third and fourth embodiments. this is,
This is a so-called telescopic amplifier. Since the NMIS QN1 and QN2 are used for the input differential pair in which 1 / f noise is a problem as in the second to fourth embodiments,
The same effects as in the first to fourth embodiments can be obtained. Other NMIS QNA1, QNA6 to QNA9 and PM
Each of ISQPA7 to QPA10 has the same structure as NMISQNA and PMISQPA described in the first embodiment. Also here, since the oxynitride film is used as the gate insulating film of the MIS constituting the mixed analog / digital circuit, the same effects as in the first to fourth embodiments can be obtained. In this circuit, a pair of PMISQPA
8, QPA10 and a pair of NMIS QNA7, QNA
9 is cascode-connected. Although the power supply voltage increases, the output impedance increases due to the multistage connection. Since the power supply voltage suppression ratio is improved, power supply noise can be prevented.

FIG. 30B shows a switched capacitor amplifier circuit using the fully differential amplifier circuit OPA4. This switched capacitor amplifier circuit is substantially the same as that of the third embodiment shown in FIG.

(Embodiment 6) This embodiment is a modification of the second embodiment. In the present embodiment, as shown in FIG.
NMISs QN1 and QN2 forming an input differential pair of PA5
Has a depletion-type embedded channel structure,
The NMIS QN3 of the second amplification stage and the NMIS QN4 for the constant current source of the input differential pair have the same depression type buried channel structure as the NMIS QN described in the first embodiment. One of the NMISs QN3 and QN4 may be a depression type buried channel. The rest is the same as the second embodiment.

The noise of the second amplification stage becomes the input conversion noise by an amount divided by the gain of the first amplification stage. Therefore, if the gain of the first stage is sufficiently high, there is little need to take measures against the noise of the second stage. However, if the gain of the first stage is not sufficiently high, the effect will occur.
SQN3 also has a depression type buried channel structure.

An NMIS for a constant current source of an input differential pair
Since the noise from QN4 is diode-connected to PMISQPA1, the gain appearing at the output is small and the effect is not so large. Therefore, although omitted in the second embodiment, when it is necessary to further reduce the influence of noise, it is effective to form the NMISQN4 into a depletion type buried channel.

When the threshold voltage VthD of these NMISs QN3 and QN4 is a negative voltage, a negative gate bias voltage needs to be generated in some cases. However, since a voltage is applied to the gate and no current capacity is required, a negative gate bias voltage is required. There are no difficult problems in designing the generator.

(Embodiment 7) The present embodiment describes a modification of the third embodiment. In the present embodiment, as shown in FIG. 32, NMISs QN1 and Q
In addition to N2 having a depletion type buried channel structure, other NMISs QN5 to QN9 also have a depletion type buried channel structure. The rest is the same as the third embodiment.

Output noise appears as input conversion noise in the ratio of the mutual conductance (gmi) of the input differential pair to the mutual conductance (gmn) of the NMISs QN6 and QN9 for the constant current source of the fully differential amplifier OPA6. Usually, since the transconductance (gmi) is larger, this NMIS
The QN6 and QN9 may not have a depletion type buried channel structure. However, in order to further reduce noise, it is desirable that the NMIS QN6 and QN9 for the constant current source also have a depletion type buried channel structure.

Although the NMIS QN7 may not be a depletion-type buried channel (ie, an enhancement-type surface channel structure), the NMIS QN5 to QN9 other than the input differential pair may have a depletion-type buried channel structure. In analog circuits, lower noise can be achieved.
The noise characteristics of the digital mixed circuit can be improved.

(Eighth Embodiment) The present embodiment describes a modification of the fourth embodiment. In the present embodiment, as shown in FIG. 33, NMISs QN1 and Q
In addition to N2 having a depletion type buried channel structure, NMIS QN6 and QN9 for a constant current source and other NMIS QN5, QN7 and QN8 also have a depletion type buried channel structure. Other NMISQN
5, QN7, QN8 may not have a depletion type buried channel structure, that is, an enhancement type surface channel structure. Except for this, it is the same as the fourth embodiment.

In this type of fully differential amplifier circuit OPA7, as described in the seventh embodiment, the NMISs QN6 and QN9 for the constant current source have a depression type buried channel structure to further reduce noise. Can be achieved. Also, NMIS QN5, QN7,
The QN8 also has a depletion-type buried channel structure, so that the noise in the analog circuit can be further reduced, and the noise characteristic of the analog / digital mixed circuit can be improved.

(Embodiment 9) This embodiment describes a modification of the embodiment 5. In the present embodiment, as shown in FIG. 34, NMISs QN1 and Q
N2 has a depletion type buried channel structure, NMISQN10 for a constant current source and other NM
ISQN11 to QN14 also have a depression type buried channel structure. Other NMIS QN11-QN
The structure may be such that 14 is not a depression type buried channel, that is, an enhancement type surface channel structure. Except for this, it is the same as the fifth embodiment.

In this type of fully differential amplifier circuit OPA8, as described in the seventh embodiment, the NMIS QN10 for the constant current source has a depletion type buried channel structure to further reduce noise. be able to. In addition, since the NMISs QN11 to QN14 also have a depletion type buried channel structure, it is possible to further reduce noise in an analog circuit and to improve noise characteristics of an analog / digital mixed circuit.

(Embodiment 10) FIG. 35 illustrates a main part of an analog / digital mixed circuit according to another embodiment of the present invention. Here, the signal input to the input terminal IN of the analog / digital mixed circuit is a relatively small signal such as a CCD (Charge Coupled Device) image sensor output signal (detection signal) of a video camera. An example is given in which the noise in the first stage becomes a problem.

The input terminal IN is connected to the amplifier circuits AMP1 to AMP
Via MP3, it is electrically connected to the A / D converter AD and further to the digital signal processing circuit DSC. The amplifier circuit AMP1 is a zero-level sample amplifier circuit. The amplifier circuit AMP2 is a first-stage variable gain amplifier circuit. Note that C7 to C9 indicate capacitors, and SW3 and SW4 indicate switches.

The minute input signal transmitted to the input terminal IN is weak and needs to be amplified by the amplifier circuits AMP1 to AMP3. At this time, the amplifier circuits AMP1, AMP2
If 1 / f noise is present at the first stage, it will be amplified and interfere with the image. Therefore, the amplifier circuits AMP1, AM
In the first stage of P2, it is necessary to reduce the noise with a device having a small 1 / f noise. Therefore, in the present embodiment, as described in the first to ninth embodiments, an NMIS having a depression type buried channel is used as the first transistor of the amplifier circuits AMP1 and AMP2. As a result, a low-noise amplifier can be realized, and an analog / digital mixed circuit that does not disturb the image can be realized.

The signals amplified by the amplifier circuits AMP1 to AMP3 are transmitted to the input of the A / D converter AD. The A / D converter AD converts an analog signal transmitted from the amplifier circuit AMP3 into a digital signal and transmits the digital signal to the digital signal processing circuit DSC. In the digital signal processing circuit DSC, for example, 8
Digital signal of bit (for example, 256 gradations)
Various signal processings are performed, such as taking out the output of.

In the present embodiment, an example of an image signal has been described. However, the present invention is not limited to this, and various applications are possible. That is, the technical idea of the present invention is effective when applied to all kinds of analog / digital mixed circuits that first amplify a small signal from a sensor and then perform signal processing.

(Embodiment 11) In this embodiment, for example, an oscillating circuit in an analog circuit of an analog / digital mixed circuit (for example, an oscillating circuit for forming an RF oscillating frequency or a phase locked loop (PLL) serving as a reference for clock generation) ) The case where the present invention is applied to the circuit) will be described.

FIG. 36 shows an example of the oscillation circuit VCO. The oscillation circuit VCO is, for example, a differential LC oscillation circuit. In order to improve the voltage utilization rate, an AC load is formed by the coils L1 and L2. The oscillation frequency is the capacitance C1
0, C11 and the resistor R1 (or the capacitors C12, C13
And the resistance R2).

An oscillation circuit VCO for an RF signal requires an oscillation circuit with small phase noise, and a low-noise oscillation circuit is very important. Therefore, in the present embodiment,
The NMIS QN15 and QN16 of the differential pair for generating a negative resistance of the negative resistance differential type oscillation circuit VCO have a depression type buried channel structure similar to the NMIS QN of the first embodiment. This makes it possible to reduce the input noise of the oscillation circuit VCO.

The NMIS QN 17 for the constant current source also has a depression type buried channel structure. That N
The MISQN 17 may have a structure that is not a depression type buried channel, that is, a structure of an enhancement type surface channel. NMISQN for constant current source
By using a depletion-type embedded channel structure for 17, noise can be further reduced, and the noise characteristics of the analog / digital mixed circuit can be improved.

The NMISs QN15 to QN17 having a depletion type buried channel used here are:
The threshold voltage Vth has a value close to zero (0) or a negative value. Therefore, the input bias voltage Vbn1 needs to be given a sufficiently low voltage, and in some cases, a negative potential. In this oscillation circuit VCO, the DC bias can be separated from other circuit components by using the capacitive coupling, so that it is possible to apply a low bias voltage or a negative voltage as necessary as a gate bias.

By incorporating such an oscillator circuit VCO into a mobile communication device, phase noise can be reduced, and sufficient separation from adjacent channels required for mobile communication can be achieved.

As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say,

For example, in the above embodiment, the MIS having the depression type
Although the case of S has been described, the present invention is not limited to this, and various changes can be made. For example, even if PMIS is used as a depletion type buried channel at a predetermined location described in the above-described embodiment of the analog circuit. good. In this case, the gate electrode of the PMIS is a P-type. Then, a P-type channel layer is formed in the channel region. In the case where polycrystalline silicon is used as a gate electrode material, boron is introduced into the gate electrode to make it a P-type. When a metal is used as the gate electrode material, for example, ruthenium oxide (RuO ₂ ), iridium (ir), platinum (Pt), tungsten nitride (W
N) or molybdenum nitride (Mo ₂ N).

In the above description, the case where the invention made by the present inventor is applied to a semiconductor integrated circuit device, which is the field of application, has been described. However, the present invention is not limited to the above-described semiconductor integrated circuit device. For example, DRAM (Dynamic Random Access Memory), SR
AM (Static Random Access Memory) or flash memory (EEPROM; Electric Erasable Programm)
The present invention is also applicable to other semiconductor integrated circuit devices in which a memory circuit such as an Able Read Only Memory) and an analog / digital mixed circuit are provided on the same semiconductor substrate.

[0140]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows. (1) According to the present invention, the gate insulating film of the insulated gate field effect transistor forming the analog circuit of the analog / digital mixed circuit is formed of an oxynitride film, and at least one of the first circuits forming the analog circuit is formed. When the transistor has a structure having a depression-type buried channel, the noise characteristics of a semiconductor integrated circuit device having an analog / digital mixed circuit can be improved. (2) According to the above (1), the operation reliability of a semiconductor integrated circuit device having an analog / digital mixed circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a principal part of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 shows an N-channel type M according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a main part showing a structure of a buried channel of an IS • FET.

FIG. 3A is an enlarged sectional view of a region A in FIG. 2,
(B) is an explanatory view showing the impurity concentration distribution of (a).

FIG. 4A is an N-channel MIS-FET of FIG. 3;
FIG. 3B is an explanatory diagram showing an operation state of the buried channel structure of FIG.

5A is an N-channel type MIS • FET of FIG. 3;
4 shows an operation state different from that in FIG. 4 of the buried channel structure shown in FIG.

6A is an N-channel type MIS • FET of FIG. 3;
4 shows an operation state of the buried channel structure of FIG. 4 similar to that of FIG. 4, and FIG.

7A is an N-channel type MIS • FET of FIG. 3;
7 shows an operation state of the buried channel structure shown in FIG. 4 different from those shown in FIGS. 4 to 6, and FIG.

8 (a) is an N-channel MIS • FET of FIG. 3;
7 shows an operation state of the buried channel structure shown in FIG. 4 different from those in FIGS. 4 to 7, and FIG.

FIG. 9 is an explanatory diagram of an energy band showing a physical phenomenon that gives a limiting condition to a parameter characterizing a buried channel structure of an N-channel type MIS • FET.

FIG. 10 is an explanatory diagram of an energy band showing a physical phenomenon that gives a limiting condition to a parameter characterizing a buried channel structure of an N-channel type MIS • FET.

FIG. 11 is an explanatory diagram of an energy band showing a physical phenomenon that gives a limiting condition to a parameter characterizing a buried channel structure of an N-channel type MIS • FET.

FIG. 12 is an explanatory diagram of an energy band showing a physical phenomenon that gives a limiting condition to a parameter characterizing a buried channel structure of an N-channel type MIS • FET.

FIG. 13 is a schematic explanatory view for giving a restriction condition on a structural parameter defined by a resistance condition of the N-type channel layer in FIG. 2;

FIG. 14 is an enlarged perspective view of an essential part schematically showing an N-type channel layer extracted from FIG. 13;

FIG. 15 is a graph showing conditions to be satisfied by an N-type channel layer width represented by Expression (7).

FIG. 16 is a graph showing the result of verifying the validity of equation (7) by device simulation.

FIG. 17 is a graph illustrating a range of a gate voltage that realizes a state where 1 / f noise is suppressed.

FIG. 18 is a graph showing a relationship between gate voltage and current of a MIS having an enhancement type surface channel.

FIG. 19 is an explanatory diagram illustrating Expression (14) obtained by approximation.

FIG. 20 is a graph showing an electron concentration obtained by device simulation.

FIG. 21 is a plan view of a semiconductor chip having a mixed analog / digital circuit.

FIG. 22 is a sectional view of a main part of FIG. 21;

23 is a fragmentary cross-sectional view of an analog circuit and a digital circuit during a manufacturing step of the semiconductor integrated circuit device of FIG. 21;

24 is a fragmentary cross-sectional view of the analog circuit and the digital circuit during the manufacturing process of the semiconductor integrated circuit device, following FIG. 23;

25 is a fragmentary cross-sectional view of the analog circuit and the digital circuit during the manufacturing process of the semiconductor integrated circuit device, following FIG. 24;

26 is a fragmentary cross-sectional view of the analog circuit and the digital circuit during the manufacturing process of the semiconductor integrated circuit device, following FIG. 25;

FIG. 27A is a circuit diagram of an analog circuit of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 27B is a circuit diagram of an example in which the analog circuit of FIG.

28A is a circuit diagram of an analog circuit of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 28B is a circuit diagram of an example to which the analog circuit of FIG.

29A is a circuit diagram of an amplifier circuit in an analog circuit of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 29B is a circuit diagram of a switched capacitor amplifier circuit using the circuit of FIG. It is a circuit diagram.

30A is a circuit diagram of an amplifier circuit in an analog circuit of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 30B is a circuit diagram of a switched capacitor amplifier circuit using the circuit of FIG. It is a circuit diagram.

FIG. 31 is a circuit diagram of an amplifier circuit in an analog circuit of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 32 is a circuit diagram of an amplifier circuit in an analog circuit of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 33 is a circuit diagram of an amplifier circuit in an analog circuit of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 34 is a circuit diagram of an amplifier circuit in an analog circuit of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 35 is an explanatory diagram of a configuration of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 36 is an explanatory diagram of an example of an oscillation circuit in an analog circuit of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 37 is a graph showing the relationship between the amount of oxynitridation of a gate insulating film, hot carrier lifetime, and 1 / f noise intensity obtained by an experiment performed by the present inventors.

FIG. 38 is an explanatory diagram schematically showing the cause of 1 / f noise.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 1C semiconductor chip 2 semiconductor region 2N, 2Ns, 2Nd semiconductor region 3 gate insulating film 4 gate electrode 5a surface channel layer 5b buried channel layer 5N N-type channel layer 6 depletion layer 7 separation portion 8 sidewall 9 interlayer insulating film 10 Contact hole 11 electrode wiring 12a photoresist pattern 60 semiconductor substrate 61 gate insulating film 62 gate electrode 63 source 64 drain 65 surface channel layer Ce electron flow Ce1 electron flow Ce2 electron scattering Ce3 electron flow Te electron e1 electron Q MIS FET (first transistor) QN N-channel MIS • FET (first transistor) QN1 to QN16 N-channel MIS • FET (first transistor) QNA N-channel MIS • FET (second transistor) Register) QNA1~QNA5 N-channel type MIS · FET
(Second Transistor) QND N-Channel MIS • FET QPA P-Channel MIS • FET (Second Transistor) QPA1 to QPA10 P-Channel MIS • FET
(Second Transistor) QPD P-channel type MIS • FET PWL P-type well layer NWL N-type well layer Xjd N-type channel layer width DA Digital circuit area AA Analog circuit area SCA area GmA Non-mutual conductance (gm) deterioration area INV Inverter circuit OPA1 Operational amplifier circuit OPA2 to OPA8 Fully differential amplifier circuit SW1 to SW4 Switch C1 to C9 Capacity AMP1 to AMP3 Amplifier circuit AD A / D converter DSC Digital signal processing circuit VCO Oscillator circuit L1, L2 Coil Q60 MIS • FET

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 301K 301G (72) Inventor Masao Hotta 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Within the Hitachi, Ltd.Semiconductor Group (72) Inventor Shiro Kambara 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Within the Hitachi, Ltd.Semiconductor Group (72) Nobue Nakajima, Nobue Nakajima Kamimizuhoncho, Kodaira-shi, Tokyo 5-20-1 F-Term within Hitachi, Ltd. Semiconductor Group F-term (reference) EK01 EK05 EL02 FA05 FC15 5F048 AA07 AB01 AB10 AC02 AC03 BB04 BB06 BB07 BB08 BB09 BB11 BB12 BB13 BB15 BD05 BE03 BG12 BG14 DA twenty five

Claims (23)

[Claims] 1. A semiconductor device comprising: a semiconductor substrate; an analog circuit and a digital circuit formed on a main surface of the semiconductor substrate; and each of the analog circuit and the digital circuit includes a main circuit of the semiconductor substrate. A gate electrode formed on a surface of the element forming region via a gate insulating film, and a gate electrode formed in the element forming region at opposite ends of the gate electrode and separated from the element forming region by a PN junction A plurality of insulated gate field effect transistors having a source region and a drain region, and a channel forming region for forming a channel between the source region and the drain region in the element forming region; The gate insulating film of each of the plurality of insulated gate field effect transistors forming a circuit is formed of an oxynitride film, At least one of the plurality of insulated gate field effect transistors constituting the analog circuit;
A semiconductor integrated circuit device, wherein one of the first transistors has a depression type buried channel layer formed in the channel formation region between the source region and the drain region. 2. The semiconductor integrated circuit device according to claim 1, wherein said gate insulating film of each of said plurality of insulated gate field-effect transistors forming said digital circuit comprises:
A semiconductor integrated circuit device comprising an oxynitride film. 3. The semiconductor integrated circuit device according to claim 2, wherein, out of the plurality of insulated gate field effect transistors constituting the analog circuit, those other than the first transistor are enhancement-type transistors. 1
And a second transistor having a surface channel of the same conductivity type as that of the first transistor. 4. The semiconductor integrated circuit device according to claim 2, wherein each of said plurality of insulated gate field effect transistors forming said digital circuit has an enhancement type surface channel in said channel forming region. A semiconductor integrated circuit device comprising: 5. The semiconductor integrated circuit device according to claim 2, wherein a width of the buried channel of the first transistor in a depth direction is larger than 0.7 times a width of a depletion layer formed by a PN junction of the source region. A semiconductor integrated circuit device having a size smaller than 1.7 times. 6. The semiconductor integrated circuit device according to claim 2, wherein the gate electrodes of said first and second transistors of said plurality of insulated gate field effect transistors forming said analog circuit are N-type polycrystalline. The element region of the first transistor is P-type; the source region and the drain region of the first transistor form a PN junction with the element formation region; A semiconductor integrated circuit device, wherein an N-type buried channel layer is formed in the channel formation region in the formation region. 7. The semiconductor integrated circuit device according to claim 6, wherein said plurality of insulated gate field effect transistors forming said digital circuit have said gate electrode made of an N-type polycrystalline silicon film, and said element formation region. Is a P-type, and the channel formation region in the P-type element formation region has an enhancement-type N-type surface channel. 8. The semiconductor integrated circuit device according to claim 6, wherein a width of the buried channel layer of the first transistor in a depth direction is larger than 0.7 times a width of a depletion layer formed by a PN junction of the source region. A semiconductor integrated circuit device having a size smaller than 1.7 times. 9. The semiconductor integrated circuit device according to claim 1, wherein said first transistor of said analog circuit is one of a plurality of insulated gate field effect transistors forming an amplifier circuit. A semiconductor integrated circuit device comprising an input amplification stage. 10. The semiconductor integrated circuit device according to claim 1, wherein said first transistor of said analog circuit is one of a plurality of insulated gate field effect transistors forming an oscillation circuit. A semiconductor integrated circuit device comprising an amplification stage. 11. A semiconductor substrate, comprising: an analog circuit and a digital circuit formed on a main surface of the semiconductor substrate, wherein each of the analog circuit and the digital circuit includes a main circuit of the semiconductor substrate. A gate electrode formed on a surface of the element forming region via a gate insulating film, and a gate electrode formed in the element forming region at opposite ends of the gate electrode and separated from the element forming region by a PN junction A plurality of insulated gate field effect transistors having a source region and a drain region, and a channel forming region for forming a channel between the source region and the drain region in the element forming region; A gate insulating film of each of the plurality of insulated gate field effect transistors constituting the circuit and the digital circuit, The analog circuit includes a differential amplifier circuit configured from the insulated gate field effect transistor, a pair of differential input insulated gate field effect transistors configuring the differential amplifier circuit,
A semiconductor integrated circuit device having a depression type buried channel layer formed in the channel formation region between the source region and the drain region. 12. The semiconductor integrated circuit device according to claim 11, further comprising an insulated gate field effect transistor other than said pair of differential input insulated gate field effect transistors and said digital circuit constituting said differential amplifier circuit. A semiconductor integrated circuit device comprising a plurality of insulated gate field effect transistors having an enhancement type surface channel. 13. The semiconductor integrated circuit device according to claim 11, wherein said differential amplifier circuit includes said pair of differential input insulated gate field effect transistors in addition to said pair of differential input insulated gate field effect transistors. And a pair of insulated gate field effect transistors forming a current mirror load coupled to the semiconductor integrated circuit device. 14. The semiconductor integrated circuit device according to claim 13, wherein said plurality of insulated gate field effect transistors forming said analog circuit and said digital circuit include N-type and P-type channels. A semiconductor integrated circuit device comprising: 15. The semiconductor integrated circuit device according to claim 14, wherein said gate electrode of said complementary insulated gate field effect transistor is an N-type polycrystalline silicon film. 16. A semiconductor device comprising: a semiconductor substrate; an analog circuit and a digital circuit formed on a main surface of the semiconductor substrate; and each of the analog circuit and the digital circuit is a main circuit of the semiconductor substrate. A gate electrode formed on a surface of the element forming region via a gate insulating film, and a gate electrode formed in the element forming region at opposite ends of the gate electrode and separated from the element forming region by a PN junction A plurality of insulated gate field effect transistors having a source region and a drain region, and a channel forming region for forming a channel between the source region and the drain region in the element forming region; A gate insulating film of each of the plurality of insulated gate field effect transistors constituting the circuit and the digital circuit, The analog circuit includes an oscillation circuit including the insulated gate field effect transistor, and the amplifying insulated gate field effect transistor included in the oscillation circuit is configured between the source region and the drain region. A semiconductor integrated circuit device having a depression type buried channel layer formed in the channel formation region. 17. The semiconductor integrated circuit device according to claim 16, wherein the oscillation circuit comprises a differential LC oscillation circuit including a pair of inductive loads, a pair of amplifying transistors, and a pair of CR time constant circuits. Wherein the pair of amplifying transistors has a depression type buried channel layer formed in the channel formation region between the source region and the drain region. 18. The semiconductor integrated circuit device according to claim 17, wherein said pair of amplifying transistors are N-type channels. 19. A semiconductor device comprising: a semiconductor substrate; and an analog circuit and a digital circuit formed on a main surface of the semiconductor substrate, wherein each of the analog circuit and the digital circuit includes a main circuit of the semiconductor substrate. A gate electrode formed on a surface of the element forming region via a gate insulating film, and a gate electrode formed in the element forming region at opposite ends of the gate electrode and separated from the element forming region by a PN junction A plurality of insulated gate field effect transistors having a source region and a drain region, and a channel forming region for forming a channel between the source region and the drain region in the element forming region; The gate insulating film of each of the plurality of insulated gate field effect transistors constituting the circuit and the digital circuit is formed by a hot At least one first transistor of the plurality of insulated gate field effect transistors, which is constituted by a dielectric film for suppressing carrier trapping and constitutes the analog circuit, is formed by the source region and the drain region. A semiconductor integrated circuit device having a depletion type buried channel layer formed in the channel formation region therebetween. 20. The semiconductor integrated circuit device according to claim 19, out of the plurality of insulated gate field-effect transistors constituting the analog circuit, those other than the first transistor are enhancement-type, and A semiconductor integrated circuit device including a second transistor having a surface channel of the same conductivity type as one transistor. 21. The semiconductor integrated circuit device according to claim 19, wherein said dielectric film has a silicon nitride film. 22. The semiconductor integrated circuit device according to claim 19, wherein said dielectric film has a tantalum oxide film. 23. A semiconductor device comprising: a semiconductor substrate; and an analog circuit and a digital circuit formed on a main surface of the semiconductor substrate. Each of the analog circuit and the digital circuit includes a main circuit of the semiconductor substrate. A gate electrode formed on a surface of the element forming region via a gate insulating film, and a gate electrode formed in the element forming region at opposite ends of the gate electrode and separated from the element forming region by a PN junction A plurality of insulated gate field effect transistors having a source region and a drain region, and a channel forming region for forming a channel between the source region and the drain region in the element forming region; Forming P-type and N-type element forming regions in the analog circuit forming region and the digital circuit forming region on the main surface of the substrate, respectively. Excluding the selected P-type element formation region of the analog circuit and introducing the impurity for forming the N-type region by masking the other element formation region, Forming an N-type layer for a buried channel in the P-type and N-type layers.
Forming an oxynitride insulating film for an insulated gate in each of the device forming regions of the type, and forming an N-type for the gate electrode on each of the oxynitriding insulating films for the insulated gate in the P-type and N-type device forming regions. Forming a polycrystalline silicon film, and using the N-type polycrystalline silicon film for the gate electrode as a mask, forming an impurity for forming an N-type region in the P-type element forming region and a P-type impurity in the N-type element forming region. Forming N-type and P-type source and drain regions in the P-type and N-type element forming regions, respectively, by introducing impurities for forming the regions, respectively.
A method of manufacturing a semiconductor integrated circuit device, comprising: forming an insulated gate field effect transistor having a depletion type N-type buried channel layer in a type element formation region.