JP2000156494A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor device which can be stabilized in element characteristics surely fixing a substrate at a certain potential. SOLUTION: A P-type well layer 2 is formed on a P-type silicon substrate 1, and a gate finger-type N-channel transistor 3 is formed on the P-type well layer 2. A substrate potential fixing P+ layer 10 is formed inside the silicon substrate extending from an active region to the end of a field oxide film 9. A contact hole 12 is bored in the source region 7 of a transistor 3 so as to reach the inside of the substrate potential fixing P+ layer 10 penetrating through the source region 7, so that both the source region 7 and the P+ layer 10 are fixed at a certain potential by the contact hole 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a gate finger type MO.
The present invention relates to a structure for fixing a substrate potential in an S transistor and a method for forming the same.

[0002]

2. Description of the Related Art For example, in a high-frequency MOS LSI used in the field of wireless communication or the like, a field-effect transistor (Field-Ef) of a type in which a gate is branched into a plurality of electrode fingers.
fect transistor (hereinafter abbreviated as FET), which is a so-called gate finger type FET. This kind of gate finger type FET is a high frequency MOS LSI
And is often used for analog circuits such as amplifiers, and high output is required.

The threshold voltage Vt, which is the most basic characteristic of a MOSFET, is generally expressed by the following (1)
It is expressed by an equation.

(Equation 1) Here, V _t : threshold voltage, V _SB : source-substrate voltage, V _t0 : threshold voltage when V _SB = 0, Φ _f : Fermi level, N _A : substrate impurity concentration, C _ox : Gate oxide film capacity, q: electron charge amount, ε: dielectric constant of semiconductor. (1) Example of a graph of a relationship of a (2Φ _f + V _SB) ^1/2 and V _t in the formula is 23. Since [Phi _f is a constant determined by the material, it will be V _t varies depending on the value of V _SB, higher the value of V _SB increases, a tendency that V _t increases.

In addition, between the drain and source of a MOSFET
Voltage V_dsAnd drain current I_dFigure showing the relationship with
24. Multiple Vs in FIG._ds-I_dCharacteristic curve T₁~
T₆Is the gate potential (V_g-V_t) Are different,
The higher the heat potential, the higher the V_ds-I_dThe characteristic curve is located on the upper side
You. For example, if a MOSFET is used for the amplifier,
Area V_ds-I_dCharacteristic curve T_FourPoint of intersection of load curve F
At point Q, MOSFET operates at operating point Q
Gate applied voltage V_gIs adjusted to a predetermined value. Toko
The gate applied voltage V_gIs constant,
Port potential is V_g-V _tTherefore, V_tOperates when fluctuates
The point Q will also fluctuate.

[0005] Generally the MOSFET as used in the amplifier to the gate width is as large as 100-400, to obtain a drain current I _d of a few mA required for the operation, usually, the applied gate voltage V _g to around 1V We use lower. Thus, the influence of variation in V _t becomes larger, distortion of the output waveform due to variations in operating point due to variations in V _t, such as reduction of the gain, defects or characteristics occur. That, V _t varies due to fluctuations in V _SB, since the operating point is to vary sufficiently suppress the variation of V _SB in MOSFET, or secured to how constant V _SB is important.

[0006]

SUMMARY OF THE INVENTION Gate finger type F
19 and 20 show examples of a structure for fixing the source-substrate voltage ( _VSB ) in ET. In the structure shown in FIG. 19, a plurality of gate fingers 51 are formed on the N ⁺ type source / drain diffusion layer 50,
An N-channel MOSFET 52 is configured. The N ⁺ type source / drain diffusion layer 50 is formed on the P well layer, and a well contact 53 for fixing the potential (substrate potential) of the P well layer is formed on the N ⁺ type source / drain diffusion layer 5.
0 are formed at two places on both sides. In the structure shown in FIG. 20, the well contact 54 has an N ⁺ type source
The drain diffusion layer 50 is formed to surround the periphery.

However, in the conventional substrate potential fixing structure shown in FIGS. 19 and 20, a well contact is formed in the peripheral portion of the source / drain diffusion layer anyway, so that the number of gate fingers increases. As the width of the entire gate increases, the distance between the gate finger and the well contact near the center increases, and it becomes more difficult to fix the substrate potential to the minimum potential due to the substrate resistance between them. Thus, although not an example of a gate finger type FET, examples in which the substrate potential is fixed at a position close to the gate are described in JP-A-2-15665 and JP-A-63-250177.

FIG. 21 shows a substrate potential fixing structure described in JP-A-2-15665. In this structure, the well contact 55 penetrates through the N ⁺ source region 57 of the MOSFET 56 to reach the P well region 58, and is electrically connected to these two regions 57, 58. This is a common contact for the wells. The common contact is connected to a wiring 60 formed on interlayer insulating film 59, and N ⁺ source region 57 and P well region 58 are connected via wiring 60.
Are fixed at the lowest potential.

FIG. 22 shows a substrate potential fixing structure described in JP-A-63-250177. In this structure, P ⁺ diffusion region 63 of the well contact adjacent to the N ⁺ source region 62 of the MOSFET61 are formed, these N ⁺ source region 62, P ⁺ source potential fixing contact 64 to the diffusion region 63, the substrate Potential fixing contact 65
Are formed respectively. These two contacts 64 and 65 are commonly connected to a wiring 67 formed on the interlayer insulating film 66, and both the N ⁺ source region 62 and the P well region 68 are fixed at the lowest potential via the wiring 67. It is supposed to be.

However, each of these two structures has its own problems. Usually, the contact structure on the source side and the drain side of the MOSFET is symmetrical, so that the contact hole on the source side and the drain side can be formed by one photolithography process. However, FIG.
In the case of the structure shown in FIG.
Due to the asymmetry that the ⁺ source region penetrates to the P well region and the drain side contact hole stops at the N ⁺ drain region, the source side and drain side contact holes are formed in one photolithography process. And the manufacturing process becomes complicated. On the other hand, if the structure shown in FIG. 22, N ⁺
Since it is necessary to form a P ⁺ diffusion region for a well contact adjacent to the source region, there is a drawback that the occupied area of the MOSFET is increased and the device is not suitable for miniaturization of the device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has been made to complicate the manufacturing process and reduce the MOSF.
An object of the present invention is to provide a semiconductor device capable of stably fixing a substrate potential and stabilizing element characteristics without causing a conventional problem such as an increase in occupation area of ET, and a method of manufacturing the same.

[0012]

In order to achieve the above object, a first semiconductor device according to the present invention is provided on a semiconductor substrate.
A control electrode having a plurality of electrode fingers, a common electrode, and an output electrode, wherein a plurality of transistors having one electrode finger of the control electrode, a common electrode impurity diffusion region, and an output electrode impurity diffusion region are adjacent to each other. The formed active region is provided, and is electrically connected to the semiconductor substrate inside the semiconductor substrate below the common electrode impurity diffusion region of each transistor into which the impurity of the first conductivity type is introduced. Electrically connected to the common electrode impurity diffusion region,
An impurity diffusion region for fixing a substrate potential into which an impurity of a second conductivity type opposite to the first conductivity type is introduced is formed.

According to a first semiconductor device of the present invention, in a transistor having a control electrode having a plurality of electrode fingers, a so-called gate finger type transistor, a semiconductor substrate and a common electrode for a common electrode are provided below an impurity diffusion region for a common electrode of the transistor. In this case, a substrate potential fixing impurity diffusion region electrically connected to the impurity diffusion region is formed. In this structure, by fixing the potential of the substrate potential fixing impurity diffusion region, both the potential of the semiconductor substrate and the potential of the common electrode impurity diffusion region are fixed. In this case, since these potentials are fixed below each single transistor constituting the gate finger type transistor, these potentials are stably fixed at a common potential.

Further, it is preferable that the substrate potential fixing impurity diffusion region extends to an element isolation region outside the active region. The position where the substrate potential fixing impurity diffusion region is formed may be at least below the common electrode impurity diffusion region of each transistor and below the electrode finger of the control electrode,
When extending to the element isolation region outside the active region, the substrate potential can be more stably fixed.

The form of the impurity diffusion region for the common electrode may be formed on the well region into which the impurity of the second conductivity type is introduced, and the impurity diffusion region for fixing the substrate potential may be formed inside the well region. . Specifically, for example, when an N-type semiconductor substrate is used, an N-type impurity diffusion region for a common electrode may be formed in the substrate, or a P-well layer may be formed in the N-type semiconductor substrate. Then, a P-type impurity diffusion region for a common electrode may be formed in the P-well layer.

Further, in the first semiconductor device semiconductor substrate of the present invention, a contact hole is provided which penetrates through the common electrode impurity diffusion region of each of the transistors and reaches the substrate potential fixing impurity diffusion region. By burying the conductive layer, a structure in which the impurity diffusion region for fixing the substrate potential is electrically connected to the impurity diffusion region for each common electrode can be obtained. Then, a common wiring can be provided over the interlayer insulating film covering the plurality of transistors, so that the conductive layer embedded in the contact hole and the common wiring can be electrically connected. In the case of adopting this structure, the surface of the semiconductor substrate and the surface of the control electrode corresponding to the entire region except the contact hole portion in the impurity diffusion region for the common electrode of each transistor and the surface of the control electrode are etched at the time of forming the contact hole. A stop film may be provided. The advantage of providing this etching stop film will be described later. Specifically, when the silicon oxide film is used as the interlayer insulating film, a silicide film can be used as the etching stop film.

A second semiconductor device according to the present invention includes a control electrode having a plurality of electrode fingers, a common electrode, and an output electrode on a semiconductor substrate, wherein one of the control electrodes is connected to a common electrode. An active region is provided in which a plurality of transistors each having an impurity diffusion region and an impurity diffusion region for an output electrode are formed adjacent to each other, and an impurity diffusion region for a common electrode of each transistor into which an impurity of the first conductivity type is introduced. A second conductive layer, which is electrically connected to the semiconductor substrate below and extends below the element isolation insulating film outside the active region, and has a conductivity type opposite to the first conductivity type. The impurity diffusion region for fixing the substrate potential into which the impurity of the type is introduced is formed, and the impurity diffusion region for the common electrode of each transistor penetrates the interlayer insulating film and covers the plurality of transistors. And a second contact hole penetrating through the interlayer insulating film and the isolation insulating film and reaching the substrate potential fixing impurity diffusion region, respectively. A conductive layer is embedded in each of the contact holes, and a common wiring provided on the interlayer insulating film is electrically connected to each of the conductive layers, so that the substrate potential fixing impurity diffusion regions are shared by the respective common layers. It is characterized by being electrically connected to the impurity diffusion region for an electrode.

In the second semiconductor device of the present invention, similarly to the first semiconductor device of the present invention, the potential of the semiconductor substrate and the potential of the impurity diffusion region for the common electrode are stably fixed at the common potential. Can be. Further, while the position of the contact in the first semiconductor device of the present invention is in the impurity diffusion region for the common electrode, in the case of the second semiconductor device of the present invention, the contact is located on the element isolation insulating film outside the active region. Become. Therefore, the provision of the contact structure for fixing the substrate potential does not increase the occupied area.

Also in the second semiconductor device of the present invention, the impurity diffusion region for the common electrode can be formed on the well region, and the impurity diffusion region for fixing the substrate potential can be formed inside the well region. The present invention is advantageous in that an etching stop film for forming a contact hole is provided on the surface of the semiconductor substrate and the surface of the control electrode corresponding to the entire region of the impurity diffusion region for the common electrode and the entire region of the impurity diffusion region for the output electrode of each transistor. This is the same as the first semiconductor device.

A third semiconductor device according to the present invention includes a control electrode having a plurality of electrode fingers, a common electrode, and an output electrode on a semiconductor substrate, wherein one of the control electrodes is connected to a common electrode. An active region is provided in which a plurality of transistors each having an impurity diffusion region and an impurity diffusion region for an output electrode are formed adjacent to each other, and an impurity diffusion region for a common electrode of each transistor into which an impurity of the first conductivity type is introduced. An impurity diffusion region for fixing a substrate potential, which is electrically connected to the semiconductor substrate and into which an impurity of a second conductivity type opposite to the first conductivity type is introduced, is formed in a lower semiconductor substrate, A contact hole is provided from the back surface side of the semiconductor substrate, penetrating through the impurity diffusion region for fixing the substrate potential and reaching the impurity diffusion region for the common electrode. It is characterized in that the conductive layer is embedded in part.

While the first and second semiconductor devices of the present invention fix the potential of the impurity diffusion region for fixing the substrate potential through the wiring on the substrate surface side, the third semiconductor device of the present invention provides In this structure, the potential of the impurity diffusion region for fixing the substrate potential is fixed from the back side of the substrate. Therefore, in the case of the third semiconductor device of the present invention, the wiring provided on the substrate surface side is a wiring only for applying a potential to the impurity diffusion region for the output electrode, and the wiring region can be reduced.

In the first to third semiconductor devices of the present invention, the semiconductor substrate is provided with a semiconductor substrate inside the semiconductor substrate instead of the substrate potential fixing impurity diffusion region in which the second conductivity type impurity is introduced into the semiconductor substrate. A conductive layer for fixing the substrate potential, which is made of a material different from the material, for example, a metal and has the same function as the impurity diffusion region for fixing the substrate potential may be provided. In other words, in a general method, a P-type impurity diffusion region for fixing a substrate potential can be formed by, for example, deeply implanting boron ions into a silicon substrate. A metal layer can be used instead of the substrate potential fixing impurity diffusion region. A structure in which a metal layer is formed at a deep position in a semiconductor substrate can be realized by using a technique of bonding two semiconductor substrates. The use of the metal layer has an advantage that the substrate resistance can be further reduced as compared with the case where the impurity diffusion region for fixing the substrate potential in which an impurity is introduced into the semiconductor is used.

The first method of manufacturing a semiconductor device according to the present invention
Forming a substrate potential fixing impurity diffusion region by introducing a second conductivity type impurity into the semiconductor substrate; and forming a first contact hole reaching the substrate potential fixing impurity diffusion region in the semiconductor substrate. Forming a control electrode, an impurity diffusion region for a common electrode and an impurity diffusion region for an output electrode, into which a control electrode and an impurity of a first conductivity type opposite to the second conductivity type are introduced, on the surface of the semiconductor substrate. Forming a transistor having the common electrode impurity diffusion region of the transistor so as to include the first contact hole forming portion in the region, and embedding a conductive layer in the first contact hole. Electrically connecting the common electrode impurity diffusion region and the substrate potential fixing impurity diffusion region. .

In the first method of manufacturing a semiconductor device according to the present invention, a first contact hole reaching a substrate potential fixing impurity diffusion region in a semiconductor substrate is formed, and a common electrode impurity diffusion region is formed in the first contact hole. After a transistor is formed so as to include one contact hole formation portion, a conductive layer is buried in the first contact hole to electrically connect the common electrode impurity diffusion region and the substrate potential fixing impurity diffusion region. As a result, the potentials of both the common electrode impurity diffusion region and the semiconductor substrate can be fixed.

In the above-described manufacturing method, after the transistor forming step, a step of forming an interlayer insulating film covering the transistor and a step of forming a second contact hole penetrating the interlayer insulating film and continuous with the first contact hole are formed. And a step of electrically connecting the common electrode impurity diffusion region and the substrate potential fixing impurity diffusion region by burying a conductive layer in the contact hole formed by the first and second contact holes. Forming a common wiring on the interlayer insulating film above the conductive layer. Further, after the first contact hole forming step,
Burying a silicon oxide film inside the first contact hole, forming a transistor, forming an interlayer insulating film made of the silicon oxide film, and then forming a second contact hole penetrating the interlayer insulating film; In the method described above, the etching of the interlayer insulating film and the etching of the silicon oxide film embedded in the first contact hole are continuously performed to form a contact hole in which the first and second contact holes are continuous. Good.

When the above method is employed, a silicon oxide film is buried inside the first contact hole to form a transistor, and then the region excluding the first contact hole forming portion in the impurity diffusion region for the common electrode of the transistor and the transistor are formed. After forming an etching stop film for stopping etching in the second contact hole forming step on the surface of the semiconductor substrate and the surface of the control electrode corresponding to the entire region of the impurity diffusion region for the output electrode, forming an interlayer insulating film, It is desirable to perform a contact hole forming step of No. 2. A silicide film can be used as the etching stop film.

The reason for using an etching stop film is that when etching is performed in the second contact hole forming step,
In the first contact hole portion in the common electrode impurity diffusion region, the embedded silicon oxide film is etched following the etching of the interlayer insulating film, and the position of the contact hole bottom is set to the depth of the substrate potential fixing impurity diffusion region. However, on the side of the impurity diffusion region for the output electrode, only the etching of the interlayer insulating film must be performed, and the position of the bottom of the contact hole must be fixed on the surface of the impurity diffusion region for the output electrode. As described above, since it is necessary to perform asymmetric etching on the side of the impurity diffusion region for the common electrode and on the side of the impurity diffusion region for the output electrode, an etching stop film is used. When a silicon oxide film is used as a film material to be etched, if a silicide film is used as an etching stop film, a sufficient etching selectivity can be secured, and the function as an etching stop film can be achieved.

Therefore, when this method is adopted, the formation of the contact hole on the side of the impurity diffusion region for the common electrode and the formation of the contact hole on the side of the impurity diffusion region for the output electrode can be performed in one photolithography step.
The advantage is that the manufacturing process is not complicated.

According to the second method of manufacturing a semiconductor device of the present invention,
Forming a substrate potential fixing impurity diffusion region by introducing an impurity of the second conductivity type into the inside of the semiconductor substrate; and extending over an end of the substrate potential fixing impurity diffusion region on the semiconductor substrate surface. Forming an element isolation insulating film to be formed, and forming a control electrode and a second electrode of a conductivity type opposite to the second conductivity type on an active region of the semiconductor substrate surface excluding a region where the element isolation insulating film is formed. Forming a transistor having a common electrode impurity diffusion region into which an impurity of one conductivity type is introduced and an output electrode impurity diffusion region;
Forming an interlayer insulating film covering the transistor, forming a first contact hole penetrating through the interlayer insulating film and reaching the impurity diffusion region for the common electrode of the transistor; A second portion which reaches the substrate potential fixing impurity diffusion region through the interlayer insulating film and the element isolation insulating film at a location where a film extends above an end of the substrate potential fixing impurity diffusion region; Forming a contact hole, embedding a conductive layer in each of the first and second contact holes, and forming a common wiring on the interlayer insulating film above the conductive layer to form the common electrode. Electrically connecting the impurity diffusion region for substrate and the impurity diffusion region for fixing the substrate potential.

According to the second method of manufacturing a semiconductor device of the present invention,
The second aspect of the present invention in which the contact with the substrate potential fixing impurity diffusion region is arranged on the element isolation insulating film outside the active region.
This is a method for manufacturing the semiconductor device.

In the above manufacturing method, the formation of the first contact hole and the formation of the second contact hole can be performed in the same step. In this case, as in the first manufacturing method, after the transistor forming step, the first and the control electrode surfaces are formed on the surface of the semiconductor substrate and the control electrode corresponding to the entire region of the impurity diffusion region for the common electrode and the entire region of the impurity diffusion region for the output electrode of the transistor. It is preferable to form an etching stop film for stopping etching in the second contact hole forming step, form an interlayer insulating film, and then perform the first and second contact hole forming steps. The function of this etching stop film is the same as that of the first method for manufacturing a semiconductor device of the present invention. However, in the case of this method, the portion to be etched deep to the depth of the substrate potential fixing impurity diffusion region is the element. At the location of the isolation insulating film and at the location of the impurity diffusion region for the common electrode and the impurity diffusion region for the output electrode, the etching depth must be kept on the surface of the impurity diffusion region. Therefore, an etching stop film is formed on the entire region of the impurity diffusion region for the common electrode and the entire region of the impurity diffusion region for the output electrode.

In the first and second methods for manufacturing a semiconductor device according to the present invention, the step of forming the impurity diffusion region for fixing the substrate potential includes the step of introducing an impurity of the second conductivity type into the semiconductor substrate. It is possible to form the impurity diffusion region for fixing the substrate potential and the well region by performing a plurality of times of ion implantation of the second conductivity type while changing the implantation energy, and then performing heat treatment. Since the impurity diffusion region for fixing the substrate potential and the well region are regions in which impurities of the same conductivity type are diffused, for example, after performing high-concentration ion implantation at a deep position in a semiconductor substrate and low-concentration ion implantation at a shallow position, heat treatment is performed. By doing so, it is possible to simultaneously form a substrate potential fixing impurity diffusion region containing a high concentration impurity and a well region containing a lower concentration impurity. With this method,
The photolithography process for forming the substrate potential fixing impurity diffusion region and the photolithography process for forming the well region need only be performed once, and the manufacturing process can be simplified.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a cross-sectional view showing a main part of the semiconductor device of the present embodiment, and shows a substrate potential fixing structure of a gate finger type FET.

As shown in FIG. 1, P-type silicon (Si)
A P-type well layer 2 is formed on a substrate 1 (semiconductor substrate),
An N-channel transistor 3 is formed on P-type well layer 2. That is, a gate electrode 4 (control electrode) made of polysilicon is formed on a P-type Si substrate 1 via a gate insulating film (not shown) made of a silicon oxide film (SiO ₂ ). Reference numeral 4 indicates each electrode finger of the comb-shaped gate electrode. A silicide film 5 is formed on the upper surface of the gate electrode 4, and a sidewall film 6 made of SiO ₂ is formed on a side wall. A region under the gate electrode 4 on the surface of the silicon substrate 1 is a channel region, and N ⁺ -type (first conductivity type) source regions 7 (impurity diffusion regions for common electrodes) and N ^{+ on} both sides of the channel region. Drain region 8 (impurity diffusion region for output electrode).
In the adjacent transistor, the source region 7,
The drain regions 8 are commonly used.

Outside the active region where the transistor 3 is formed on the surface of the silicon substrate 1 is an element isolation region where a field oxide film 9 (element isolation insulating film) is formed.
From the active region inside the silicon substrate 1 to the field oxide film 9
The substrate potential fixing P ⁺ layer 10 (substrate potential fixing impurity diffusion region) is formed at the end of the substrate. Further, a first interlayer insulating film 11 covering the transistor 3 is formed, and contact holes 12 and 13 are formed in portions above the source region 7 and the drain region 8, respectively. The contact hole 12 on the source region 7 side is the first interlayer insulating film 11
Through the source region 7 on the surface of the substrate 1 to reach the inside of the substrate potential fixing P ⁺ layer 10. A silicide film 5 is formed in a region other than the contact hole 12 on the surface of the source region 7. On the other hand, the contact hole 13 on the drain region 8 side penetrates the first interlayer insulating film 11 and stops at the surface of the silicide film 5 formed on the surface of the drain region 8. A tungsten (W) layer 14 is provided inside these contact holes 12 and 13.
(Conductive layer) is embedded.

Tungsten layer 1 on first interlayer insulating film 11
4, a source-side first Al wiring 15 and a drain-side first Al wiring 16 made of aluminum (Al)
Is formed, and a second interlayer insulating film 17 is formed on the first interlayer insulating film 11 including on the first Al wirings 15 and 16. Furthermore, the first Al wiring 1 on the first interlayer insulating film 11
Through holes 18 and 19 penetrating through the second interlayer insulating film 17 are formed in regions above the layers 5 and 16, and the source-side second Al wiring 20 and the drain are formed in regions above the through holes 18 and 19 on the second interlayer insulating film 17. Side second Al wiring 21
Are formed respectively. In addition, the through hole 18,
19 is filled with tungsten.

Next, a method of manufacturing a semiconductor device having the above-described configuration will be described in the order of steps with reference to the process flow charts shown in FIGS. 2 to 4 are plan views of the semiconductor device, and FIGS. 5 to 8 are longitudinal sectional views taken along broken lines in FIGS. First, as shown in FIG. 5A, a pattern (not shown) for forming a P ⁺ layer for fixing the substrate potential is formed on the surface of the P-type Si substrate 1, and then a high implantation energy of about 800 keV to 1.2 MeV is used. By ion-implanting boron (impurities of the second conductivity type), a substrate potential fixing P ⁺ layer 10 is formed at a deep position in the P-type Si substrate 1.

Next, as shown in FIG. 5B, a silicon oxide film 22 and a silicon nitride film 23 are sequentially formed on the entire surface. The thermal oxidation method is used to form the silicon oxide film 22,
A silicon oxide film 22 having a thickness of about 5 to 15 nm is grown at a temperature of 00 to 900 ° C. Also, the silicon nitride film 23
Is formed using a low pressure CVD method, and has a thickness of 100 to 200 n.
A silicon nitride film 23 of about m is grown. Thereafter, a resist pattern 24 for forming a trench (first contact hole) reaching the hole of the element isolation region and the P ⁺ layer for fixing the substrate potential by a photolithography process.
To form

Thereafter, as shown in FIG.
The silicon nitride film 23 and the silicon oxide film 22 are etched by using the resist pattern 24 shown in FIG. 2B as a mask, and then the Si substrate 1 is etched, so that the hole 25 in which the element isolation region is dug, the substrate potential A trench 26 is formed by dug a part of the fixing P ⁺ layer 10. At this time, it is essential that the etching depth is such that the bottom of the trench 26 reaches the P ⁺ layer 10 for fixing the substrate potential, and the depth is 300 to 500 n.
m.

Next, as shown in FIG. 6D, a high-density plasma CVD oxide film 2 is formed on the entire surface by a plasma CVD method.
Grow 7. At this time, the thickness of the high-density plasma CVD oxide film 27
7, it is necessary that the film thickness be sufficiently embedded.
The thickness is set to 500 to 1000 nm. Thereafter, the plasma CVD oxide film 27 on the upper portion of the Si substrate 1 is polished by the CMP method to flatten the substrate 1, and only inside the holes 26 in the element isolation region and the trenches 26 reaching the substrate potential fixing P ⁺ layer 10. With the plasma CVD oxide film 27 buried,
This is referred to as a field oxide film 9. After that, the silicon nitride film 23 and the silicon oxide film 22 are removed by wet etching.

FIG. 2A is a plan view corresponding to the step shown in FIG. In a plan view, a field oxide film 9 is formed in a portion (hatched portion) that becomes a plurality of contacts (six in FIG. 2A) in the element isolation region and the source region of each transistor. And the active region 2
A rectangular pattern of the substrate potential fixing P ⁺ layer 10 is formed so as to cover the outside of the element 8 and the end of the element isolation region. Note that this pattern shape is not limited to a rectangle.

Next, as shown in FIG. 6E, a silicon oxide film (not shown) having a thickness of about 10 to 20 nm is formed on the entire surface by a thermal oxidation method, and then a P-type well layer is formed for ion implantation. A resist pattern 29 is formed, and boron is ion-implanted using the resist pattern 29 as a mask.
At the time of this ion implantation, a plurality of ion implantations with different implantation energies and doses are performed so that the impurity distribution shows a retrograde profile.

Next, as shown in FIG. 6F, after removing the resist pattern 29 and removing the silicon oxide film by wet etching, a gate oxide film (not shown) having a thickness of 10 nm or less is formed on the entire surface. . Then, the film thickness 10
Form a polysilicon film of about 0 to 200 nm on the entire surface,
The polysilicon film and the gate oxide film are patterned by a photolithography process to form a gate electrode 4.

FIG. 2B is a plan view corresponding to the step shown in FIG. In plan view, a plurality of lines (4 in FIG. 2B) are formed on the active region 28 shown in FIG.
The pattern of the comb-shaped gate electrode 4 is formed so as to cover the electrode fingers of the present invention.

Next, as shown in FIG.
A source region 7 and a drain region 8 having a structure are formed. For this purpose, arsenic is ion-implanted at a dose of about 1 × 10 ¹³ cm ⁻² to form an N-type low-concentration diffusion layer (not shown).
Then, after forming a sidewall film 6 made of a silicon oxide film on the side wall of the gate electrode 4 by a well-known method, arsenic is ion-implanted at a dose of about 1 × 10 ¹⁵ cm ⁻² which is higher than the previous ion implantation. Then, an N-type high concentration diffusion layer is formed to be a source region 7 and a drain region 8 having an LDD structure. Through the steps up to here, the gate finger type transistor 3 is formed.

Next, as shown in FIG. 7H, cobalt or titanium (Co or Ti) is formed on the silicon substrate 1 and the polysilicon film forming the gate electrode 4 by using a film forming method such as sputtering and heat treatment. ) Containing silicide 5
(CoSi ₂ , TiSi ₂ ) is selectively grown. Here, the silicide film 5 does not grow on the field oxide film 9 in the element isolation region and on the field oxide film 9 in the contact portion in the source region 7.

Next, as shown in FIG. 7I, a first interlayer insulating film 11 made of a silicon oxide film covering the entire surface is
After the formation by the method D, a resist pattern 30 for forming the contact holes 12 and 13 with the source region 7 and the drain region 8 is formed. At this time, it is necessary to align the source region 7 with the field oxide film 9 (corresponding to the position of the contact hole) reaching the substrate potential fixing P ⁺ layer 10. The dimensions of the holes are determined in consideration of the alignment margin.

Next, as shown in FIG. 8 (j), plasma etching is performed using the resist pattern 30 as a mask to form contact holes 12 and 13 (second contact holes) on the source region 7 and the drain region 8 side, respectively. (As will be described later, actually, a contact hole of the gate electrode 4 is also formed simultaneously). At this time, plasma etching is performed by controlling the etching time, and the etching time is long enough to remove the silicon oxide film having the thickness corresponding to the thickness of the first interlayer insulating film 11 and the depth of the trench 26. To secure.

At this time, the silicide film 5 on the drain region 8 is exposed at the stage when the first interlayer insulating film 11 on the drain region 8 has been completely etched. In general, the silicide film in the etchant for the silicon oxide film is used. Since the etching selectivity with respect to silicon can be sufficiently ensured, the silicide film 5
Functions as an etching stop film, and the drain region 8 side is not etched any more. Also, on the source region 7 side, the opening of the resist pattern 30 is large by the size of the alignment margin, and the silicide film 5 is slightly exposed around the trench 26 when the etching of the first interlayer insulating film 11 is completed. However, the etching is also stopped here, and the size of the trench 26 does not increase. In this embodiment, the silicide film 5 is used.
However, any material other than silicide may be used as long as it is a film material having a large etching selectivity to an etchant for a silicon oxide film.

FIG. 3C is a plan view corresponding to the step shown in FIG. In plan view, the shape of the contact holes 12 and 13 in the source region 7 and the drain region 8 is a slit shape that extends long along the electrode finger of the gate electrode 4. Therefore, especially in the source region 12, the contact hole 12 reaching the entire source region 7 is opened in a slit shape to make contact with the source region 7, and the substantially square trench 26 therein has a substrate potential fixing P ⁺
The structure is such that contact with the layer 10 is obtained. Also,
FIG. 8 (j) is a cross-sectional view taken along the line CC ′. Therefore, in the above description, only the contact holes 12 and 13 for the source region 7 and the drain region 8 are formed in this step. As shown in FIG. 3 (c), a plurality of contacts (FIG. 3 (c)) for making contact between the gate electrode 4 and a gate wiring to be formed later at a connection portion connecting a plurality of electrode fingers of the gate electrode 4. , Three contact holes 31 having a substantially square shape.

Next, as shown in FIG. 8K, a tungsten layer 14 is formed to fill the inside of the contact hole 12 and the trench 26 of the source region 7 and the inside of the contact hole 13 of the drain region 8, respectively.

Next, as shown in FIG. 8 (l), an aluminum film is formed on the entire surface of the first interlayer insulating film 11 and patterned by a photolithography process so as to leave the aluminum film in a region above the tungsten layer 14. Is performed, and the source-side first A is electrically connected to the source region 7 and the drain region 8 at the location of the tungsten layer 4.
An l wiring 15 and a drain-side first Al wiring 16 are formed.

Next, the second interlayer insulating film 1 is formed on the entire surface of the first interlayer insulating film 11 including the first Al wirings 15 and 16.
7 is formed. Then, through holes 18 and 19 penetrating the second interlayer insulating film 17 are formed in regions corresponding to the first Al wirings 15 and 16 by a photolithography process, and then a tungsten film is buried in the through holes 18 and 19. Then, an aluminum film is formed on the entire surface of the second interlayer insulating film 17, and finally, patterning is performed by a photolithography process so as to leave the aluminum film in a region above the through holes 18, 19. , The source-side second Al wiring 20 (common wiring) electrically connected to the source-side first Al wiring 15 and the drain-side first Al wiring 16, and the drain-side second Al wiring 15.
An Al wiring 21 is formed.

FIG. 4D is a plan view corresponding to the step shown in FIG. In plan view, the first A on the source side
1 wiring 15 and second Al wiring 20, first Al on drain side
The wiring 16 and the second Al wiring 21 overlap each other, and the source-side wiring and the drain-side wiring extend in opposite directions along the slit-shaped contact holes 12 and 13 in the source region 7 and the drain region 8. Further, a gate wiring 32 made of a first Al wiring is formed in a direction in which the three contact holes 31 on the gate electrode 4 are arranged (a direction orthogonal to a direction in which the source wiring and the drain wiring extend).
That is, the gate wiring 32 is formed from the first-layer Al wiring, and the source-side wiring and the drain-side wiring are formed from the second-layer Al wiring so as not to be in contact with the gate wiring 4 even when being orthogonal to the gate wiring 4. These wirings have a two-layer wiring structure. Therefore, the source-side first Al wiring 15 and the drain-side first Al wiring 16 exist only on the contact holes 12 and 13 even though they are wirings. Through the above steps, the semiconductor device of the present embodiment is completed.

In the semiconductor device according to the present embodiment, a contact hole penetrating source region 7 of transistor 3 and reaching substrate potential fixing P ⁺ layer 10 is provided, and tungsten layer 14 is buried inside the contact hole. As a result, the substrate potential fixing P ⁺ layer 10 and the source region 7 are electrically connected. Further, the tungsten layer 14 is connected to the source-side second Al
It is connected to the Al wiring 20. Therefore, by fixing the potential of the source-side second Al wiring 20, the source region 7 and the substrate potential fixing P ⁺ layer 10 are fixed to a common potential. Moreover, since all the single transistors 3 constituting the gate finger type FET have such a structure, the gate finger type FET has
The substrate potential can be fixed sufficiently stably unlike the conventional structure in which a contact is made in the peripheral region of.
In the case of the present embodiment, the substrate potential fixing P ⁺ layer 10
Extend to the element isolation region, the substrate potential becomes more stable.

Further, since the contact with the substrate potential fixing P ⁺ layer 10 is made through the source region 7, unlike the conventional structure in which a contact region is provided at a position adjacent to the source region, the FET has The occupied area does not increase so much.

As a result, according to the FET of the present embodiment, the variation of Vt can be sufficiently suppressed. When this gate finger type FET is used for an amplifier in an analog circuit, for example, the variation of the operating point can be reduced. An analog circuit having good characteristics can be realized without causing a problem in characteristics or an increase in occupied area, such as distortion of an output waveform, a decrease in gain, and the like.

Further, in the case of the present embodiment, the silicide film 5 serving as an etching stop film at the time of forming a contact hole is formed on the entire region except for the contact hole 12 in the source region 7 and the drain region 8 and on the upper surface of the gate electrode 4. Was provided. Due to the presence of the silicide film 5, a contact hole having an asymmetric depth on the source side and the drain side, which is a feature of the present invention, can be formed in one photolithography step, and the manufacturing process is not complicated.
The effect described above can be achieved. In addition, since the silicide film 5 is selectively formed in the above-described region, this method is also an excellent method that does not increase the number of photolithography steps.

The use of the silicide film 5 having a lower specific resistance than single crystal silicon or polysilicon not only has an effect on the manufacturing process, but also the source region 7 and the drain region 8 having the silicide film 5 on the surface, and Can reduce the resistance of the gate electrode 4. Therefore, it is possible to obtain an effect on device characteristics such that the response speed of the gate finger type FET can be improved.

[Second Embodiment] Hereinafter, a second embodiment of the present invention will be described.
The embodiment will be described with reference to FIGS.
FIG. 9 is a cross-sectional view showing a main part of the semiconductor device of the present embodiment, and shows a substrate potential fixing structure of a gate finger type FET. This embodiment is the same as the first embodiment in that a substrate potential fixing P ⁺ layer is provided in the substrate, but the contact form is different. That is, the first
In this embodiment, the substrate potential fixing P
^In contrast to the case where a common contact for connecting to the ⁺ layer is taken, in the present embodiment, a contact for connecting to the substrate potential fixing P ⁺ layer through the field oxide film of the element isolation region separately from the source region is provided. The differences are different.

As shown in FIG. 9, a P-type silicon substrate 1
An N-channel transistor 3 is formed on a P-type well layer 2 on the surface of a (semiconductor substrate). That is, a gate electrode 4 made of polysilicon is formed on a P-type silicon substrate 1 via a gate insulating film (not shown). A silicide film 5 is formed on the upper surface of the gate electrode 4, and a sidewall film 6 is formed on a side wall. An N ⁺ type (first conductivity type) source region 7 (impurity diffusion region for common electrode) and an N ⁺ type drain region 8 are formed on the surface of the silicon substrate 1.
(Impurity diffusion region for output electrode) is formed.

A field oxide film 9 (insulating film for device isolation) is formed in a device isolation region on the surface of the silicon substrate 1, and a substrate potential fixing P ⁺ extends from the active region inside the silicon substrate 1 to the end of the field oxide film 9. A layer 10 has been formed. Further, a first interlayer insulating film 11 covering the transistor 3 is formed, and contact holes 34 and 13 (first contact holes) penetrating the first interlayer insulating film 11 are formed in portions above the source region 7 and the drain region 8, respectively. Is formed. The first interlayer insulating film 1 is formed at a position where the substrate potential fixing P ⁺ layer 10 extends to the end of the field oxide film 9.
1 and a contact hole 35 (second contact hole) penetrating through the field oxide film 9 and reaching the substrate potential fixing P ⁺ layer 10. A silicide film 5 is formed over the entire region of the source region 7 and the drain region 8 on the surface of the silicon substrate 1, and the contact holes 34 and 13 on the source region 7 and the drain region 8 stop at the surface of the silicide film 5. The tungsten (W) layer 14 (conductive layer) is buried in all of the contact holes 34, 13, and 35.

Tungsten layer 1 on first interlayer insulating film 11
4, the source-side first Al wiring 36 and the drain-side first Al wiring 16 made of aluminum (Al)
Are formed, and the source-side first Al wiring 36 extends to above the tungsten layer 14 in the contact hole 35 on the field oxide film 9 and is connected thereto. The second interlayer insulating film 17 is formed on the first interlayer insulating film 11 including the first Al wirings 36 and 16. Further, through-holes 18 and 19 penetrating the second interlayer insulating film 17 are formed in regions on the first Al wirings 36 and 16 on the first interlayer insulating film 11, and the through-holes 18 and 19 on the second interlayer insulating film 17 are formed. A source-side second Al wiring 37 and a drain-side second Al wiring 21 are respectively formed in regions above 19. In addition, through hole 1
A tungsten layer is buried in 8 and 19 like the contact portion.

Next, a method of manufacturing the semiconductor device having the above configuration will be described in the order of steps with reference to the process flow charts of FIGS. FIGS. 10 to 13 are plan views of the semiconductor device, and FIGS. 14 and 15 are longitudinal sectional views taken along the broken line passing through the contact hole on the field oxide film in FIGS. FIG. 14 is a longitudinal sectional view taken along a broken line crossing the gate electrode in FIGS.

In the manufacturing method of the present embodiment, FIG.
(A), as shown in FIG.
To the substrate potential fixing P⁺From the step of forming the layer 10
For forming a p-well layer 2
The steps up to the step of forming the gate electrode 4 are substantially the same.
Therefore, detailed description during this period is omitted. However, the first
Penetrates the portion to be the source region 7 as in the embodiment
To fix the substrate potential P ⁺A trench 26 reaching the layer 10
The field oxide film 9 does not need to be formed, and is selectively oxidized.
What is necessary is just to form.

FIG. 10A is a plan view showing a state after the substrate potential fixing P ⁺ layer forming step is completed, and the pattern of the substrate potential fixing P ⁺ layer 10 is an element isolation outside the active region 28. It overlaps with the pattern edge of the field oxide film 9 in the region. FIG. 11B shows a plan view after the gate electrode forming step is completed, and the comb-shaped gate electrode 4 having a plurality of (four in FIG. 11B) electrode fingers on the active region 28. Is formed.

After the formation of the gate electrode 4, FIG.
As shown in FIG. 6B, arsenic is ion-implanted to form an N-type low-concentration diffusion layer (not shown). And the gate electrode 4
After the sidewall film 6 is formed on the side wall of the substrate, arsenic is ion-implanted again to form an N-type high-concentration diffusion layer, thereby forming a source region 7 and a drain region 8 having an LDD structure. Through the above steps, the transistor 3 is formed.

Next, the source region 7 on the silicon substrate 1
A silicide film 5 is selectively grown over the entire region and the entire drain region 8 and over the gate electrode 4. Next, after the first interlayer insulating film 11 is formed on the entire surface, the source region 7, the drain region 8, and the contact hole 3 on the field oxide film 9 are formed.
A resist pattern (not shown) for forming 4, 13, and 35 is formed. Next, plasma etching is performed using this resist pattern as a mask to form a source region 7.
Contact hole 34 on the drain region 8, the contact hole 13 on the drain region 8, and the contact hole 35 on the field oxide film 9 where the substrate potential fixing P ⁺ layer 10 extends to the end of the field oxide film 9 (the first contact hole 35). (A contact hole on the gate electrode is also formed at the same time as described later). At this time, plasma etching is performed by controlling the etching time, and as shown in FIG.
A sufficient etching time is ensured so that the upper contact hole 35 penetrates the field oxide film 9 and reaches the substrate potential fixing P ⁺ layer 10. At this time, as shown in FIG. 16B, the silicide film 5 functions as an etching stop film on the source region 7 and the drain region 8, and the etching stops on the surface of the silicide film 5.

FIG. 12C is a plan view corresponding to the steps shown in FIGS. 14B and 16B. In plane,
Contact holes 3 of source region 7 and drain region 8
The shapes of 4 and 13 are slit-like shapes that extend long along the gate electrode 4. Further, two contact holes 35 on the field oxide film 9 are provided on both sides along the direction in which each source region 7 extends. Although not shown in the cross-sectional views of FIGS. 14B and 16B, in actuality, FIG.
As shown in FIG. 12C, a plurality of contacts (3 in FIG. 12C) for making contact between the gate electrode 4 and a gate wiring to be formed later at a connection portion connecting a plurality of electrode fingers of the gate electrode 4. ) Contact holes 31 are formed.

Next, as shown in FIGS. 15C and 17C, the inside of the contact hole 34 of the source region 7, the inside of the contact hole 13 of the drain region 8, and the inside of the contact hole 35 on the field oxide film 9. Are formed to form tungsten layers 14 respectively. Next, a source-side first Al wiring 36 and a drain-side first Al wiring 16 that are electrically connected to the source region 7 and the drain region 8 respectively at the location of the tungsten layer 14 on the first interlayer insulating film 11 are formed. The source-side first Al wiring 36 is as shown in FIG.
As shown in FIG. 5, the wiring extends to above the tungsten layer 14 in the contact hole 35 on the field oxide film 9 to serve as a common wiring for the source region 7 and the substrate potential fixing P ⁺ layer 10.

Next, after the second interlayer insulating film 17 is formed, the first Al wiring 36 on the source side and the first Al wiring 36 on the drain side are formed.
Through holes 18 and 19 penetrating the second interlayer insulating film 17 are formed on the l wiring 16 respectively.
19. Tungsten is buried in the inside of 19. Then, an aluminum film is formed on the entire surface.
At 19 places, a source-side second Al wiring 37 and a drain-side second Al wiring 21 electrically connected to the source-side first Al wiring 36 and the drain-side first Al wiring 16, respectively, are formed.

FIG. 13D is a plan view corresponding to the step shown in FIGS. 15C and 17C. In plane,
The first Al wiring 36 and the second Al wiring 37 on the source side and the first Al wiring 16 and the second Al wiring 21 on the drain side are both overlapped, and the source wiring and the drain wiring are slit-shaped in the source region 7 and the drain region 8. Extend in the opposite direction along the contact holes 34, 13. Also,
A gate wiring 32 made of a first Al wiring is formed in a direction in which the three contact holes 31 on the gate electrode 4 are arranged (a direction orthogonal to a direction in which the source-side wiring and the drain-side wiring extend). Through the above steps, the semiconductor device of the present embodiment is completed.

In this embodiment, the source region 7 and the substrate potential fixing P ⁺ layer 10 are connected via the tungsten layer 14 to the source-side first Al wiring 36 and the source-side second Al wiring 37.
Are connected in common. Therefore, by fixing the potential of the source-side second Al wiring 37, the source region 7 and the substrate potential fixing P ⁺ layer 10 are fixed to a common potential, and the substrate potential can be fixed sufficiently stably. . Also,
Also in the case of the present embodiment, since the substrate potential fixing P ⁺ layer 10 extends to the element isolation region, the substrate potential is more stable.

Further, in the case of the present embodiment, since the contact portion with the substrate potential fixing P ⁺ layer 10 is provided in the element isolation region not used for forming the element, the occupation area of the FET may increase. In addition, when compared with the first embodiment, it is possible to reduce the occupation area of the source region 7 in particular.

As described above, also in the FET of the present embodiment, the fluctuation of Vt is suppressed to a small value. When this gate finger type FET is used for an analog circuit or the like, the distortion of the output waveform due to the fluctuation of the operating point, An effect similar to that of the first embodiment, in which an analog circuit having good characteristics can be realized without causing a problem in characteristics such as a decrease in gain or an increase in occupied area, can be obtained.

[Third Embodiment] Hereinafter, a third embodiment of the present invention will be described.
The embodiment will be described with reference to FIG. FIG. 18 is a cross-sectional view showing a main part of the semiconductor device of the present embodiment,
1 shows a substrate potential fixing structure of a gate finger type FET. This embodiment is similar to the first and second embodiments in that a substrate potential fixing P ⁺ layer is provided in the substrate.
The form of the contact is different. That is, in the first and second embodiments, a contact connected to the potential fixing P ⁺ layer is taken from the front surface side of the substrate aside from the position of the contact. The difference is that a contact is made from the side to be connected to the substrate potential fixing P ⁺ layer.

As shown in FIG. 18, a P-type silicon substrate 1
An N-channel transistor 3 is formed on a P-type well layer 2 on the surface of a (semiconductor substrate). That is, a polysilicon gate electrode 4 having a sidewall film 6 is formed on a P-type silicon substrate 1 with a gate insulating film (not shown) interposed therebetween. Then, an N ⁺ type (first
Source region 7 of conductivity type (impurity diffusion region for common electrode)
And an N ⁺ type drain region 8 (impurity diffusion region for output electrode).

Outside the active region on the surface of the silicon substrate 1 is an element isolation region on which a field oxide film 9 (insulating film for element isolation) is formed. The substrate potential fixing P ⁺ layer 10 is formed over the end. Also, the first on the substrate 1
An interlayer insulating film 11 is formed, and a contact hole 13 is formed in a portion of the first interlayer insulating film 11 above the drain region 8. Then, a contact hole 39 is formed from the back side of the substrate 1 through the substrate potential fixing P ⁺ layer 10 and reaches the source region 7. A tungsten (W) layer 14 is provided inside these contact holes 13 and 39.
(Conductive layer) is embedded.

Tungsten layer 1 on first interlayer insulating film 11
4, a drain-side first Al wiring 16 made of aluminum (Al) is formed in a region above, and a second interlayer insulating film 17 is formed on the first interlayer insulating film 11. Further, the first Al wiring 1 on the drain side on the first interlayer insulating film 11 is formed.
A through hole 19 penetrating through the second interlayer insulating film 17 is formed in a region corresponding to 6, and tungsten is buried in the through hole 19. Then, the second interlayer insulating film 1
The drain-side second Al wiring 21 is formed in a region above the through hole 19 on the gate 7.

In the case of the present embodiment, P
By fixing the potential of the silicon substrate 1 itself, the potentials of the substrate potential fixing P ⁺ layer 10 and the source region 7 can be fixed. Therefore, a great advantage of this embodiment is that a source wiring is not required on the front surface side of the substrate 1.

The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, in the above-described embodiment, an example was given in which a P-type silicon substrate was used as the semiconductor substrate, an N-channel transistor was formed on the P-type well layer, and the impurity diffusion region for fixing the substrate potential was P-type. The configuration to which the present invention can be applied is not limited thereto, and the above-described respective conductivity types may be reversed, or a configuration in which a transistor is directly formed on a substrate without providing a well layer may be used.

In the above embodiment, the impurity diffusion region for fixing the substrate potential is formed by introducing an impurity into the semiconductor substrate. However, a metal layer is used instead of this type of the impurity diffusion region for fixing the substrate potential. You can also. A structure in which a metal layer is formed at a deep position in a semiconductor substrate can be realized by using a technique of bonding two semiconductor substrates. The use of the metal layer has an advantage that the substrate resistance can be further reduced as compared with the case where the impurity diffusion region for fixing the substrate potential in which an impurity is introduced into the semiconductor is used.

Various specific descriptions, such as the planar shape of each pattern used in the above embodiment, dimensions such as constituent materials and film thickness of each layer, and processing conditions of each step in the manufacturing method, are appropriately given. Of course, the design can be changed.

[0084]

As described above in detail, according to the present invention, an impurity diffusion region for fixing a substrate potential is provided below a gate finger type FET, and this is electrically connected to the impurity diffusion region for a common electrode. As a result, the substrate potential can be fixed sufficiently stably. At this time, since the contact of the impurity diffusion region for fixing the substrate potential penetrates the impurity diffusion region for the common electrode or is arranged in the element isolation region, the occupied area of the transistor does not increase. As a result, the variation of the threshold voltage of the transistor can be suppressed sufficiently small. When this gate finger type FET is used for an amplifier in an analog circuit, for example, the distortion of the output waveform and the gain due to the variation of the operating point Thus, an analog circuit having stable characteristics can be realized without causing a defect in characteristics or an increase in occupied area, such as a decrease in the characteristics.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a main part of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process flow diagram (plan view) showing the manufacturing steps of the semiconductor device in order.

FIG. 3 is a continuation of the process flow diagram.

FIG. 4 is a continuation of the process flow diagram.

FIG. 5 is a process flow diagram (longitudinal sectional view) showing the manufacturing steps of the semiconductor device in order.

6 is a continuation of the same process flow diagram (FIG. 6).
(D) is a longitudinal sectional view along the line AA ′ in FIG. 2 (a), and FIG. 6 (f) is a longitudinal sectional view along the line BB ′ in FIG. 2 (b).

FIG. 7 is a continuation of the process flow diagram.

8 is a continuation of the same process flow diagram (FIG.
(J) is a longitudinal sectional view along the line CC ′ in FIG. 3 (c), and FIG. 8 (l) is a longitudinal sectional view along the line DD ′ in FIG. 4 (d).

FIG. 9 is a longitudinal sectional view showing a main part of a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a process flow diagram (plan view) showing the manufacturing steps of the semiconductor device in order.

FIG. 11 is a continuation of the process flow diagram.

FIG. 12 is a continuation of the process flow diagram.

FIG. 13 is a continuation of the process flow diagram.

FIG. 14 is a process flow diagram (longitudinal sectional view) showing the manufacturing steps of the semiconductor device in order (FIG. 14 (a)).
FIG. 14B is a longitudinal sectional view taken along the line AA ′ of FIG. 11B, and FIG. 14B is a longitudinal sectional view taken along the line CC ′ of FIG.

FIG. 15 is a continuation of the same process flow diagram (FIG. 1);
FIG. 5 (c) is a longitudinal sectional view taken along line EE ′ of FIG. 13 (d)).

16 is a continuation of the same process flow diagram (FIG. 1)
6 (a) is a longitudinal sectional view taken along line BB 'of FIG. 11 (b), and FIG. 16 (b) is a longitudinal sectional view taken along line DD' of FIG. 12 (c).

17 is a continuation of the same process flow diagram (FIG. 1)
7 (c) is a longitudinal sectional view taken along line FF 'of FIG. 13 (d)).

FIG. 18 is a longitudinal sectional view showing a main part of a semiconductor device according to a third embodiment of the present invention.

FIG. 19 is a plan view showing an example of a well contact structure in a conventional semiconductor device.

FIG. 20 is a plan view showing another example of a well contact structure in a conventional semiconductor device.

FIG. 21 is a cross-sectional view showing an improved example of a well contact structure in a conventional semiconductor device.

FIG. 22 is a cross-sectional view showing another improved example of a well contact structure in a conventional semiconductor device.

FIG. 23 is an example of a graph showing a relationship between a parameter of the MOSFET threshold voltage _{(2Φ f + V S B)} 1/2 and V _t.

FIG. 24 is a diagram showing a V _ds -I _d characteristic of a MOSFET.

[Description of Signs] 1 P-type silicon substrate (semiconductor substrate) 2 P-type well layer 3 N-channel transistor 4 gate electrode (control electrode) 5 silicide film (etching stop film) 6 sidewall film 7 source region (impurity for common electrode) Diffusion region) 8 drain region (impurity diffusion region for output electrode) 9 field oxide film (insulating film for element isolation) 10 substrate potential fixing P ⁺ layer (substrate potential fixing impurity diffusion region) 11 first interlayer insulating film 12 13, 34, 35, 39 Contact hole 14 Tungsten layer (conductive layer) 15, 36 Source-side first Al wiring 16 Drain-side first Al wiring 17 Second interlayer insulating film 18, 19 Through hole 20, 37 Source-side second Al wiring

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 4M104 AA01 BB18 BB20 BB25 CC01 DD05 DD08 FF02 FF18 FF27 GG09 GG14 5F033 HH08 JJ19 KK01 KK25 KK27 MM30 NN03 NN38 NN39 QQ08 QQ09 QQ16 QQ24 QQ13 EC03 EC07 EC07 EC17 EF02 EH08 EJ07 EK05 EM00 FA03 FA05 FB02 FC10 FC21 5F048 AA07 AA09 AB10 AC01 BA01 BA12 BB02 BB05 BC02 BC06 BC12 BE09 BF07 BF11

Claims (24)

[Claims] 1. A control electrode having a plurality of electrode fingers, a common electrode, and an output electrode on a semiconductor substrate, wherein one electrode finger of the control electrode, an impurity diffusion region for a common electrode, and an impurity diffusion region for an output electrode are provided. An active region formed by adjoining a plurality of transistors having the same structure, wherein the semiconductor substrate is located below a common electrode impurity diffusion region of each of the transistors into which an impurity of the first conductivity type is introduced. And a substrate potential fixing impurity electrically connected to the impurity diffusion regions for the common electrode and having a second conductivity type impurity opposite to the first conductivity type introduced thereinto. A semiconductor device, wherein a diffusion region is formed. 2. The semiconductor device according to claim 1, wherein said substrate potential fixing impurity diffusion region extends to an element isolation region outside said active region. 3. The method according to claim 2, wherein the impurity diffusion region for the common electrode is a second impurity diffusion region.
Formed on the well region where the conductivity type impurity is introduced,
3. The semiconductor device according to claim 1, wherein said substrate potential fixing impurity diffusion region is formed inside said well region. 4. A contact hole penetrating through the impurity diffusion region for a common electrode of each of the transistors and reaching the impurity diffusion region for fixing the substrate potential, wherein a conductive layer is embedded in the contact hole. 4. The semiconductor device according to claim 1, wherein said substrate potential fixing impurity diffusion region is electrically connected to each of said common electrode impurity diffusion regions. 5. A common wiring is provided on an interlayer insulating film covering the plurality of transistors, and a conductive layer embedded in the contact hole and the common wiring are electrically connected. Item 5. The semiconductor device according to item 4. 6. The surface of the semiconductor substrate and the surface of the control electrode corresponding to the entire region of the impurity diffusion region for an output electrode of each transistor and the region other than the contact hole portion in the impurity diffusion region for a common electrode of each of the transistors. 6. The semiconductor device according to claim 4, wherein an etching stop film is provided when forming a contact hole. 7. The semiconductor device according to claim 6, wherein said interlayer insulating film is a silicon oxide film, and said etching stop film is a silicide film. 8. A control electrode having a plurality of electrode fingers, a common electrode, and an output electrode on a semiconductor substrate, wherein one electrode finger of the control electrodes, a common electrode impurity diffusion region, and an output electrode impurity diffusion region. An active region formed by adjoining a plurality of transistors having the same structure, wherein the semiconductor substrate is located below a common electrode impurity diffusion region of each of the transistors into which an impurity of the first conductivity type is introduced. Substrate potential fixing, which is electrically connected to the element and extends to below the element isolation insulating film outside the active region, and into which impurities of a second conductivity type opposite to the first conductivity type are introduced. A first contact hole, in which an impurity diffusion region for a transistor is formed, and an interlayer insulating film covering the plurality of transistors, penetrating the interlayer insulating film and reaching the impurity diffusion region for a common electrode of each transistor; A second contact hole penetrating through the interlayer insulating film and the element isolation insulating film and reaching the substrate potential fixing impurity diffusion region is provided, and a conductive layer is formed inside the first and second contact holes. Each of the conductive layers is buried and electrically connected to a common wiring provided on the interlayer insulating film, and the impurity diffusion region for fixing the substrate potential is electrically connected to the impurity diffusion region for each common electrode. A semiconductor device, wherein the semiconductor device is connected to a semiconductor device. 9. The impurity diffusion region for a common electrode is formed on a well region into which an impurity of a second conductivity type is introduced, and the impurity diffusion region for fixing a substrate potential is formed inside the well region. The semiconductor device according to claim 8, wherein 10. An etching stop film at the time of forming the contact hole is formed on the surface of the semiconductor substrate and the surface of the control electrode corresponding to the entire region of the impurity diffusion region for the common electrode and the entire region of the impurity diffusion region for the output electrode of each transistor. The semiconductor device according to claim 8, wherein the semiconductor device is provided. 11. The semiconductor device according to claim 10, wherein said interlayer insulating film is a silicon oxide film, and said etching stop film is a silicide film. 12. A control electrode having a plurality of electrode fingers, a common electrode, and an output electrode on a semiconductor substrate, wherein one of the control electrodes is an electrode finger, a common electrode impurity diffusion region, and an output electrode impurity diffusion region. An active region formed by adjoining a plurality of transistors having the same structure, wherein the semiconductor substrate is located below a common electrode impurity diffusion region of each of the transistors into which an impurity of the first conductivity type is introduced. A substrate potential fixing impurity diffusion region electrically connected to the first conductivity type and doped with an impurity of a second conductivity type opposite to the first conductivity type is formed, and the substrate potential fixation is performed from the back surface side of the semiconductor substrate. A contact hole penetrating through the impurity diffusion region for the common electrode and reaching the impurity diffusion region for the common electrode, and that a conductive layer is embedded in the contact hole. Characteristic semiconductor device. 13. The semiconductor substrate according to claim 1, wherein said semiconductor substrate is made of a material different from a material of said semiconductor substrate in place of said substrate potential fixing impurity diffusion region in which said second conductivity type impurity is introduced into said semiconductor substrate. 13. The semiconductor device according to claim 1, further comprising a substrate potential fixing conductive layer having the same function as the substrate potential fixing impurity diffusion region. 14. The semiconductor device according to claim 13, wherein said substrate potential fixing conductive layer is made of metal. 15. A step of forming a substrate potential fixing impurity diffusion region by introducing a second conductivity type impurity into a semiconductor substrate, and a step of arriving at the substrate potential fixing impurity diffusion region in the semiconductor substrate. Forming a contact hole, an impurity diffusion region for a common electrode and a control electrode and an impurity of a first conductivity type opposite to the second conductivity type introduced into the surface of the semiconductor substrate, and an output electrode. Forming a transistor having an impurity diffusion region such that the impurity diffusion region for a common electrode of the transistor includes the first contact hole formation portion in the transistor; and forming a conductive region in the first contact hole. Electrically connecting the common electrode impurity diffusion region and the substrate potential fixing impurity diffusion region by burying a layer. Manufacturing method of a semiconductor device. 16. A step of forming an interlayer insulating film covering the transistor after the transistor forming step, and forming a second contact hole penetrating the interlayer insulating film and continuous with the first contact hole. And a step of burying a conductive layer in a contact hole where the first and second contact holes are continuous to electrically connect the common electrode impurity diffusion region and the substrate potential fixing impurity diffusion region. The method according to claim 15, further comprising: forming a common wiring on the interlayer insulating film above the conductive layer. 17. After the first contact hole forming step, a silicon oxide film is embedded in the first contact hole, the transistor is formed, and the interlayer insulating film made of a silicon oxide film is formed. Then, in the step of forming the second contact hole penetrating the interlayer insulating film, etching the interlayer insulating film,
17. The semiconductor according to claim 16, wherein the silicon oxide film embedded in the contact hole is continuously etched to form a contact hole in which the first and second contact holes are continuous. Device manufacturing method. 18. The method according to claim 18, wherein said silicon oxide film is buried in said first contact hole, said transistor is formed, and then a region excluding a first contact hole forming portion in said transistor common electrode impurity diffusion region and said transistor are formed. Forming an etching stop film for stopping etching in the second contact hole forming step on the surface of the semiconductor substrate and the surface of the control electrode corresponding to the entire area of the impurity diffusion region for output electrodes; 18. The method according to claim 17, wherein the second contact hole forming step is performed after the formation. 19. The method according to claim 18, wherein a silicide film is used as the etching stop film. 20. A step of forming a substrate potential fixing impurity diffusion region by introducing a second conductivity type impurity into a semiconductor substrate, and forming an end portion of the substrate potential fixing impurity diffusion region on the semiconductor substrate surface. Forming a device isolation insulating film extending upward; and providing a control electrode and a second conductive type opposite to the second conductivity type in an active region of the semiconductor substrate surface excluding a region where the device isolation insulating film is formed. Forming a transistor having an impurity diffusion region for a common electrode and an impurity diffusion region for an output electrode into which an impurity of a first conductivity type, which is a conductivity type, is introduced; and a step of forming an interlayer insulating film covering the transistor. Forming a first contact hole penetrating through an interlayer insulating film and reaching the impurity diffusion region for the common electrode of the transistor; and fixing the element isolation insulating film to the substrate potential. Forming a second contact hole extending through the interlayer insulating film and the element isolation insulating film to reach the substrate potential fixing impurity diffusion region at a location extending above an end of the impurity diffusion region for substrate use. Process and
Embedding a conductive layer in each of the first and second contact holes; and forming a common wiring on the interlayer insulating film above the conductive layer to fix the impurity diffusion region for the common electrode and the substrate potential. Electrically connecting the impurity diffusion region to the semiconductor device. 21. The method according to claim 20, wherein forming the first contact hole and forming the second contact hole are performed in the same step. 22. After the step of forming the transistor, the first and the first surfaces of the semiconductor substrate and the control electrode which correspond to the entire region of the impurity diffusion region for the common electrode and the entire region of the impurity diffusion region for the output electrode of the transistor. An etching stop film for stopping etching in a second contact hole forming step is formed, and after forming the interlayer insulating film, the first and second contact hole forming steps are performed. Item 22. The method for manufacturing a semiconductor device according to item 21. 23. The method according to claim 22, wherein a silicide film is used as the etching stop film. 24. In the step of forming the impurity diffusion region for fixing the substrate potential, a plurality of times of the implantation of the second conductivity type having different implantation energy when introducing the impurity of the second conductivity type into the semiconductor substrate. 16. The semiconductor device according to claim 15, wherein the impurity ions are implanted, and the heat treatment is performed thereafter to form the impurity diffusion region for fixing the substrate potential and the well region.
24. The method for manufacturing a semiconductor device according to any one of items 23 to 23.