JP2002330345A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pickup device with hyperfine structured pixels and a high S/N. SOLUTION: The image pickup device is provided with a plurality of pixels placed in vertical and horizontal directions, in each of which a floating well of an amplification purpose field effect transistor stores electric charges photoelectrically converted from light, the transistor outputs a signal in response to a potential change in the floating well to an output line, the floating well is brought into a depletion state and the electric charges photoelectrically converted from light is reset; a drive means which reads a 1st signal from the pixel after storing the electric charges photoelectrically converted from light for a prescribed time, brings the floating well into the depletion state after reading the 1st signal from the pixel to reset the electric charges photoelectrically converted from light, and reads a 2nd signal from the pixel; and a differential output means which outputs a difference between the 1st and 2nd signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high S / N ratio of an imaging device, and more particularly to a threshold modulation type imaging device capable of resetting a photocharge storage region to a complete depletion.

[0002]

2. Description of the Related Art In recent years, active CMOS sensors that can be manufactured by a CMOS process as solid-state imaging devices with low power consumption, low voltage driving, and low cost have been actively developed. In a general active CMOS sensor, since one pixel is composed of three to four MOS transistors, it is difficult to reduce the pixel size as compared with a CCD. Conventionally, an active CMOS sensor using threshold modulation of a MOS transistor has been proposed as a CMOS sensor that compensates for the disadvantage of miniaturization. As a threshold modulation type solid-state imaging device, for example, Patent No. 30
There is a solid-state image sensor proposed by Shinohara in Japanese Patent No. 16815. FIG. 13 is a circuit diagram and a cross-sectional view of this solid-state imaging device.
And FIG.

In FIG. 1, reference numeral 4 denotes a vertical output line, 5 denotes a horizontal drive line, 6 denotes a MOS transistor for resetting the vertical output line 4, 7 denotes a capacitor for accumulating a signal from a pixel, and 8 denotes a pixel. MOS transistor for transferring the output of capacitor 7 to capacitor 7, 9 is a horizontal output line, 10 is a MOS transistor for transferring the output of capacitor 7 to horizontal output line 9, and 10 is the output of capacitor 7 to horizontal output line 9. MOS transistor for transfer, 11 is a buffer MOS transistor that is selected by the vertical shift register and applies a drive pulse to the pixel, 12 is a preamplifier that outputs a sensor output, and 13 is a pulse that is applied to the gate of the MOS transistor 6 Input terminal for driving the drive pulse to MO
An input terminal for applying the voltage to the S transistor 11 and an output terminal 16 are provided. Reference numeral 17 denotes an n ⁻ region having a low impurity concentration;
Is a silicon oxide film, and 19 is a p-type well in which photocharges are stored, which are independent for each pixel. 20 is the element isolation region and MO
N ⁺ region also serving as drain of S transistor, 21 is MOS
An n ⁺ region as a source of the transistor, 22 is a horizontal drive line as a gate of the MOS transistor, and 23 is an n ^{+ as a} source.
A vertical output line connected to the region 21; 24, a contact hole for connecting the n ⁺ region 21 as a source to the output line 23;
Is an interlayer insulating film. 26 is a MOS transistor having a capacitance (P well) constituting a pixel, 27 is a power supply terminal of the source of the reset MOS transistor 6, and 28 is a MOS for resistive load.
The transistor 29 is an input terminal for applying a pulse to the gate.

This solid-state imaging device accumulates photoelectrically converted photocharges in a semiconductor region, amplifies the photocharges accumulated in the semiconductor region by a MOS transistor, and outputs the amplified photocharges from a main electrode to an output line. Has a plurality of pixels. Therefore, by reading the potential change of the floating semiconductor region from the main electrode of the MOS transistor, it is possible to output a signal corresponding to the accumulated electric charges completely non-destructively at the time of reading.

[0005]

However, as a result of detailed study and examination, kTC noise is generated in this solid-state imaging device because the well is not completely depleted when the well is reset.・ Low sensitivity due to large well capacity. It turned out that there was a drawback.

[0006]

In order to solve the above problem, photoelectrically converted photoelectric charges are accumulated in a floating well of an amplifying field effect transistor, and a signal corresponding to a change in the potential of the floating well is output to an output line. Output, resetting the photocharge by depleting the floating well, a pixel having a plurality of pixels in the vertical and horizontal directions,
Reading the first signal from the pixel after accumulating the photocharge for a predetermined time, after reading the first signal from the pixel, and after resetting the photocharge by depleting the floating well and depleting the floating well; And a driving unit for reading a second signal from the pixel, and a differential output unit for outputting a difference between the first signal and the second signal.

A first semiconductor region of a first conductivity type;
A photoelectric conversion portion formed of a second semiconductor region having a conductivity type opposite to that of the first semiconductor region formed on a surface of the semiconductor region; and a gate electrode provided on the first semiconductor region. A field-effect transistor that outputs a signal corresponding to a threshold change due to a potential change of the first semiconductor region to an output line, wherein the first semiconductor region has a higher concentration than the first semiconductor region. A pixel in which a third semiconductor region of a conductivity type is formed in a vertical direction and a horizontal direction, and further, after a photocharge is accumulated in the first semiconductor region for a predetermined time, a first signal is read from the pixel; After the first signal has been read out of the pixel and after resetting the photocharge of the first semiconductor region,
And a differential output unit that outputs a difference between the first signal and the second signal.

In the above-described pixel configuration, there is a feature that kTC noise is not generated in principle by the complete depletion reset of the signal storage section. Also, FPN due to processing variations of the amplifying element can be suppressed to a practically acceptable level by the noise elimination circuit.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is an equivalent circuit diagram of a solid-state imaging device for explaining this embodiment,
They are formed on the same semiconductor substrate by a process.
Actually, pixels are in the area of several hundred thousand to several million, and even 1000
The array is made up of an area of 10,000 pixels or more, but here, for simplicity, a 3 × 3 pixel area is described.

FIG. 2 is a diagram showing a sectional view of a pixel of the solid-state imaging device of FIG. The same parts as those in FIG. 14 are denoted by the same reference numerals.

FIG. 2 shows a structure in which generated charges are swept out to the substrate to perform a complete depletion reset, and a structure in which a potential pocket for accumulating photocharges is provided in a well near the source of a MOS transistor. In the figure, reference numeral 1 denotes a p-type silicon substrate, and 2 denotes a p-type high-concentration region having a higher concentration than the p-type well 19, and serves as a potential pocket for holes. The n ⁺ region 20 as a high impurity diffusion layer and the p-type well region form a pn junction photodiode as a photoelectric conversion element. The n ⁺ region 20 also functions as a drain region of the MOS transistor. N ⁺ region 21
This is the source region of the MOS transistor.

All the photocharges generated in the photoelectric conversion region are transferred to the two potential pockets, and the threshold is modulated by the potential change of the potential pocket, and a signal is output in accordance with the variation of the threshold. In this case, since the sensitivity is substantially determined by the capacity of the potential pocket instead of the capacity of all the floating wells of the conventional example described above, a high-sensitivity solid-state imaging device can be realized. At the time of reset, a pulse of positive polarity is applied to the gate electrode 22, and the p-type potential pocket 2, the p-type well 19, the n-type semiconductor layer 17, and the p-type silicon substrate 1 are forward-biased in the substrate direction, so that the storage region Perform a full depletion reset. This form realizes a solid-state imaging device with no reset noise and high sensitivity.

Here, fixed pattern noise due to threshold variation due to the processing accuracy of the amplifying MOS transistor still remains.
Since the PN becomes large, there is a problem that the increase in FPN becomes a serious problem in miniaturization of pixels.

In order to solve the problem, in the present embodiment, a circuit configuration for performing FPN removal is provided as shown in FIG. Generally, as a means for removing FPN, there is a method of storing FPN data in an external memory and subtracting it systematically. However, a configuration as shown in FIG. 1 is desirable in consideration of the number of parts and product cost.

In FIGS. 1 and 2, 3 is a pixel, 30 is W or Al
Etc., 31 is a passivation film such as SiN or SiON, 3
2 is a differential amplifier circuit, 34 is an Al line for driving a gate electrode, 40 is an entire readout circuit, 41 is a MOS memory capacity for storing optical signals, 42 is a MOS memory capacity for storing dark signals, and 4
1 and 42 are so-called line memories provided one for each column. 43 is a transfer MOS switch for reading a signal to each memory capacity of 41 and 42, and 44 is a horizontal transfer for outputting a signal stored in the memory capacity to 32 differential amplifiers
This is a MOS switch and is driven by a horizontal shift register. Here, the same components as those in the conventional example are denoted by the same reference numerals, and description thereof is omitted here. In a general conventional noise elimination circuit, the S + N signal is read after the N signal is read, but in the present embodiment, the N + signal is read after the S + N signal is read.
It is a driving method for reading out signals.

In this embodiment, one of the source electrodes 1
A gate electrode is provided adjacent to the side, and the potential pocket 2 is provided near the source region 21 and on one side of the source region 21.

As described above, by providing the potential pocket 2 on one side of the source region 21,
Ion implantation for forming a potential pocket is facilitated.

It is desirable that the gate electrode be square or rectangular and have a relatively small area from the viewpoint of reducing the size of pixels. In this embodiment, even if the area of the gate electrode is reduced and the manufacturing variation of the MOS transistor for each pixel is increased, the problem can be solved by performing the noise removing operation (described later).

Next, the timing chart of FIG.
The operation will be described with reference to a potential diagram in the direction from the surface of the photodiode and the MOS transistor of the pixel to the substrate in FIG.

First, at time T0, VDD and VSE of the pixel portion
By setting L to the highest potential VH (power supply voltage), the photodiode and the charge amplification MOS transistor are reset. In this state, the potential of the photodiode and the MOS transistor from the semiconductor surface toward the substrate becomes a forward bias state as shown in FIGS. 4 and 5, respectively, and the charges (holes) accumulated in the well region Is completely discharged to the substrate. By completely depleting the well, kTC noise due to reset can be prevented.

From time T1 after the end of the reset, an optical signal accumulation period starts. At time T1, VDD is at a middle level (VM) and VSEL is at a low level (VL). At this time,
As shown in FIGS. 6 and 7, in the wells of the photodiode and the MOS transistor, a potential barrier is formed between the well and the n-type semiconductor layer, so that photocarriers (holes) can be accumulated. The holes generated in the photodiode are transferred to the potential pocket in the well of the MOS transistor by the potential gradient and accumulated.

At time T2 when an arbitrary accumulation period ends, the operation shifts to a read operation from the pixel to the memory capacity. FIG. 8 shows the potential distribution of the MOS transistor of the pixel at this time. At time T2, by turning on ΦCTS, the optical signal containing the FPN component of the MOS transistor of the pixel is
Write to CTS. Then, at time T3, VDD and VS again
By setting EL to a high level, a complete depletion reset of the wells of the photodiode and the MOS transistor is performed. Immediately thereafter, VDD and VSEL are returned to the middle level, and at time T4, ΦCTN is turned ON, so that only the FPN component of the MOS transistor of the pixel is written into the capacitor CTN.

After reading the optical signal and the dark signal into the memory capacity, the horizontal shift register is operated from time T6 to perform the differential output of the optical signal and the dark signal. At this time, the signal of only the optical component (S) from which the noise component has been removed can be output from the differential amplifier by the operation of (S + FPN) -FPN.

In the actual driving of the area sensor, the time
The reset immediately after reading the optical signal at T3 is performed at time T0 shown earlier.
After the reset at time T3, the accumulation period starts. Therefore, resetting at time T0 is basically unnecessary in an actual operation.

By applying the noise elimination circuit and the driving method of the present embodiment to the pixel structure in which kTC noise does not occur due to the reset of the present embodiment, a high S / N miniaturized C is obtained.
MOS sensors become possible. According to this embodiment, a high-sensitivity solid-state imaging device from which RN and FPN have been removed has been realized. In the present embodiment, the same driving method can be applied to a solid-state imaging device in which reset noise does not occur in the pixel portion, for example, CMD, BCMD, FGA, or the like.

(Embodiment 2) FIG. 9 is a schematic circuit diagram of a second embodiment of the present invention. This embodiment is an embodiment in which a charge slice type noise elimination circuit is used.
The configuration of the pixel is the same as that of the first embodiment.

FIG. 10 shows a timing chart of the present embodiment. In the conventional charge slice type noise elimination circuit, the S + N signal was read after the N signal was read.
This embodiment is characterized in that the driving method is to read out the N signal after reading out the S + N signal.

By applying the noise elimination circuit and the driving method of the present embodiment to the pixel structure in which kTC noise does not occur due to the reset of the present embodiment, a high S / N miniaturized C is obtained.
MOS sensors become possible. This embodiment also has a solid-state imaging device in which reset noise does not occur in the pixel portion, such as a CM
The same noise elimination circuit and driving method can be applied to D, BCMD, FGA, and the like.

(Embodiment 3) FIG. 11 is a sectional view of a pixel according to a third embodiment of the present invention. A feature of the present embodiment is that the potential pocket 2 is eliminated. Since a complicated manufacturing process is not required to form the potential pocket, further miniaturization is possible. Pixels of 2 μm size are also possible. However, since the generated photocharge is distributed over the entire well, there is a disadvantage that the sensitivity is reduced. Therefore, in fields where image quality is not a concern,
This pixel structure is effective when cost reduction is required. The noise removing circuit and the driving method can be applied to both the first and second embodiments.

According to the present embodiment, a further miniaturized CM
OS area sensor is now possible. (Embodiment 4) An imaging apparatus using the solid-state imaging device described in Embodiments 1 to 3 will be described with reference to FIG.

In FIG. 12, reference numeral 101 denotes a barrier which serves both as protection of the lens and as a main switch; 102, a lens for forming an optical image of a subject on the solid-state image sensor 104;
Reference numeral 03 denotes an aperture for varying the amount of light passing through the lens 102, reference numeral 104 denotes a solid-state imaging device for capturing a subject formed by the lens 102 as an image signal, and reference numeral 105 denotes an image signal output from the solid-state imaging device 104. An image signal processing circuit including a variable gain amplifier section for amplifying and a gain correction circuit section for correcting a gain value; and 106, an A / D converter for performing analog-digital conversion of an image signal output from the solid-state image sensor 104 , 107 are A / D converters 1
A signal processing unit 108 for performing various corrections on the image data output from the unit 06 and compressing the data;
04, an imaging signal processing circuit 105, an A / D converter 106,
A timing generation unit, which is a driving unit that outputs various timing signals, to a signal processing unit 107; an overall control / operation unit 109 that controls various operations and the entire still video camera;
Reference numeral 10 denotes a memory unit for temporarily storing image data, 1
11 is an interface unit for recording or reading on a recording medium, 112 is a detachable recording medium such as a semiconductor memory for recording or reading image data,
An interface unit 113 communicates with an external computer or the like.

Next, the operation of the still video camera at the time of photographing in the above configuration will be described.

When the barrier 101 is opened, the main power is turned on, the power of the control system is turned on, and the power of the imaging system circuit such as the A / D converter 106 is turned on.

Then, in order to control the amount of exposure, the overall control / arithmetic unit 109 opens the aperture 103, and the signal output from the solid-state imaging device 104 is converted by the A / D converter 106, and then the signal is processed. The data is input to the unit 107.

Based on the data, the exposure calculation is totally controlled.
The calculation is performed by the arithmetic unit 109.

The brightness is determined based on the result of the photometry, and the overall control / calculation unit 109 controls the aperture according to the result.

Next, based on the signal output from the solid-state imaging device 104, a high-frequency component is extracted, and the overall control / calculation unit 109 calculates the distance to the subject. Thereafter, the lens is driven to determine whether or not the lens is in focus. When it is determined that the lens is not focused, the lens is driven again to perform distance measurement.

Then, after the focus is confirmed, the main exposure starts.

When the exposure is completed, the image signal output from the solid-state imaging device 104 is A / D-converted by an A / D converter 106, passes through a signal processing unit 107, and is controlled by the overall control / arithmetic unit 10.
9 is written to the memory unit.

Thereafter, the data stored in the memory unit 110 is recorded on a removable recording medium 112 such as a semiconductor memory through a recording medium control I / F unit under the control of the overall control / arithmetic unit 109. Further, the image may be processed by directly inputting it to a computer or the like through the external I / F unit 113.

[0042]

As described above, according to the present invention,
Pixels can be miniaturized and high S / N ratio can be achieved.
Smaller imaging devices such as still video cameras, fewer parts,
Along with the cost reduction, the image quality of the reproduced image is improved, and the minimum illuminance is also improved.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram of a first embodiment of the present invention.

FIG. 2 is a sectional view of a pixel according to the first embodiment of the present invention.

FIG. 3 is a drive timing chart according to the first embodiment of the present invention.

FIG. 4 is a potential distribution diagram of the photodiode at the time of reset according to the first embodiment of the present invention.

FIG. 5 is a potential distribution diagram of a MOS transistor at the time of reset according to the first embodiment of the present invention.

FIG. 6 is a potential distribution diagram of the photodiode during accumulation according to the first embodiment of the present invention.

FIG. 7 is a potential distribution diagram of a MOS transistor at the time of accumulation according to the first embodiment of the present invention.

FIG. 8 is a potential distribution diagram of a MOS transistor at the time of reading according to the first embodiment of the present invention.

FIG. 9 is a schematic circuit diagram of a second embodiment of the present invention.

FIG. 10 is a drive timing chart according to the second embodiment of the present invention.

FIG. 11 is a sectional view of a pixel according to a third embodiment of the present invention.

FIG. 12 is a diagram illustrating a fourth embodiment of the present invention.

FIG. 13 is a schematic circuit diagram of a conventional example.

FIG. 14 is a sectional view of a pixel in a conventional example.

[Explanation of symbols]

Reference Signs List 1 P-type silicon substrate 2 P ⁺ diffusion layer 3 pMOS transistor 4 vertical output line 5 horizontal drive line 6 reset MOS transistor 7 capacitance 8 transfer MOS transistor 9 horizontal output line 10 transfer MOS transistor 11 buffer MOS Transistor 12 Preamplifier 13 Input terminal 14 Input terminal 15 Input terminal 16 Output terminal 17 n ^- region (substrate) 18 Silicon oxide film 19 P-type well 20 n ⁺ region 21 n ⁺ region 22 Horizontal drive line 23 Vertical output line 24 Contact hole 25 Interlayer insulating film 26 MOS transistor with capacity (well) 27 Power supply terminal 28 MOS transistor for resistive load 29 Input terminal 30 Light shielding film such as W or Al 31 Passivation film such as SiN or SiON

Claims (16)

[Claims] 1. A photoelectric charge that has been photoelectrically converted is accumulated in a floating well of an amplifying field-effect transistor, a signal corresponding to a change in potential of the floating well is output to an output line, and the floating well is depleted. A pixel having a plurality of pixels in a vertical direction and a horizontal direction for resetting a photoelectric charge;
Driving means for reading out the second signal from the pixel after the first signal is read out from the pixel and after the floating well is depleted to reset the photocharge. And a differential output unit that outputs a difference between the first signal and the second signal. 2. The imaging device according to claim 1, wherein the field-effect transistor outputs a signal corresponding to a change in the threshold value of the field-effect transistor due to a change in the potential of the floating well to an output line. apparatus. 3. The imaging apparatus according to claim 1, further comprising a line memory capable of storing signals for effective pixels in a horizontal direction. 4. The imaging device according to claim 1, wherein said line memory is a MOS capacitor. 5. The imaging device according to claim 1, wherein the field-effect transistor is formed in a first conductive type semiconductor layer opposite to the first conductive type semiconductor substrate.
A conductivity type well region, and a drain diffusion region and a source diffusion region of opposite conductivity types formed on the surface of the well region;
An imaging device comprising a gate electrode formed on a well region between the drain region and the source region via a gate oxide film, wherein the well region is independent for each pixel. 6. The imaging device according to claim 5, wherein a potential pocket for accumulating a photocharge is provided in a partial region of a well below a gate of the field-effect transistor. 7. The imaging device according to claim 6, wherein a potential pocket is formed by changing a concentration of a part of a well of the field effect transistor. 8. The imaging device according to claim 5, wherein the driving unit applies a pulse voltage to a gate of the field effect transistor to cause a forward bias state between the well and the substrate. The resetting is performed by completely discharging the accumulated charge to the substrate. 9. The imaging device according to claim 8, wherein the well has an impurity concentration at which the well is completely depleted at the time of reset. 10. The imaging device according to claim 1, wherein the driving unit applies a voltage to turn on the field effect transistor to a drain and a gate, and resets the depletion of the floating well. And applying a voltage to turn off the field effect transistor to the gate to accumulate photocharges, and then applying an intermediate level voltage to the gate of the field effect transistor to read out the first signal. After the first signal is read, a pulse voltage is applied to the drain and the gate of the field effect transistor to perform the depletion reset of the floating well. The second signal is read out by applying the voltage of the second signal to output the difference between the first signal and the second signal. Image apparatus. 11. The imaging device according to claim 10, wherein the drain voltage of the field-effect transistor is a pulse voltage having a high level during a reset period and an intermediate level during other periods. . 12. The imaging device according to claim 1, wherein the photoelectric conversion element that performs photoelectric conversion comprises:
A buried photodiode structure including a first conductivity type well region formed in a semiconductor layer of the opposite conductivity type of the first conductivity type semiconductor substrate, and an impurity diffusion region of the opposite conductivity type formed on a surface of the well region. An imaging apparatus characterized in that: 13. The solid-state imaging device according to claim 1, wherein a well region of a photoelectric conversion element that performs photoelectric conversion is connected to a well region of the field-effect transistor. An image pickup apparatus, wherein signal reading is performed by transferring a photocharge generated in an element to a well region of the field effect transistor. 14. A photoelectric conversion unit formed of a first semiconductor region of a first conductivity type and a second semiconductor region of a conductivity type opposite to the first semiconductor region formed on a surface of the semiconductor region. Providing a gate electrode on the first semiconductor region;
A field-effect transistor that outputs a signal corresponding to a threshold value change due to a potential change of the first semiconductor region to an output line, wherein the first semiconductor region has a higher concentration than the first semiconductor region. A pixel in which a third semiconductor region of the first conductivity type is formed in a vertical direction and a horizontal direction, and further, a first signal is read out from the pixel after accumulating photocharges in the first semiconductor region for a predetermined time; From the pixel to the first
Is read out, and after resetting the photocharge of the first semiconductor region, the second
An image pickup apparatus comprising: a driving unit that reads out a signal; and a differential output unit that outputs a difference between the first signal and the second signal. 15. The imaging device according to claim 1, wherein the imaging device is manufactured by a CMOS process. 16. The imaging apparatus according to claim 1, wherein a lens that forms an image of light on the pixel, and an AD conversion that converts a signal output from the difference output unit into a digital signal. An imaging apparatus comprising: a device; and a signal processing circuit that processes a signal from the AD converter.