JP2003324191A - Photoelectric conversion device and image pickup unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, since the concentration of a part brought into contact with a channel stop layer under a wiring layer is effectively decreased due to the continuity of an HIGH condition in the wiring layer in the neighborhood of a photodiode, the concentration of a small number of carriers is increased, and the small number of carriers are dispersed in the photodiode, and S/N is deteriorated as a result. <P>SOLUTION: This photoelectric conversion device is provided with a photoelectric conversion part, an element separation part formed between an element adjacent to the photoelectric conversion part and the photoelectric conversion part whose lower part is formed with a channel stop, and an amplification transistor for reading the charge of the photoelectric conversion part wherein a drain voltage in the reading operation of the amplification transistor is first potential. This photoelectric conversion device is provided with electric conductor wiring formed on the element separation part configuring a part of the gate of the amplification transistor, and a potential switching means for switching the potential of the electric conductor wiring between the first potential and second potential lower than the first potential. When the photoelectric conversion part is put into a charge storage state, the potential of the conductor wiring is set as the second potential by the potential switching means. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device and an amplification type solid-state imaging device and system using the photoelectric conversion device. The present invention relates to a digital camera, a video camera, a copying machine,
The present invention relates to an image pickup apparatus and system such as a facsimile.

[0002]

2. Description of the Related Art Many image sensors in which solid-state image pickup devices including photoelectric conversion elements are arranged one-dimensionally or two-dimensionally are mounted in digital cameras, video cameras, copying machines, facsimiles and the like. For the solid-state image sensor, for example, a CCD
There are image pickup devices and amplification type solid-state image pickup devices.

These image pickup devices tend to have a large number of pixels, and as the area of one pixel decreases, the photodiode area also tends to decrease. Therefore, it becomes necessary to handle a smaller amount of signal charge, and it becomes necessary to further reduce the leak current of the photodiode, which becomes a noise component.

FIG. 12 shows a circuit configuration example of the amplification type solid-state image pickup device.
Shown in. The amplification type solid-state imaging device has at least a photodiode in a unit pixel and a transistor for amplifying an optical signal accumulated in the photodiode.

FIG. 8 shows a sectional structure of a photodiode in a unit cell of a conventional amplification type MOS sensor. In the figure, 801 is, for example, an n-type semiconductor substrate, and 802 is
It is a P-type semiconductor layer, for example, a P-well layer, and forms a photodiode with the N-type semiconductor region 803.
Reference numeral 804 is an element isolation insulating film, 805 is a wiring layer,
6 is a P-type channel stop layer, which is an element isolation insulating film 8
It is provided under 04.

As shown in FIG. 8, the n-type layer forming the photodiode together with the p-type silicon substrate is formed in self-alignment with the LOCOS (Local Oxidization of Silicon) oxide film layer for element isolation. The structure is such that the area of the n-type layer corresponding to the area of the photodiode is increased to the limit. A channel stop layer 806 for improving the punch-through breakdown voltage between the source / drain region 807 of the adjacent MOS transistor and the N region 803 of the photodiode is formed under the element isolation insulating film 804. A wiring layer 805 of the transistor is formed on the LOCOS oxide film for element isolation.

[0007]

However, in FIG. 8, the potential of the wiring layer 805 of the transistor is HIGH (for example, +
5V), the effective concentration of the P-type channel stop layer 806 thereunder decreases, and the minority carrier concentration increases below 805. The minority carriers (electrons) diffuse into the photodiode, which causes a problem that the dark current of the photodiode increases.

FIGS. 9 and 10 show the plan view of FIG. 8 and its equivalent circuit, and the circuit configuration will be described.

FIG. 8 shows a cross section taken along the line AA 'of FIG. FIG. 9 is a view mainly showing the element isolation insulating film, the conductor layer, and the contact hole in order to prevent the drawing from being complicated.
Actually, the metal wiring layer and the like to be formed are omitted. In FIG. 9, 901 is a photodiode for photoelectric conversion, 902 is a reset transistor for resetting the photodiode 901 and the floating diffusion (FD) region 906, and 903 is a transfer MOS transistor for reading the signal charge of the photodiode 901. , 904 are source follower amplifiers for converting the read charges into voltages, which are connected to the FD region of 906. A row selection MOS transistor 905 connects the output of the source follower amplifier to the signal line.

Next, the circuit operation will be described with reference to FIGS. 10 and 11. In order to reset the photodiode 1001 in FIG. 10, the reset MOS transistor 1002 and the transfer MOS transistor 1003 are turned on, and then the transfer MOS transistor 1003 is turned off to reset the photodiode 1001. From this state, the photodiode enters the storage state. After the storage time ts has elapsed, the reset MOS transistor 1002 is turned off, the selection MOS transistor 1005 is turned on, and the source follower amplifier 1004 is activated, and the transfer MOS transistor 1003 is turned on.
The signal charge of 1 is read.

In the accumulation state, the FD area 1006 is Vdd
For example, the voltage of + 5V is applied in the HIGH state, the gate potentials of the MOS transistors 904 and 902 in FIG. 9 are in the HIGH state, and the potential of the wiring layer 805 in FIG. 8 is HI.
It is GH. At this time, in the lower part of the wiring layer 805, 80
When the P region of 2 has a potential of Vss, for example, 0 V, the P region of 806
The concentration of the portion of the mold channel stop layer in contact with 804 is effectively reduced, and the concentration of the minority carriers is increased as compared with the region 806 ′ where the wiring layer 805 is not in the upper portion. Therefore, the generated minority carriers diffuse into the photodiode 901 and deteriorate the S / N.

As a countermeasure against this, it is conceivable to increase the concentration of the P-type channel stop layer 806, but at that time, the junction breakdown voltage is lowered with respect to the N + + layer of the source drain of the adjacent 807, or the junction breakdown voltage There is a problem that the leak current increases.

It is also conceivable to increase the film thickness of the element isolation insulating film 804 formed by LOCOS, but in that case, the level difference of the wiring layer 805 increases, which makes it unsuitable for the formation of fine wiring and easily causes disconnection or short circuit. The problem arises. That is, there is a problem that noise increases due to an increase in dark current and S / N deteriorates.

[0014]

In order to solve the above-mentioned problems, the present invention forms a second semiconductor region of the second conductivity type in a first semiconductor region of the first conductivity type having a potential of Vs. The photoelectric conversion part obtained by performing the above, an element isolation insulating film formed between the photoelectric conversion part and the adjacent element, and the concentration of the first semiconductor region located below the element isolation insulating film. Higher third conductivity type semiconductor region, at least one or more conductor layers formed on a part of the element isolation insulating film, and the second read out charge of the photoelectric conversion unit. A source follower amplifier formed in a semiconductor region, and a photoelectric conversion device in which the drain voltage during a read operation of the source follower amplifier is Vd, wherein the photoelectric conversion unit is in an accumulation state, the All potentials of the conductor layer differ from Vd Characterized in that in the potential between Li Kui Vs and Vd. Further, when the photoelectric conversion unit is in the storage state, all the potentials of the conductor layer may be between Vs and (Vs + Vd) / 2, or Vs and (Vs + Vd) / 4. It may be a potential between. Further, a plurality of the photoelectric conversion devices of the present invention may be arranged one-dimensionally or two-dimensionally.

In order to solve the above-mentioned problems, the present invention further provides a photoelectric conversion section and a first one for transferring charges generated from the photoelectric conversion section in which one electrode of the photoelectric conversion section and a source electrode are connected. MOS transistor, a second MOS transistor for amplifying charges generated from the photoelectric conversion unit, and a third MO transistor for resetting the photoelectric conversion unit.
A pixel circuit having an S-transistor, comprising:
The drain electrode of the MOS transistor of
Connected to the gate electrode of the S transistor and the source electrode of the third MOS transistor via a first wiring,
A photoelectric conversion device in which a plurality of pixel circuits in which the drain electrode of the third MOS transistor is connected to the second wiring is arranged, and the potentials of the first and second wirings are set to a plurality of potentials. It has a potential switching means for switching to. Here, the potential switching means may be provided for each of the plurality of arranged pixels, or for each row, or for each column. Further, the second potential when the second MOS transistor is performing the amplifying operation of the first potential of the first wiring and the charge of the photoelectric conversion unit when the photoelectric conversion unit is in the storage state. Different from the second potential, which is the drain potential of the MOS transistor, and the first potential may be a potential between the second potential and the third potential. The gate potential of the third MOS transistor may be the third potential when the photoelectric conversion unit is in the storage state.

Needless to say, the above problem can be solved in an image pickup apparatus having the photoelectric conversion device of the present invention.

[0017]

DETAILED DESCRIPTION OF THE INVENTION Referring to the drawings,
A photoelectric conversion device according to the present invention will be described.

[First Embodiment] FIGS. 1 and 2 show a circuit diagram and an operation timing diagram of a first embodiment of a photoelectric conversion device of the present invention. In FIG. 1, 100 is a circuit of one pixel. In the one pixel circuit 100, 101 is a photodiode for photoelectric conversion, 102 is a photodiode 101 and a floating diffusion (F
D) A reset transistor for resetting the region 106, 103 is a transfer MOS transistor for reading the signal charge of the photodiode 101, 104 is a source follower amplifier for converting the read charge into a voltage, and is connected to the FD region of 106 Has been done. Reference numeral 105 denotes a row selection MOS transistor, which connects the output of the source follower amplifier to the signal line. Further, switches 107 and 108 for switching the voltage between Vdd (for example, 5V) and VL (for example, 1V) are connected to the drains of the reset transistor 102 and the source follower amplifier 104. In addition, in the one-pixel circuit 100 according to the present embodiment, 101
All the MOS transistors Nos. To 105 are nMOS transistors, which are formed in a P-type well, and the potential Vss of the P-well is fixed to the potential of 0V, for example. Further, 109 is an inverter.

Next, the circuit operation will be described with reference to FIG. The operation of resetting the photodiode 101 will be described.
First, the reset MOS transistors 102 and Φ are turned on to reset the FD region 106 (t1). Next transfer MOS
The transistor 103 is turned on and the photodiode is reset (t2). After that, transfer MOS transistor 103
It is turned off and the photodiode 101 is held in a reset state (t3). Φ is turned off, that is, 107 is OF
By turning on F and 108, the FD area 106 is set to the level of VL (t4). Further, by setting Φres to the LOW state, the storage state (t5) is set. The row selection MOS transistor 105 remains in the OFF state from t1 to t4.

By this operation, all the wiring layers adjacent to the photodiode of FIG. 9 are fixed at a potential lower than Vdd, so that the wiring layer 8 is fixed as compared with the case where the wiring layer is fixed at Vdd.
The minority carrier density in the lower part of 05 can be reduced.

The voltage of VL is effective if it is lower than Vdd, more preferably Vdd / 2 or less, and further preferably Vss to Vdd / 4.

Next, the read operation will be described. After the accumulation time ts has elapsed, the reset MOS transistors 102 and 107 are turned on and 108 are turned off, and
6 is raised to the potential of Vdd (t6). The source follower amplifier 10 is turned on by turning on the selection MOS transistor 105.
4 is activated (t7), and the transfer MOS transistor 103 is turned on (t8).
The signal charge of 1 is read. Next, the transfer MOS transistor 103 is turned off (t9), and the selection MOS transistor 105 and Φ
Turn off (t10) to return to the initial state.

As described above, the drain voltage of the reset MOS transistor 102, the floating diffusion region and the source follower amplifier 104 is set to Vdd during the accumulation time.
By switching to a lower voltage, minority carriers diffused and injected into the photodiode can be suppressed, and a solid-state imaging device with high S / N can be created.

Although FIG. 1 shows an example of one pixel, it may be formed in a one-dimensional or two-dimensional array. At this time, one voltage switching means 107, 108 and 109 may be provided for all pixels. In this case, the operation from the reset of the photodiode 101 to the lapse of the storage time ts is executed simultaneously for all pixels.

[Second Embodiment] FIGS. 3 and 4 show a second embodiment of the photoelectric conversion device of the present invention. In this embodiment, the row selection MOS transistor 105 in the first embodiment is eliminated by providing a Vdd and VL changeover switch for each row, and the photodiode area can be increased accordingly. Although an example in which pixels are arranged in a 2 × 2 array is shown in the drawing, it is needless to say that the arrangement is not limited to this, and it can be arranged two-dimensionally with an arbitrary number of rows and columns. As shown in the timing chart of FIG. 4, the basic operation is the same as that of the first embodiment, and after performing the reset operation of the photodiode in the period of tr, and after the elapse of the accumulation time ts, for one row The read operation is executed within the period of tu. At this time, when the source follower amplifier 304 of the selected row is operated, Φrn of the selected row is turned ON to serve as a selection MOS transistor. Therefore,
In the present embodiment, the reset and accumulation operations in the pixel circuit are executed in units of one row.

Also in this embodiment, as is clear from the timing chart, the reset MOS transistor 3 is activated during the accumulation time.
02. By controlling the voltage of the floating diffusion region and the drain of the source follower amplifier 304 from Vdd to a lower voltage, the minority carriers diffused and injected into the photodiode are suppressed, and a solid-state imaging device with high S / N is created. You can

[Third Embodiment] FIGS. 5 and 6 show a third embodiment of the photoelectric conversion device of the present invention. The present embodiment shows a configuration in which the potential of the FD region from the vertical output line 507 is set to a voltage lower than Vdd.

In FIG. 5, 501 is a photodiode for photoelectric conversion, and 502 is a photodiode 501.
And floating diffusion (FD) area 50
6 is a reset transistor for resetting 6, and its drain is connected to the signal output line 507. Fifty
Reference numeral 3 is a transfer MOS transistor for reading the signal charge of the photodiode 501, 504 is a source follower amplifier for converting the read charge into a voltage, and its gate electrode is connected to the FD region of 506 and its drain is Vdd. It is fixed to.

Further, the signal line 507 is the changeover switch 5
08,509 connected to the current source 51
Reference numerals 0 and 509 denote switches 511 and 5 respectively for the reset voltage Vres of the photodiode and the storage voltage VL.
It is connected via 12. Further, 513 and 514 are inverters. Further, the vertical output line 507 is connected with a capacitor 515 that temporarily holds the charge of the photodiode via a switch 516.

Next, the circuit operation will be described with reference to FIG. The n-th photodiode 50 in the reset period tr
The operation of resetting 1 will be described. When Φvr is LOW, the switch 509 is turned ON, Φcresn and Φc are set to HIGH, and the Vres voltage is reset in the FD region 506 via the signal line 507 and the reset MOS transistor 502. Next, the transfer MOS transistor 503 is turned on to reset the photodiode. After that, the transfer MOS transistor 503 is turned off and the photodiode 501 is held in a reset state. Further, Φc is set to LOW, the potential of the signal line and the FD region are set to VL potential, and then Φcresn is set to LOW to close the reset MOS transistor 502, and the potential of the FD region of 506 is held at VL to be in an accumulation state. N with similar operation
+ Resets the 1st pixel.

Further, the voltage of Vres may be Vdd as long as it can reset the photodiode. Also, VL is V
It should be lower than dd, preferably Vss to Vdd / 2, more preferably Vss to Vdd / 4.

Next, the read operation will be described. Accumulation time t
After elapse of s, first, Φc is set to the HIGH state, the potential of the signal line 507 is raised to the voltage of Vres, and then Φcresn
To HIGH, reset MOS transistor 502 to ON, F
The D area 506 is set to Vres. Then return Φcresn to LOW F
After fixing the D region 506 with Vres, set Φvr to HIGH and operate the current source 510 to set the source follower amplifier 504.
Turn it on. Next, Φctxn is set to HIGH and the transfer MOS transistor 103 is turned on to read the signal charge of the photodiode 201, and then Φctxn is set to LOW.

In this state, Φct is set to HIGH, and the output of the source follower amplifier is written in the holding capacitor 515 via the switch 516. Then set φCt to LOW. Next, Φvr and Φc are set to LOW, the vertical signal line is set to the potential of VL again, and then Φcresn is set to HIGH so that the FD region 506 is also set to the potential of VL, and Φcresn is set to LOW to terminate the read operation and the initial state. Return to.

Such a read operation is performed for one pixel (pixels for one row in the case of array arrangement) in the tu period, and the same operation is performed for the reading of the (n + 1) th pixel. Since each signal line has a switch for switching between Vdd and VL, the row selection MOS transistor 1 of the first embodiment
No. 05 can be eliminated and the photodiode area can be increased accordingly. In the drawing, an example is shown in which pixels are arranged in a 1 × 2 array, but it is needless to say that they are not limited to this and can be arranged two-dimensionally with an arbitrary number of rows and columns.

Also in this embodiment, as is clear from the timing chart, the reset MOS transistor during the accumulation time,
By switching the voltage of the drain of the source follower amplifier from Vdd to a lower voltage, the minority carriers diffused and injected into the photodiode are suppressed, and the S / N ratio is reduced.
It is possible to create a solid-state image sensor with high efficiency.

[Fourth Embodiment] The fourth embodiment of the present invention relates to an image pickup apparatus using the photoelectric conversion device described in the first to third embodiments. Figure 7
It is a block diagram of the system of the imaging device comprised using the photoelectric conversion apparatus of each embodiment mentioned above. This image pickup apparatus is provided with a barrier 70 that doubles as a lens protector and a main switch.
1. A lens 702 for forming an optical image of a subject on a solid-state image sensor 704, a diaphragm 703 for varying the amount of light passing through the lens 702, and a solid-state image sensor for capturing the subject imaged by the lens 702 as an image signal. 704 (corresponding to the photoelectric conversion device described in each of the above embodiments), an image pickup signal processing circuit 705 that performs various corrections, clamps, and other processing on an image signal output from the solid-state image pickup element 704,
An A / D converter 706 that performs analog-digital conversion of an image signal output from the solid-state imaging device 704, and a signal processing unit that performs various corrections on image data output from the A / D converter 706 and compresses the data. 707, a solid-state imaging device 704, an imaging signal processing circuit 705, an A / D converter 706, and a timing generation unit 708 that outputs various timing signals to the signal processing unit 707. In addition, 7
Each of the circuits 05 to 708 may be formed on the same chip as the solid-state image sensor 704.

An overall control / arithmetic unit 709 for controlling various arithmetic operations and the entire still video camera, a memory unit 710 for temporarily storing image data, and a recording medium control interface for recording or reading on a recording medium. Unit 711, removable recording medium 712 such as semiconductor memory for recording or reading image data, external interface (I) for communicating with an external computer or the like.
The / F) unit 713 constitutes the solid-state imaging system.

Next, the operation of FIG. 7 will be described. When the barrier 701 is opened, the main power source is turned on, then the control system power source is turned on, and further the image pickup system circuit such as the A / D converter 706 is turned on. Then, in order to control the exposure amount, the overall control / calculation unit 709
Opens the diaphragm 703, and the signal output from the solid-state imaging device 704 passes through the imaging signal processing circuit 705 and A
It is output to the / D converter 706. A / D converter 706
Outputs the signal to the signal processing unit 707 after A / D converting the signal. The signal processing unit 707 causes the overall control / calculation unit 709 to perform exposure calculation based on the data.

The brightness is determined based on the result of the photometry, and the overall control / calculation unit 709 controls the diaphragm according to the result. Next, based on the signal output from the solid-state image sensor 704, a high frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 709. After that, the lens 702 is driven to determine whether or not focus is achieved. When it is determined that focus is not achieved, the lens 702 is driven again to perform distance measurement.

Then, after the focus is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state image sensor 704 is corrected in the image signal processing circuit 705, further A / D converted by the A / D converter 706, and passed through the signal processing unit 707 to control the entire system. It is stored in the memory unit 710 by the calculation 709. After that, the memory unit 71
The data stored in 0 is recorded on the removable recording medium 712 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 709. Also external I /
An image may be processed by directly inputting it to a computer or the like through the F section 713.

[0041]

As described above, according to the present invention, it is possible to provide a photoelectric conversion device and a photographing device which can reduce the leak current of the photodiode and have a high S / N.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a photoelectric conversion device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing control timing of the photoelectric conversion device corresponding to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a photoelectric conversion device corresponding to a second embodiment of the present invention.

FIG. 4 is a diagram showing a control timing of a photoelectric conversion device corresponding to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a photoelectric conversion device corresponding to a third embodiment of the present invention.

FIG. 6 is a diagram showing a control timing of a photoelectric conversion device corresponding to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of a system of an image pickup apparatus corresponding to a fourth embodiment of the present invention.

FIG. 8 is a cross-sectional view of a conventional photoelectric conversion device.

FIG. 9 is a plan view of a conventional photoelectric conversion device.

FIG. 10 is a diagram showing a configuration of a 1-pixel circuit of a conventional photoelectric conversion device.

FIG. 11 is a diagram showing a control timing of a conventional photoelectric conversion device.

FIG. 12 is a diagram showing a circuit configuration example of an amplification type solid-state imaging device.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4M118 AA05 AB01 BA14 CA03 CA09                       DB09 DD04 DD12 DD20 FA06                       FA08 FA26 FA28 FA33 FA42                 5C024 CX03 CX32 GX07 GY31 HX47                       HX50                 5C051 AA01 BA02 DB01 DB15 DB18                       DC03 DE17

Claims (11)

[Claims] 1. A photoelectric conversion part obtained by forming a second semiconductor region of a second conductivity type in a first semiconductor region of a first conductivity type having a potential of Vs, and the photoelectric conversion part. An element isolation insulating film formed between adjacent elements, a third semiconductor region of a first conductivity type having a concentration higher than that of the first semiconductor region located under the element isolation insulating film, and At least one conductor layer formed on a part of the element isolation insulating film, and a source follower amplifier formed in the second semiconductor region for reading out charges of the photoelectric conversion unit, In the photoelectric conversion device in which the drain voltage during the read operation of the source follower amplifier is Vd, when the photoelectric conversion unit is in the storage state, all the potentials of the conductor layer are different from Vd and between Vs and Vd. Photoelectric transformation characterized by being at electric potential Apparatus. 2. The electric potential of all of the conductor layers is an electric potential between Vs and (Vs + Vd) / 2 when the photoelectric conversion unit is in the storage state. Photoelectric conversion device. 3. The electric potential of all of the conductor layers is an electric potential between Vs and (Vs + Vd) / 4 when the photoelectric conversion section is in the storage state. Photoelectric conversion device. 4. A photoelectric conversion device comprising a plurality of the photoelectric conversion devices according to claim 1 arranged in a one-dimensional form or a two-dimensional form. 5. A photoelectric conversion part, and a first MOS transistor for transferring charges generated from the photoelectric conversion part, in which one electrode of the photoelectric conversion part and a source electrode are connected,
A second MOS for amplifying charges generated from the photoelectric conversion unit
A pixel circuit having a transistor and a third MOS transistor for resetting the photoelectric conversion unit, wherein the drain electrode of the first MOS transistor is the gate electrode of the second MOS transistor and the third MOS transistor. A photoelectric conversion device in which a plurality of pixel circuits, each of which is connected to a source electrode of a MOS transistor through a first wiring and a drain electrode of the third MOS transistor is connected to a second wiring, are arranged. A photoelectric conversion device comprising a potential switching unit for switching the potentials of the first and second wirings to a plurality of potentials. 6. The photoelectric conversion device according to claim 5, wherein one potential switching unit is provided for each of the plurality of arranged pixels. 7. The photoelectric conversion device according to claim 5, wherein the potential switching unit is present in each row for the plurality of arranged pixels. 8. The photoelectric conversion device according to claim 5, wherein the potential switching unit is provided in each column for the plurality of arranged pixels. 9. A case where the second MOS transistor is performing an amplifying operation of the first electric potential of the first wiring and the electric charge of the photoelectric conversion unit when the photoelectric conversion unit is in the storage state. The second potential, which is a drain potential of the second MOS transistor, is different, and the first potential is a potential between the second potential and the third potential. Item 9. The photoelectric conversion device according to any one of items 5 to 8. 10. The gate potential of the third MOS transistor is equal to a third potential when the photoelectric conversion unit is in an accumulation state.
The photoelectric conversion device according to claim 9, wherein the photoelectric conversion device has a potential of. 11. The method according to any one of claims 1 to 10.
An image pickup device having the photoelectric conversion device according to the item 1.