JP3919243B2 - Photoelectric conversion device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a photoelectric conversion device, and more particularly to an amplification type photoelectric conversion device having a floating gate amplifier in a pixel.
[0002]
[Prior art]
Conventionally, photoelectric conversion elements can be arranged in one or two dimensions to obtain image signals, so they are used as image sensors, used in video cameras, copiers, facsimiles, etc. It is predicted that it will be used in a variety of directions with the arrival of. As an example of the amplification type photoelectric conversion device using this photoelectric conversion element, the photoelectric conversion photoelectric charge is effectively transferred and selected in the same process as the metal-oxide-semiconductor MOS structure as the photoelectric conversion element. It is desirable to be able to consistently configure active elements that can output. As an example of achieving such a structural example, there is a CMOS type sensor that is an amplification type photoelectric conversion device having a floating gate amplifier in a pixel. These devices are described in documents such as [Proceedings of the SPIE vol. 1952. Aerospace Science and Sending-Surveillance Sensors (1993)].
[0003]
FIG. 9A shows a circuit structure diagram of a pixel portion of this photoelectric conversion device. In the figure, 1 is a P-type well formed on a Si substrate, 2 is a depletion layer formed in the P-type well, 3 is a photogate supplied with a control pulse φPG, and 5 is supplied with a control pulse φTX. , A transfer gate of a MOS transistor for transferring photocharge accumulated under the photogate 3, an antiblooming gate (ABG) for preventing excessive accumulation of photocharge in the photogate, and 7 an antiblooming drain (ABD), 8 is a floating gate (FG), 9 is a source follower amplifier MOS transistor, 11 is a selection switch for selecting the pixel, 19 is a source follower load MOS, 31 is an element isolation gate, and 32 is a MOS switch for resetting the floating gate. It is.
[0004]
FIG. 9B is a schematic equivalent circuit diagram of the photoelectric conversion device. In the figure, 33 is a transfer MOS transistor controlled by the transfer gate 5 and 34 is an anti-blooming MOS transistor controlled by the anti-blooming gate (ABG) 6. Other reference numerals are the same as those in FIG.
[0005]
In this photoelectric conversion device, of the incident light from the target image, the electron charge generated under the photogate 3 is accumulated by the light transmitted through the photogate 3, and the high pulse to the transfer gate 5 causes A charge is transferred to the depletion layer, the potential change of the floating gate 8 is obtained by the source follower MOS transistor 9 constituting the source follower amplifier, and an output having a voltage gain of about 1 is obtained. 11 and 19 are turned on and output as VOUT.
[0006]
Since this photoelectric conversion device performs nondestructive reading, reading can be performed any number of times. In addition, since it can be manufactured with CMOS process compatibility, it is also characterized by low cost. Furthermore, since it amplifies pixel by pixel, a very sensitive sensor can be realized.
[0007]
[Problems to be solved by the invention]
However, in the conventional example, since the number of elements constituting one pixel is large, miniaturization has been difficult. Further, since a MOS switch is connected to the floating gate to reset V _DD , kTC noise is generated due to switching, and sensitivity is lowered due to an increase in parasitic capacitance.
[0008]
The object of the first invention according to the present application is to suppress reset noise and increase the sensitivity, and the object of the second invention is to miniaturize the photoelectric conversion device.
[0009]
[Means and Actions for Solving the Problems]
The present invention is characterized in that a floating gate amplifier is provided in a pixel portion, and signals are read out and reset by controlling the floating gate by capacitive coupling. For this reason, there is no need to provide a switch in the floating gate, so that reset noise does not occur and highly sensitive signal detection is possible.
[0010]
Further, since the electrode for controlling the floating gate is formed on the floating gate, miniaturization is possible.
[0011]
Specifically, in an XY address type amplifying type photoelectric conversion device having a plurality of photoelectric conversion elements, a charge follower amplifier floating gate is transferred to each XY address type pixel, and charge is transferred from the photoelectric conversion element to the bottom of the floating gate. An electrode for controlling the potential of the floating gate by capacitive coupling is provided on the floating gate, and the potential change of the floating gate is read by a source follower operation. It is characterized by that. The photoelectric conversion element is formed of a depletion layer controlled by a photogate. Further, the photoelectric conversion element is a pn photodiode. Further, the drain for draining charge and the control gate connect the drain to a power source, and supply a control pulse for making the control gate high in synchronization with making the control pulse for the electrode low. Features. The control pulse to the transfer gate is a middle level smaller than the supply level of the control pulse to the control gate.
[0012]
With the structure and configuration of such a photoelectric conversion device, a high pulse is supplied to the electrode controlled by capacitive coupling, and the depletion layer of the floating gate is deeply spread instantaneously to absorb the electron charge, and the depletion layer gradually corresponds to a predetermined potential. Return to depth. Thereafter, the electron charge in the depletion layer is output by a source follower operation.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings together with each example.
[0014]
(First embodiment)
FIG. 1 shows a pixel configuration diagram of a first embodiment according to the present invention. FIG. 2 shows a schematic circuit configuration diagram when the pixels are two-dimensionally arranged and used as an area sensor.
[0015]
1 and 2, 1 is a p-type well region formed on an n-type Si substrate, 2 is a depletion layer formed by an electric field of a photogate 3 to which a high voltage is supplied to a control pulse φPG, and 3 is thin Photo gate made of poly-Si, 4 is an insulating oxide film formed on the depletion layer gate 2, 5 is a transfer gate for forming a transfer MOS transistor, 6 is an anti-blooming gate for discharging excessive charges to prevent blooming, 7 Is an n ⁺ region fixed to the power source VDD, 8 is a floating gate of the source follower amplifier type MOS transistor 9, 10 is a control electrode for controlling the potential of the floating gate 8 and controlling a depletion layer region under the floating gate 8, 11 A switch MOS transistor 12 serving as a signal output selection switch is a vertical MOS signal that outputs a pixel signal in the vertical direction of the two-dimensional area sensor. Output line 13 is a horizontal drive line for driving the horizontal pixel signal of two-dimensional area sensor corresponding to the vertical output line 12.
[0016]
Reference numeral 15 denotes one pixel including the above elements, 16 denotes a vertical scanning circuit that outputs a timing signal for activating the horizontal drive line 13 of the two-dimensional area sensor, and 17 denotes an image from each vertical output line 12. A horizontal scanning circuit for supplying a timing signal for selectively outputting a signal to the horizontal output line 22, 18 is a switch of a transfer MOS transistor for transferring an image signal output to the vertical output line 12, 19 is a load for the source follower, and A load MOS transistor for resetting the vertical output line 12, 20 is a storage capacitor for temporarily storing the image signal of the vertical output line 12, and 21 is a horizontal transfer MOS switch for transferring to the horizontal output line 22 in accordance with the timing of the horizontal scanning circuit 17. , 22 are horizontal output lines for outputting image signals of vertical output lines in time series in accordance with the timing of the horizontal scanning circuit 17; An output amplifier for amplifying an image signal of the horizontal output line 22, 24 is a MOS transistor for the horizontal line reset for resetting the horizontal output line 22. Hereinafter, the operation of the photoelectric conversion device according to the present invention will be schematically described. Electron hole pairs are generated in the depletion layer 2 by the incident light hν that has passed through the photogate 3 having the poly-Si electrode structure, and the control pulse φPG is set to high to cause electrons to flow under the photogate 3. Accumulated at the Si interface in the depletion layer 2, holes are discharged to the p-type well. When the accumulation period ends, the transfer MOS switch is turned on, and the accumulated charge is transferred under the floating gate 8. When charge is transferred under the floating gate 8, the potential of the floating gate 8 changes due to capacitive coupling, and the change in potential is output to the outside by a source follower operation, thereby providing high sensitivity, non-destructive, and high linearity photoelectric conversion. Characteristics can be obtained.
[0017]
Next, the operation will be described in detail with reference to the timing chart of FIG. First, at time T0, the timing control φV1 is set to the high state by the vertical scanning circuit 16, and the pixels 15-11 to 15-13 of the horizontal line 13 are selected. FIG. 4A shows the potential distribution and the charge state at this time. At this time, the power supply VDD is supplied to the n ⁺ region 7, the control pulse φPG is set high, and the control pulse φTX is set low, so that the depletion layer 2 shown in FIG. 4A is formed. At time T1, the control pulse φR is set high, and a potential is applied to the floating gate 8 by capacitive coupling, the depletion layer 2 under the floating gate 8 is expanded, and electrons under the floating gate 8 are discharged to the power source VDD and reset. The state at this time is shown in FIG.
[0018]
At time T3, the control pulse φTX is set to the middle level and the control pulse φPG is set to the low level, so that the charges under the photogate 3 are completely transferred under the floating gate 8 (FIG. 4C). At this time, the control pulse φTX may be fixed at the middle level instead of the pulse operation as long as the charge can be completely transferred. When the charge under the photogate 3 is transferred, the potential of the floating gate 8 changes according to the number of charges. At time T ₄ , the potential change is output to the storage capacitor CT 20 by the source follower operation of the source follower MOS transistor 9 with the transfer control pulse φT set to high.
[0019]
At time T ₅ , the control pulse φPG is kept low and the control pulses φTX and φR are set to the low level, whereby the charge generated under the insulating oxide film 4 is discharged to the anti-blooming drain 7, thereby remaining residual charge. Is reset (FIG. 4D).
[0020]
At time T ₆ , the horizontal scanning circuit 17 is scanned and the timing pulses φh 1 to φh 3... Are set high, and the charges accumulated in the storage capacitor CT 20 are sequentially transferred to the respective pixels via the horizontal output line 22 and the output amplifier 23. Is output serially in time series.
[0021]
By sequentially scanning the above operation with the timing pulses φV1 to φV3... Of the vertical scanning circuit 16 being high, the electric charge of each pixel 15 is output for each horizontal line 13.
[0022]
The control pulse φABG supplied to the anti-blooming gate 6 may be at a middle level, but can be driven by a high / low binary pulse as well as other control pulses. In this case, at time T ₅ in FIG. 3, the control pulse φR is set to low and the control pulse φABG is set to high at the same time. The potential distribution and charge state in this case are shown in FIG. Since the charges under the photogate 3 are more easily discharged than when the control pulse φABG is fixed, the charge reset time can be shortened. Further, the same effect can be obtained when the control pulse φABG is set to the high level after the control pulse φR is set to the low level. Also, this operation is effective for HDTV sensors that require high speed.
[0023]
In the present invention, the potential of the floating gate 8 is capacitively coupled by the supply pulse of the control pulse φR, so that no reset noise is generated as in the prior art, so that highly sensitive signal detection is possible. Further, since a reset MOS transistor for the floating gate 8 is not necessary, it is advantageous for miniaturization.
[0024]
In this embodiment, a floating gate type CMOS sensor advantageous to high sensitivity, low noise, and miniaturization can be realized.
[0025]
(Second embodiment)
FIG. 5 shows a circuit configuration diagram of a second embodiment according to the present invention. This embodiment is characterized in that a noise storage capacitor CTN, transfer MOS transistors 28 and 29, and a differential amplifier 31 are provided in order to remove fixed pattern noise and I / f noise of the pixel amplifier.
[0026]
As the operation, at the time T2 before the signal reading at the time T3 during the timing shown in FIG. 3, the control pulse φTN is set high to read the dark output remaining on the vertical output line to the storage capacitor CTN27, and then at the time T6. In response to the timing pulse φh 1, the transfer MOS transistors 21 and 29 are turned on, the charges of the storage capacitors 20 and 27 are output to the horizontal output lines 22 and 30, and differentially amplified by the differential amplifier 31. Subsequently, image signals are sequentially output by scanning the timing pulse φh 2... From the horizontal scanning circuit 17.
[0027]
Thus, the bright output and dark output of the image signal itself are simultaneously read out as a depletion layer optical signal, and the storage capacitors CTS and CTN are differentially output in the horizontal output period to remove noise.
[0028]
Naturally, this noise removal is possible even if performed externally. In this embodiment, a floating gate amplifier type CMOS sensor from which fixed pattern noise is also removed is possible.
[0029]
(Third embodiment)
FIG. 6 shows a pixel configuration diagram of the third embodiment according to the present invention. Although the anti-blooming drain 7 is formed adjacent to the photogate 3 in the first and second embodiments, this embodiment is characterized in that it is formed adjacent to the floating gate 8.
[0030]
The operation of the present embodiment is the same as the timing shown in FIG. 3. At time T ₅ , the control pulse φTX and φR are set to low level and the control pulse φABG is set to high while the control pulse φPG remains low. By discharging the electron charge of the depletion layer generated under the insulating oxide film 4 to the anti-blooming drain 7, the residual generated charge in the depletion layer is reset.
[0031]
Also in this embodiment, the same anti-blooming effect as in the first embodiment can be obtained.
[0032]
(Fourth embodiment)
FIG. 7 shows a pixel configuration diagram of a fourth embodiment according to the present invention. This embodiment is characterized in that a pn junction photodiode 25 is used in the photoelectric conversion unit. Since light absorption by the photogate 3 is eliminated, sensitivity, particularly blue sensitivity, is improved.
[0033]
In this embodiment, the photoelectron charge accumulated in the pn junction photodiode 25 by the photon hν for a predetermined time is transferred to the source follower MOS transistor 9 by transferring the control pulse φR high and the control pulse φTX high to the floating gate 8. Is output. Further, the control pulse φABG is set to high and discharged to the anti-blooming drain 7 as in the third embodiment.
[0034]
In this embodiment, a floating gate type CMOS sensor with improved sensitivity can be realized.
[0035]
(5th Example)
FIG. 8 shows a pixel configuration diagram of a fifth embodiment according to the present invention. In this embodiment, a p ⁺ np photodiode is used for the photoelectric conversion portion. In the case of the present embodiment, since the p ⁺ layer 26 is formed at the interface of the photoelectric conversion unit, it is possible to suppress dark current from the interface. That is, in the conventional pn photodiode, since the concentration of the n layer is low, the semiconductor interface is depleted. Therefore, the defect (interface state) at the interface becomes the generation center of the dark current. Therefore, a p ⁺ high concentration layer is formed to prevent depletion of the interface. In the process of this configuration, one step of the p ⁺ layer forming process may be added to the conventional CMOS process. Thus, in the case of this structure, a signal having a good S / N can be obtained even for a long accumulation operation. Further, in this embodiment, a floating gate type CMOS sensor having a good S / N with suppressed dark current can be realized.
[0036]
【The invention's effect】
As described above, according to the present invention, a high S / N sensor with extremely small random noise can be realized by providing a floating gate amplifier for each pixel and controlling the potential of the floating gate by capacitive coupling.
[0037]
Further, miniaturization can be achieved as compared with the prior art, and miniaturization and cost reduction can be realized at the same time.
[0038]
Further, by providing the anti-blooming gate, it is possible to prevent blooming of the photoelectric conversion element and to reduce a part of the noise of the dark output.
[Brief description of the drawings]
FIG. 1 is a pixel configuration diagram of a first embodiment of the present invention.
FIG. 2 is an apparatus configuration diagram of the first embodiment of the present invention.
FIG. 3 is a drive timing chart of the first embodiment of the present invention.
FIG. 4 is an operation explanatory diagram of the first embodiment of the present invention.
FIG. 5 is an apparatus configuration diagram of a second embodiment of the present invention.
FIG. 6 is a pixel configuration diagram of a third embodiment of the present invention.
FIG. 7 is a pixel configuration diagram of a fourth embodiment of the present invention.
FIG. 8 is a pixel configuration diagram of a fifth embodiment of the present invention.
FIG. 9 is an apparatus configuration diagram of a conventional photoelectric conversion apparatus.
[Explanation of symbols]
1 p-type well 2 depletion layer 3 photogate 4 gate oxide film 5 transfer gate 6 anti-blooming gate 7 n ⁺ anti-blooming drain 8 floating gate 9 source follower amplifier MOS
DESCRIPTION OF SYMBOLS 10 Floating gate control electrode 11 Selection MOS switch 12 Vertical output line 13 Horizontal drive line 15 Pixel unit 16 Vertical scanning circuit 17 Horizontal scanning circuit 18 Transfer switch 19 Source follower load MOS
20 storage capacitor 21 horizontal transfer switch 22 horizontal output line 23 output amplifier 25 n-type diffusion layer 26 p ⁺ surface layer 27 element isolation gate 28 floating gate reset MOS

Claims (9)

In an XY address type amplifying photoelectric conversion device having a plurality of pixels ,
Each XY address type pixel includes a photoelectric conversion element , a floating gate of a source follower amplifier, a transfer gate that transfers charges from the photoelectric conversion element to the floating gate, a drain for draining charge, and a control gate. An electrode for changing the potential of the floating gate by capacitive coupling is provided on the floating gate, and the potential change of the floating gate is read out by a source follower operation.   The photoelectric conversion device according to claim 1, wherein the photoelectric conversion element includes a depletion layer controlled by a photogate.   The photoelectric conversion device according to claim 1, wherein the photoelectric conversion element is a pn photodiode.   2. The photoelectric conversion device according to claim 1, wherein the drain for draining charge and the control gate are connected to the power source, and the control gate has a high level in synchronization with the control pulse of the electrode being low. A photoelectric conversion device characterized in that a control pulse is supplied.   2. The photoelectric conversion device according to claim 1, wherein the control pulse to the transfer gate is a middle level smaller than a supply level of the control pulse to the control gate.   2. The photoelectric conversion device according to claim 1, wherein the charge discharging drain and the control gate are provided adjacent to the photogate.   2. The photoelectric conversion device according to claim 1, wherein the charge draining drain and the control gate are provided adjacent to the floating gate, and the control gate is set to high after the electrode is set to low level. Photoelectric conversion device. 8. The photoelectric conversion device according to claim 1, wherein the signal is read and reset by changing the potential of the floating gate by capacitive coupling by the electrode. 9. apparatus. 9. The photoelectric conversion device according to claim 1, wherein a thickness of a depletion layer in a semiconductor region under the floating gate is changed by the electrode.

Images