JP3311004B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device used for a video camera, an electronic still camera or the like, and more particularly to a solid-state image pickup device for reducing a leak current in a photoelectric conversion section.

[0002]

2. Description of the Related Art In recent years, as a device for capturing an image,
Various solid-state imaging devices are used in place of the imaging tube.
A conventional example of this type of solid-state imaging device will be briefly described below.

FIG. 18 is a sectional view of a unit pixel of an interline transfer type CCD image sensor. A p-type well 2 is formed on an n-type semiconductor substrate 1 and an n-type diffusion layer is provided therein.
And In this device, incident light is subjected to photoelectric conversion, and the obtained electrons are accumulated in the photodiode 3 for a certain period of time, and then the transfer channel 5 is turned on so that the CCD channel 4 is turned on.
Is read out. At this time, a reverse bias of 2 to 10 V is applied between the photodiode 3 and the p-type well 2.

FIG. 19 shows that n ⁺ FIG. 3 is a cross-sectional view of a unit pixel of an amplification type image sensor using a pn bipolar transistor. A p-type base layer 7 is provided on an n-type semiconductor substrate (collector layer) 6 and n ⁺ A mold emitter layer 8 is provided. In this device, incident light is photoelectrically converted and accumulated in the base layer 7 as holes. At the time of reading, first, a positive voltage is applied to the line selection gate 9, and then the current amplified from the emitter layer 8 is read.

FIG. 20 shows a state of potential distribution in the device shown in FIG. Of the two solid lines, the upper side indicates the conduction band, and the lower side indicates the full band. The upper two solid lines are band diagrams when signals are stored, and the lower two broken lines are band diagrams of addressed pixels. The reverse bias is applied to the p-type base layer 7 and the n-type substrate 6 both at the time of accumulation and at the time of addressing. In particular, at the time of accumulation, a stronger reverse bias is applied than at the time of addressing.

Here, the voltage-current characteristics of the pn junction are shown in FIG.
It is shown in FIG. Applying a positive voltage to the n-type layer is a reverse bias. When a negative voltage is applied to the n-type layer, a current flows because of a forward bias (region A). When a positive voltage of 0.6 V or more is applied, the current is substantially saturated and becomes constant (region B).
The area B is an area in which the imaging apparatus has been used up to now. The leak current (saturation current) Id is a so-called dark current, which varies from pixel to pixel, resulting in noise and a reduction in sensitivity.

On the other hand, when the reverse bias is 0.6 V or less, the leak current decreases (C region), and when the reverse bias is 0 V, the leak current naturally becomes zero. Although noise can be reduced if used in the C region, conventional devices do not operate in this region. This is because, as can be seen from FIG. 20, when the signal charge is read by turning on the gate, if the potential of the collector layer is not sufficiently high, the signal charge to be read to the emitter side also flows to the collector side. is there.

Here, in both of the structures shown in FIGS. 18 and 19, a reverse bias of 2 V or more is applied to the photoelectric conversion storage section. For this reason, a reverse current flows, and the variation becomes noise, and it has been difficult to realize a solid-state imaging device with high sensitivity.

[0009]

As described above, in the conventional solid-state imaging device, it is necessary to apply a reverse bias of 2 V or more to the photoelectric conversion unit, which is a factor that increases the dark current and lowers the sensitivity. Was.

The present invention has been made in view of the above circumstances, and an object thereof is to reduce a reverse bias voltage applied to a photoelectric conversion unit, to reduce dark current and improve sensitivity. An object of the present invention is to provide a solid-state imaging device that can be measured.

[0011]

The gist of the present invention resides in that the light receiving / accumulating portion is constituted by a bipolar transistor, and a signal is read out by controlling the collector potential of the bipolar transistor .

That is, according to the present invention, there is provided a light receiving and accumulating section arranged two-dimensionally in the X and Y directions on a semiconductor substrate, an X direction address circuit for selecting an X direction address of these light receiving and accumulating sections, In a solid-state imaging device including a Y-direction address circuit for selecting a Y-direction address of a storage unit, a light-receiving storage unit includes a collector layer of a conductivity type opposite to that of a substrate provided on a surface portion of the substrate, and a collector layer of the collector layer. the substrate and the same conductivity type base layer provided on the inside surface portion, formed by phototransistors consisting of the base layer substrate and the opposite conductivity type emitter layer provided on the inner surface of, and the light receiving storage portion In
Bias applied between base layer and collector layer
The voltage is set to 0.6 V or less during the light receiving accumulation period,
An X-direction address circuit is connected to the emitter layer, and a Y-direction address circuit is connected to the collector layer.

[0013]

Further, preferred embodiments of the present invention include the following. (1) A first vertical CCD is formed by a buried CCD channel and a transfer electrode thereabove, and a gate insulating film under all transfer electrodes of the first vertical CCD and a semiconductor substrate surface during integration and accumulation of signal charges. Accumulation of mobile charges of the opposite conductivity type to signal charges at the interface. (2) A drain is provided on the side or lower part of the photoelectric conversion
The signal charge is not discharged during the period when the vertical CCDs are integrating and accumulating the signal charges, and during the period when the signal charges are being transferred from the first vertical CCD to the second vertical CCD, they are obtained by the photoelectric conversion unit. Discharging all or part of the signal charge to the drain. (3) An extraction electrode electrically coupled to the impurity diffusion layer that constitutes the photoelectric conversion unit, a photoelectric conversion film that performs photoelectric conversion on the extraction electrode, and a voltage applied to the upper part of the photoelectric conversion film. And a transparent electrode that transmits light. (4) In addition to the configuration of (3), different voltages are applied to the transparent electrodes during a period when the first vertical CCD is integrating and accumulating signal charges and during a period when the second vertical CCD is transferring signal charges. Apply.

[0015]

According to the present invention, holes obtained by photoelectric conversion are accumulated in the base layer while a reverse bias is applied between the base layer and the core layer. By further increasing the potential of the collector layer and increasing the reverse bias,
A signal can be read from the emitter layer. That is, at the time of signal reading, a signal is read by applying a larger reverse bias than at the time of accumulation. In this case, the reverse bias in the accumulation state does not need to be increased unlike the conventional case . Soshi
The reverse bias in the accumulation state to 0.6V or less
Then , not only the dark current is reduced and the noise is reduced, but also the sensitivity can be increased.

The reason why the signal can be read out by changing the potential of the collector layer is that the collector layer is not formed by the substrate itself and the collector layer is made common to all pixels as in the related art.
This is because the collector layer is electrically separated from the substrate.

[0017]

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

FIG. 1 is a sectional view showing one pixel configuration of a solid-state imaging device according to a first embodiment of the present invention. On a p-type semiconductor substrate 10, an n-type collector layer 11, p ⁺ Mold base layer 12 and n ⁺ The mold emitter layers 13 are sequentially formed to form a phototransistor (bipolar transistor).
Then, the signal readout line 32 is connected to the emitter layer 13, and the address line 31 is connected to the collector layer 11. FIG. 2 shows a two-dimensional array of these sensors, which is configured as an area sensor.

In FIG. 2, the size of the pixel is 4 × 4, but this is for the sake of simplicity.
The number of pixels in the direction can be changed as appropriate. Generally, a video camera or the like forms hundreds of thousands of pixels.

The address lines 31 (31-1 to 31-4) coming out of the Y-direction address circuit 21 are connected to the n-type collector layer 11. n ⁺ The signal read lines 32 (32-1 to 32-4) connected to the type emitter layer 13 are output to the output lines 33 (33-1 to 33-3) via the MOS read transistors 23 (23-1 to 23-4).
-4) is connected. The gate of the read transistor 23 is controlled by the X-direction address circuit 22. In addition,
It is also possible to configure the read transistor 23 as bipolar. Next, the operation at the time of accumulation and at the time of reading in the device configured as described above will be described.

First, a reverse bias is applied between the base layer 12 and the collector layer 11 during accumulation. in this case,
As in the conventional device, holes obtained by photoelectric conversion are accumulated in the base layer 12.

At the time of signal reading, the Y-direction address circuit 2
1 supplies a high-level voltage to the address line 31-1 and a low-level voltage to the other address lines 31-2, 31-3, and 31-4 to read out pixel-system signals on the first line. I do. Then, in this state, the X-direction address circuit 22
, A read pulse is read from transistors 23-1 and 23-2.
3-2, 23-3, and 23-4 have “high, low, low, low”, “low, high, low, low”, “low, low,
After sequentially applying voltages of “high, low” and “low, low, low, high” to sequentially read signals from the left pixel of the first line, the signal read lines 23-1, 23-2, 23- The signal is read from the signal output line 33 through 3, 23-4.

Next, a "low, high, low, low" voltage is applied from the Y-direction address circuit 21 to the address lines 31-1, 31-2, 31-3, 31-4, and reading in the X direction is performed as described above. As described above, the signal of the second line is read. Similarly, "low, low, high,
"Low" is applied to read out the third line, and "Low, low, low, high" is applied to the address line 31 to read out the fourth line, whereby signals of all pixels are read out. .

FIG. 3 is a circuit diagram showing a signal storage and a signal readout.
FIG. The solid line indicates signal accumulation and the broken line indicates signal readout.
Is shown. The incident light is photoelectrically converted and p⁺ For the mold base layer 12
Stored as a hall. In the signal accumulation state, p⁺ Type
0.6 V or less between the source layer 12 and the n-type collector layer 11
Set to reverse bias. High level of collector layer 11
Then, electrons flow from the emitter layer 13 through the base layer 12.
As a result, a signal is read (broken line). At this time,
The holes in the source layer 12 recombine with the electrons and enter a reset state.
You.

As described above, in this embodiment, the collector layer 11 of the phototransistor serving as the photoelectric conversion storage section is
Therefore, signals can be sequentially read from each pixel by the voltage applied to the collector layer 11 because the pixels are separated from each other as a conductivity type opposite to that of the first embodiment. In this case, a higher voltage is applied to the collector layer 11 at the time of signal reading than at the time of signal accumulation, so that the reverse bias voltage between the base layer 12 and the collector layer 11 at the time of signal accumulation is lower than that at the time of signal reading.
It becomes When the reverse bias voltage is set to 0.6 V or less , the dark current Id can be reduced and the noise is reduced, so that a highly sensitive sensor can be configured. Further, the present device can be used in a forward bias state. In this case, the output can be suppressed with respect to strong light, so that a sensor having a wide dynamic range can be realized.

FIG. 4 is a sectional view showing one pixel configuration of the first embodiment of the present invention, and FIG. 5 is an equivalent circuit diagram thereof. This reference
The example basically consists of two bipolar transistors Q1,
Q2. Note that it is needless to say that the following description is also possible with a device in which the n-type and the p-type are exchanged.

Transistors are formed on a part of the surface layer of the n-type substrate 40.
N of Q2⁺ The emitter layer 41 is buried and formed.
N-type epitaxial growth layer 42 is formed on
You. An optical seed is provided on the surface of the n-type epitaxial growth layer 42.
Light incident through the opening of the shield layer 46 is photoelectrically converted and stored.
And the p-type emitter layer 43 of the transistor Q1
A p-type base layer 44 is formed. p-type base layer 44
Is formed with an n-type collector layer 45 of Q2.
You. Here, the n-type epitaxial growth layer 42
And the p-type base layer 44 of Q2 is the p-type base layer of Q1.
It is a mold collector layer.

When a read pulse is applied from the address line 31 to the n-type epitaxial layer 42 serving as the n-type base layer of Q1, the p-type emitter layer 43 of Q1 moves from the base layer 4 of Q2.
4, a signal current flows. At the same time, the signal current amplified by Q2 from the n-type emitter layer 41 of Q2 flows to the n-type collector layer 45, and is read from the signal line 32.

FIG. 6 is a sectional view showing one pixel configuration of the second embodiment of the present invention. This reference example corresponds to p2 of Q2 in FIG.
The base layer 44 surrounds the p-type emitter layer 43 of Q1, and the n-type layer 48 therebetween is the base layer of Q1. FIG. 7 shows an equivalent circuit diagram thereof. The difference from FIG. 5 is that the base of Q1 and the emitter of Q2 are separated,
Q1 and Q2 can be independently biased.

FIG. 8 is a sectional view showing one pixel configuration of the third embodiment of the present invention. In this reference example , the address line 3
A coupling gate 49 is provided between the base layers 1 and Q2 so that a reverse bias is applied between the n-type base layer 42 of Q1 and the p-type collector layer 44 of Q1 during addressing. Further, an n ⁺ type contact layer 52 for contact between the element isolation n ⁺ layer 51, the address line 31 and the base layer of Q1 is provided.

FIG. 9 is a sectional view showing a pixel structure of a fourth embodiment of the present invention. This reference example corresponds to p1 of Q1 in FIG.
An n + shield layer 53 is provided on the upper part of the
Generation of unnecessary charges is suppressed at the Si-SiO ₂ interface.

FIG. 10A is a cross-sectional view showing a main configuration of a solid-state imaging device according to a fifth embodiment of the present invention. n
A p-well 61 is formed on a p-type Si substrate 60, and a first n-type diffusion layer (photoelectric conversion unit) 6 is formed on a surface layer of the p-well 61.
2, a second n-type diffusion layer 63 and an n-type buried channel 64 of a vertical CCD are formed. Then, a transfer electrode 65 is formed on the buried channel 64. A vertical overflow drain structure 66 is formed below the buried channel 64.

With such a configuration, the first diffusion layer 62 corresponding to the photodiode for performing the photoelectric conversion has the vertical C
The buried channel 64 of the CD is electrically coupled via the second diffusion layer 63, and as shown in the potential diagram of FIG. 10B, the signal charge photoelectrically converted by the first diffusion layer 62 is It is transported through the second diffusion layer 63 without being stored therein into the buried channel 64 of the vertical CCD, where it is stored.

In this case, since no signal charges are accumulated in the first diffusion layer 62, the reverse bias voltage 67 can be set very small, and the leakage current can be reduced. Excess charges due to strong incident light are discharged to the substrate 60 by a vertical overflow drain structure 66 provided below the vertical CCD. This reference
In the example , a charge that is directly photoelectrically converted in the buried channel 64 of the vertical CCD through the transfer electrode 65 is also available,
The light shield electrode need not be provided.

In the above structure, since the leakage current of the buried channel 64 of the vertical CCD also becomes noise, it is necessary to reduce this. FIG. 11A shows the relationship between the voltage applied to the transfer electrode 65 and the leakage current generated in the buried channel 64. The leak current Id is drastically reduced at an applied voltage lower than VG '. FIG. 11B shows the potential of the buried channel 64 in the depth direction of the substrate. In a potential 68 to which a normal gate voltage is applied, a leakage current generated from an SiO ₂ / Si interface 69 is dominant. The gate voltage negative, VG 'potential 70 in SiO ₂ / Si interface and below becomes to 0V, and there is the hole are accumulated. In this state, the leakage current at the interface is suppressed, and the leakage current is drastically reduced. When accumulation is performed with the vertical CCD in this state, both the first diffusion layer 62 and the leakage current generated in the buried channel 64 of the vertical CCD are suppressed.

When signal charges are accumulated in the vertical CCD as described above, signal transfer cannot be performed during the accumulation period. Therefore, a configuration having a second vertical CCD as shown in FIG. 12 is appropriate. Specifically, the solid-state imaging device according to the present reference example includes a photoelectric conversion unit 71 arranged two-dimensionally in the X and Y directions on a semiconductor substrate, and is electrically coupled to the photoelectric conversion unit 71. A first vertical CCD 72 that integrates and accumulates the signal charges obtained in step (a) and transfers the signal charges in the vertical direction.
A second vertical CCD 7 electrically coupled to the CD 72 and vertically transferring signal charges from the first vertical CCD 72;
3 and electrically connected to the second vertical CCD 73,
The horizontal CCD 74 transfers the signal charges from the vertical CCD 73 in the horizontal direction, and the output amplifier 75 outputs the signal charges from the horizontal CCD 74.

Here, the feature of this embodiment is that, by adopting the configuration of FIG. 10 described above, instead of accumulating signal charges in the photoelectric conversion unit 71, the first vertical C
That is, accumulation of signal charges is performed by the CD 72.

The operation of the above device will be described with reference to the timing chart of FIG. (A) includes a vertical blanking period 81 and a horizontal blanking period 82, which are composite blanking pulses according to the television standard. (B) is a transfer pulse of the first vertical CCD 72. During a period 83 for accumulating signal charges, a low-level DC voltage is applied, and during the vertical blanking period, a second vertical CCD 72 is applied.
A high-speed pulse 84 for transfer is applied to 73. (C)
Is a pulse applied to the second vertical CCD 73, and is a high-speed transfer pulse 8 for receiving signal charges from the first vertical CCD 72.
5 and a line shift pulse 86 which is transferred to the horizontal CCD 74 line by line during the horizontal period.

Although the above configuration basically operates, the CCD image sensor is of a frame transfer type and has sensitivity even during a high-speed transfer pulse generation period, so that band-like noise (smear) is formed above and below a bright subject. Can occur.
The following is a reference example for suppressing this.

FIG. 14 is a sectional view showing a main part of a sixth embodiment of the present invention. The same parts as those in FIG. 10 are denoted by the same reference numerals, and detailed description thereof will be omitted. This reference
In the example , in addition to the configuration of FIG.
2, a vertical overflow drain structure 76 is also provided. By controlling the voltage of the substrate 60 and discharging the charges generated in the first diffusion layer 62 during the high-speed transfer period to the substrate 60, the sensitivity in the high-speed transfer period can be reduced as compared with the signal accumulation period, and the smear can be improved. it can.

[0042] One example of a drive pulse in the present embodiment FIG. 1
It is shown in FIG. (A), (b) and (c) are completely the same as FIG.
(D) is a pulse applied to the substrate 60. This pulse 87 is a sensitivity suppression pulse during the high-speed transfer period.

Next, a seventh reference example in which the configuration of FIG. 14 is applied to a stacked image sensor will be described. FIG. 1 is a cross-sectional view of a unit pixel of a configuration of FIG. 14 in which a photoelectric conversion film is formed on an upper portion and applied to a stacked image sensor.
6, shown in FIG.

FIG. 16 shows an insulating film 91 on the structure of FIG.
And an extraction electrode 92 electrically connected to the first diffusion layer 62, and a photoelectric conversion film 93 made of amorphous silicon, amorphous selenium, or the like is formed thereon.
And a transparent electrode 94 of ITO or the like.

FIG. 17 shows a case where the second diffusion layer 63 is not provided and the first diffusion layer 63 is provided.
Of the vertical CCD has no transfer electrode 65 between the diffusion layer 62 and the buried channel 64 of the vertical CCD. The signal charges in the first diffusion layer 62 are released into the p-type well 61 by diffusing and transporting the signal charges in the first diffusion layer 62 into the buried channel 64 by biasing the first diffusion layer 62 to 0 V or slightly forward. Diffusion layer 62 and buried channel 64 are electrically coupled. Reference numeral 95 denotes a diffusion blocking layer for preventing a part of the charges discharged into the p-type well 61 from flowing into the substrate 60.

In this structure, to prevent signal charges from flowing out of the first diffusion layer 62 to the buried channel layer 64 during the high-speed transfer period in order to suppress smear, a positive voltage is applied to the transparent electrode 94. What is necessary is just to make the 1st diffusion layer 62 reverse bias. The timing chart is exactly the same as that of FIG. 15, and the pulse 87 shown in FIG.
Is a pulse applied to. That is, the first diffusion layer 62 and the buried channel 64 are electrically coupled during the signal accumulation period, and the buried channel 64 and the first diffusion layer 62 are electrically separated during the high-speed transfer period.

Also in this case, by setting the bias voltage of the first diffusion layer 62 at about 0 V, the leak current can be reduced, and the noise due to the dark current and the sensitivity can be improved. Becomes Note that the present invention is not limited to the above-described embodiments, and can be implemented with various modifications without departing from the scope of the invention.

[0048]

As described above in detail , according to the present invention, the collector of the bipolar transistor constituting the light receiving / accumulating portion is formed electrically separated from the substrate, and the signal is read out by controlling the collector potential. Since it is performed, the reverse bias applied to the photoelectric conversion storage unit can be reduced, and the dark current can be reduced to achieve higher sensitivity.

[0049]

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing one pixel configuration of a solid-state imaging device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing an example in which pixels in the first embodiment are two-dimensionally arranged.

FIG. 3 is a band diagram showing energy states at the time of signal accumulation and at the time of signal reading;

FIG. 4 is a cross-sectional view illustrating one pixel configuration of the first reference example of the present invention;

FIG. 5 is an equivalent circuit diagram of the first reference example ,

FIG. 6 is a cross-sectional view illustrating one pixel configuration of a second reference example of the present invention;

FIG. 7 is an equivalent circuit diagram of a second reference example ,

FIG. 8 is a sectional view showing one pixel configuration of a third reference example of the present invention;

FIG. 9 is a cross-sectional view illustrating one pixel configuration of a fourth reference example of the present invention;

FIG. 10 is a diagram showing a main part configuration and a potential state of a fifth reference example of the present invention;

FIG. 11 is a diagram for explaining a leakage current suppression of a vertical CCD in a fifth reference example ;

FIG. 12 is a plan view showing the overall configuration of a fifth reference example ;

FIG. 13 is a diagram showing an example of a driving pulse in a fifth reference example ;

FIG. 14 is a sectional view showing a configuration of a main part of a sixth reference example of the present invention;

FIG. 15 is a diagram showing an example of a driving pulse in a sixth reference example ;

FIG. 16 is a sectional view showing an example of a stacked CCD image sensor according to a seventh reference example ;

FIG. 17 is a sectional view showing another example of the stacked CCD image sensor according to the seventh reference example ;

FIG. 18 is a cross-sectional view showing a unit pixel configuration of a conventional CCD image sensor.

FIG. 19 is a sectional view showing a unit pixel configuration of a conventional amplification type image sensor.

20 is a band diagram showing a state of a potential distribution in the device of FIG.

FIG. 21 is a characteristic diagram showing voltage-current characteristics of a pn junction.

[Explanation of symbols]

10 ... p-type semiconductor substrate, 11 ... n-type collector layer, 12 ...
p ⁺ -type base layer, 13... n ⁺ -type emitter layer, 21... Y-direction address circuit, 22.
-1 to 23-4) ... readout transistor, 31 (31-1 to 31-4)
... Address line, 32 (32-1 to 32-4) ... Signal readout line, 3
3 (33-1 to 33-4) ... output lines.

Claims (1)

(57) [Claims] 1. A light receiving and accumulating portion arranged two-dimensionally in a X and Y directions on a semiconductor substrate, an X direction address circuit for selecting an X direction address of the light receiving and accumulating portion, and the X direction address circuit. Solid-state imaging device, comprising: a plurality of read transistors arranged in the X direction, adjacent to the transistors; a signal read line connected to these transistors; and a Y-direction address circuit for selecting a Y-direction address of the light receiving / accumulating portion. Wherein the light receiving and accumulating portion is a collector layer of the opposite conductivity type to the substrate provided on the surface portion of the substrate, and a base layer of the same conductivity type as the substrate provided on the inner surface portion of the collector layer. a phototransistor comprising a substrate and the opposite conductivity type emitter layer provided on the inside surface of the base layer, the light receiving storage
Reverse bar applied between the base layer and the collector layer
The bias voltage is set to 0.6 V or less during the light receiving accumulation period.
The X-direction address circuit is connected to the gate of the read transistor, the source and drain of the read transistor are connected to the emitter layer of a phototransistor and the signal read line, respectively, and the Y-direction address circuit is A solid-state imaging device connected to a collector layer of a phototransistor.