JPH11214667A - Active type picture element detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to display energy quantity of optical energy quantum, by converting energy of optical energy quantum to an electronic signal. SOLUTION: Photons which have given an impact to a P-anode of a diode D1 420 obtain sufficient energy and generate electron-hole pairs, Holes are moved to the P-anode of the photodiode D1 420, and electrons are collected by a cathode of the photodiode D1 420 and transferred via a power source Vcc. The holes having positive charges are accumulated in the P-anode of the photodiode D1 420 and gradually increase potential. A row activating circuit is changed from a high potential to a low potential, and a P-MOS transistor M1 415 is made electrically continuous. Charges generated by photons L334 (image) are displayed with a potential of the P-anode, flow to a P-base of a transistor Q1 410, and form a base current IB1 417. Hence, the base current forms a signal current by the amplification of a transistor. After the signal current is detected, the row activating circuit returns to a low potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active pixel detector that represents the intensity of incident light by converting incident light into an electric signal in a circuit and a semiconductor device.
In particular, overcharge in circuits and semiconductor devices
The present invention relates to the problem of image blooming due to overflow and the elimination of image delay due to residual charges in the circuits and semiconductor devices.

[0002]

2. Description of the Related Art A conventional circuit has a two-dimensional photosensor array, and each photosensor includes an image element (pixel). Light energy emitted or reflected from an object bombards the photosensor array, and the light energy is converted into an electrical signal by a detector. The video circuit scans each detector to read out the signal, and the electric signal of the video is displayed through the processing of the external circuit. Charge-coupled device (CCD, charged
Couple device) cameras are the most commonly used single-chip imaging technology. The CCD is operated via electric charges generated in a potential well of a detector integrated in a semiconductor substrate, and the depth of the potential well is controlled by a potential of a gate electrode located on a surface of the semiconductor substrate, and a potential of the gate electrode is controlled. Is changed to move the electric charge to the detection point on the surface of the semiconductor substrate, and the electric charge is amplified to become an image electronic signal.

[0003] Modern MOS process technology has perfected the effect at video rate by allowing charge transfer in the CCD configuration. However, a very small portion of the collected charge is washed away in the surface movement, and the charge stored in each potential well moves and is detected every frame time. Generally, this time is on the order of 30-60 frams / sec. The problem with CCD technology is that the charge generated by the light shock is transferred directly before detection and amplification. Therefore,
The efficiency in this process goes to zero, and the gain of the device becomes less than one, limiting the amount of charge stored in each potential well. The minimum detectable charge value is the value that the sense amplifier can detect over the noise of the sense amplifier, and the maximum detectable charge value is substantially generated and can be generated from one well to another well. Is limited only to the charge value that can move to

In order to overcome the limitation of the CCD dynamic range, incident light detection using a phototransistor is performed. USP 5,260,592 (Mead et al.), USP 5,324,958 (Mead
ad et al.) and `` A High Resolution CMOS Imager With
Active Pixel Using Capacitively CoupledBiPolar Ope
ration (Chi et al.) Paper # 82 Proceeding of Inter
-nationalConference on VLSI technology, system and
Applications, Taipei, Taiwan, June 1997, etc. have high resolution images with simple configurations depicted in FIGS. 1a, 1b, and 1c. These pixel configurations conform to typical CMOS logic technology standards. It is also a process technique.

A P substrate 5 implanted with N impurities is placed in an N well 10
A field oxide 20 is grown on the surface of the semiconductor substrate to regulate the pixel area, and a P impurity is implanted into the P base 15 forming the phototransistor Q160 in the field oxide 20, A power source is connected to the N-well to make the collector of the phototransistor Q160. In addition, a thin layer of gate oxide is grown on the surface of
The second dielectric plate of the capacitor C65 is formed by forming the capacitor dielectric 30 of C65 and depositing and etching a polysilicon layer 35 on the P base 15. After the peripheral edge is reoxidized to form an oxide spacer, the emitter 25 of the phototransistor Q160 is defined by implanting N impurities,
15 is held floating and its potential is determined via the potential V _row of the coupling capacitor C65. The polysilicon layer is connected to the row activation voltage circuit V _row 62, the transfer of charges that row activation voltage circuit V _row 62 is the phototransistor Q160 and activated the phototransistor Q1 60 is integrated.

A second insulator, silicon dioxide, is deposited on the surface of the semiconductor substrate to form a dielectric 40, and a metal layer 45 is placed on the contact 50 together with the emitter 25 of the bipolar transistor Q160. Detector 70 for metal layer 45
The above process is obviously used in the fabrication of CMOS transistors. For example, polysilicon 35 is used for the gate electrode of a CMOS transistor, and the N
The implant can be used for the source / drain electrode area. Compared to the method of fabricating a CCD, the compatibility between bipolar pixels and CMOS transistors in fabrication is a significant advantage. Light energy quanta L1 105 due to external reflection or radiation bombard the active region 17 of the P base, and the collector-base junction 12 and the emitter-base junction
It is absorbed near 22 to generate electron-hole pairs. The electron-hole pairs are collected at the nearest pn junction and minority carriers are collected at the collector-base junction 12 or at the emitter-junction.
The base current is collected by the base junction 22 to form a base current, and the base current is multiplied by the current gain of the transistor to form a collector current. The emitter 25 of the transistor Q160
The signal current I _SC 100 is a photon 105 of the light energy quantum is the sum of the base current and the collector current generated when converted to electron-hole pairs. The signal current I _SC 10
0 is transmitted to the detection amplifier 70 under certain conditions.

The operation of the phototransistor pixel configuration will be described with reference to FIG. 1d. The row activation voltage circuit V _row 62 in the integration period 102 holds the predetermined potential, thereby forming a reverse bias of the emitter-base junction 22 of the transistor Q160. In this state, the photon 105 emits electrons and holes. The current generated when the pair is converted is stored in capacitor C65.
When reading the charge value generated during the integration period 102, the row activation voltage circuit V _row 62 sets the potential to a high level during the reading time 104, the P base potential _{rises due to} the capacitive coupling of V _row , and the emitter voltage increases. 25 is biased positively, and the charge of the capacitor C65 flows through the base 15 of the transistor Q160 to form an emitter current, that is, a signal current I _SC100 .

[0008] For other structures incorporating photodiodes and MOS transistors, see "Image Capture
Circuit in CMOS "E.Fossum, Paper # B1, Proceedings
of InternationalConferenceon VLSI-Technology, Syst
See ems, and Applications, Taipei, Taiwan, June1997. The passive pixel circuit includes a photodiode and a MOS pass transistor. The photodiode converts incident light into charges, and the charges pass through the MOS pass transistor and are transmitted to the charge integration amplifier. The active pixel circuit includes a photodiode, a MOS pass transistor, and a source tracking device (source fo) serving as a buffer amplifier of a charge integration amplifier.
llower) and MOS activated by reset signal
A transistor is incorporated in an active pixel circuit and used as an electronic shutter for resetting a photodiode.

The active bipolar pixel circuit shown in FIGS. 1a, 1b, and 1c has higher sensitivity, a simplified pixel layout, lower manufacturing costs, etc., as compared to the CMOS pixel circuit described by Chi. With benefits. However, bipolar active pixels suffer from defocus and image lag. The defocus phenomenon will be described below with reference to FIG. In the pixel array [Pixel A80-Pixel X85], when the pixel row A80 collects the charge generated by the light quantum L1 105 bombarding the photodiode Q1 60a, the row activation voltage circuit V _row is at a low level. The emitter-base junction of the photodiode Q160a is reverse-biased to collect charge on the capacitor C65a, and at this point another pixel row X85 is read to detect the charge level on the capacitor C65b.

If the energy of the photons impacting the pixel A80 is sufficiently large, the charge is transferred to the photodiode Q160.
The emitter-base junction of a is positively biased, the overflow current I _ofc 95 flows through the inter-column connection 90, and the current I _tot 11 detected by the detection amplifier becomes the overflow current I _ofc
95 and the signal current I _SC . Therefore, the read pixel (pixel X85) causes a defocus phenomenon of the image due to the luminance higher than the required luminance. FIG. 3 illustrates the cause of the video delay. In FIG. 3, the pixel X20 of the last frame is shown.
0 is read in the frame before the illustrated frame,
The row activation voltage circuit V _row goes from high to low 185 and the emitter reverse biases the P base by the coupling of capacitor C165.

Although the P base potentials of the pixels in the pixel row at the start of the video integration are different, when reading starts in the reading operation and V _row changes from a high level to a low level, the P base The amount of potential drop (ΔV _B ) at the time is ΔV _B = (pulse height) × (coupling ratio), and the coupling ratio (γ) of the capacitor is defined by γ = C / (C + _CBE + _CBC ) . _Where : C _BE is the base-emitter coupling capacitance of Q1 160,
C _BC is the base-collector coupling capacitance of Q 1 160.
Note that the potential of the P base is controlled by V _row and the coupling ratio (γ), and since the charge transfer from the capacitor C 165 is incomplete, the residual current 210
Generate

A second portion of the surplus current 210 is generated by the transistor Q remaining in the P base during the read operation.
1160 is the minority residual carrier charge of the injected electrons in the base-emitter coupling. The charge remaining on the P base flows with the current gain toward the emitter of transistor Q1 160, and in addition to the signal current 215 detected during the reading period, follows the moving or bright object, thereby causing the illusion of the image. Become. The residual charge is either recombination or P
Although the image disappears after a certain period of time due to the loss of the minority carrier in the pace, the image delay time may last several frames because the recombining lifetime of the minority carrier is about 100 ms. The lifetime killer which aims to shorten the recombination time by adding an impurity to the P base has a problem in that the leakage current between the couplings increases, which deteriorates the image sensitivity.

The photodetector disclosed in US Pat. No. 5,097,305 (Mead et al.) Includes a phototransistor and a capacitor coupled to the base of the phototransistor, and selectively connects a signal by connecting a pass transistor to an emitter of the phototransistor. The current and the sense amplifier are coupled. Also US
P 5,288,988 (Hashimo et al.) Describes a photodetector circuit similar to FIGS. 1a, 1b and 1c, in which a MOS transistor is coupled to a photo-conversion cell and the MOS transistor is activated to activate the phototransistor base. To eliminate the residual charge and prevent generation of residual current.

[0014]

SUMMARY OF THE INVENTION It is a primary object of the present invention to provide an active pixel detection cell capable of displaying the energy of a light energy quantum by converting the energy of the light energy quantum into an electronic signal. . It is a further object of the present invention to provide an active pixel detection cell that solves the problem of image defocus. Another object of the present invention is to
It is an object of the present invention to provide an active pixel detection cell which reduces the problem of image delay by reducing the residual charge.

[0015]

SUMMARY OF THE INVENTION An active pixel detector provided for the purpose of the present invention comprises a photodiode, a bipolar transistor and a MOS transistor. A cathode of the photodiode is connected to an anode at a voltage supply terminal of a power supply device, and photons bombard the anode to generate charges in the photodiode. In addition,
In order to eliminate the defocus of the image with the MOS transistor,
The MOS transistor has a drain electrode connected to the anode of a photodiode, a source electrode and a gate electrode, and connects the gate electrode to a detector control circuit;
By selectively activating or deactivating the MOS transistor, charge is prevented or allowed to flow to the MOS transistor. Further, the bipolar transistor amplifies the electric charge to generate an electronic signal. The collector of the bipolar transistor is connected to a power supply, the base is connected to the source electrode of the MOS transistor, and collects electric charge when the MOS transistor is activated. The emitter is connected to an external circuit so that an electronic signal can be output to the external circuit.

Note that the active pixel detector has a parasitic MOS transistor (parastic MOS transistor), has an anode of a photodiode as a drain electrode of the parasitic MOS transistor, and has a source electrode connected to a row in the active pixel detector array. Address the anode of the photodiode of the active detector in proximity to the active pixel detector. The gate electrode of the parasitic MOS transistor resets the anode potential of the photodiode at the same potential level in the row by turning on the parasitic MOS transistor. Removed from the pixel detector.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of an active pixel detector according to the present invention will be described below with reference to FIGS. 4a, 4b and 4c. The construction of the device starts with a P-substrate 305 of a typical silicon wafer. While masking the surface of the P board 305,
The N well 310 is formed by implanting N impurities, an insulating area or a field oxide 315 is grown to regulate the active pixel cell area, and the area of the active pixel sensor cell is photomasked to form the P anode of the photodiode D1 420. Form 330 A power supply V _CC is brought into contact with the N well to serve as a cathode of the photodiode D1 420, and a second area in the area of the active pixel sensor cell is photomasked to regulate the P base 320 area of the bipolar transistor Q1 420. After the P base 320 is formed by the implantation of the P impurity, the third area is masked in the area of the P base 320 and the N impurity is implanted to form the bipolar transistor Q1.
420 emitters 325 are formed. The N-well 310 is used for the collector of the bipolar transistor Q1 420, and the P base 32 of the bipolar transistor Q1 420 is used.
0 and the P anode 330 of the photodiode D1 420 are MOS
The source and collector electrodes of the transistor are formed, a gate oxide layer 340 is grown above the channel area 337 between the source electrode 320 and the drain electrode 330, and a polysilicon material 335 is deposited and etched on the gate oxide layer 340. The MOS transistor M1
Defining 315 gates.

An insulator is deposited on the surface of the semiconductor substrate to form a dielectric 350, and the contact 327 of the N ⁺ emitter 325 is
50 formed in the opening. A metal layer 355 is deposited to form an emitter 325 of the transistor M1 410 and the detection amplifier 42.
5 to form an external circuit of the active pixel sensor array. Also, a polysilicon material 335 forming the gate electrode of the MOS transistor M1 410 is supplied to the row activation circuit V.
Connect to _row 416 to form a detector control circuit. The process steps described above can also be used to fabricate CMOS transistors. For example, polysilicon material 33
5, the formation of the gate electrode of the CMOS transistor,
The N implant of emitter 325 can be used to form source / drain electrode areas. Compared with the CCD manufacturing process, the compatibility between the bipolar pixel and the CMOS transistor in manufacturing is a great advantage.

Referring to FIG. 4d, an active pixel sensor will now be described.
The operation principle of the cell will be described. P of diode D1 420
The light quantum L334 bombarding the anode is shown in FIGS. 1a, 1b and 1c.
Enough energy like the phototransistor Q160 described
Energy to generate an electron-hole pair,
1 The hole moves to the P anode of 420, and the electrons are
Collected on the cathode (Nfel 310) of Aether D1 420
Power supply V_CCIs transferred through. Positive hall
Is the P anode of the photodiode D1 420 as shown in the figure.
And the potential is sequentially increased. Row activation circuit V_row
415 changes from high potential to low potential and
The transistor M1 415 is made conductive, and the light quantum L334 (video)
Charge Q_S494 is the potential V of the P anode
_p-anodeAnd the P base of transistor Q1 410
320 and the base current I_B1Form 417. The bee
Current I_B1417 is amplified by transistor Q1410
Signal current I _SC412, and after detecting the signal current,
Activation circuit V_row416 recovers to the low potential 485. this
At the time, surplus charge is stored in the P base 320 of the photodiode D1 420.
Q496 remains, but the P base of photodiode D1 420
The switch 320 is reset to a predetermined potential by a reset operation described later.
set.

Referring to FIG. 5, the operation principle of the active pixel detector of the present invention for eliminating pixel image blur will be described below.
Pixel A 430 and pixel X 435 are the two active pixel detectors in the active pixel detector array,
And a common detection amplifier 426. The activation of the pixel A 430 is controlled by the row activation circuit V _rowa 440 being connected to the internal connection line Ro.
The pixel X 435 is controlled via the row activation circuit V
_rowx 445 controls via the internal connection line Rowx455. Row activation circuit V _rowa 450 goes to high potential 422 and pixel A 430 is within integration time 489. At this point, pixel X435
If the collected charge generated by the light quantum L2 470 impacting the photodiode D1420b is read out, the row activation circuit V _rowx
455 becomes the low potential 477 and the PMOS transistor M1 41
5b is turned on, and the signal current I _SC 412b is output from the emitter of the transistor Q1 410b of the pixel X435.

In the above case, no matter how intense the photons _hitting the photodiode D1 420a, there is no overflow current I _ofc 95 shown in FIG. 2 and the PMOS transistor M1 415a does not _operate.
No current flows through. It quickly on to squares the P anode potential by holes are integrated in the P anode by intense action of photons L1 465, since the photodiode to the positive bias trend, overflow current flowing out to the power supply V _CC connected to the cathode of the photodiode Because you do. Therefore, there is no extraneous part in the total current I _TOT 413, and the total current I _TOT 413 is composed of only the signal current I _SC , and an appropriate current can be input to the detection amplifier 425. The reset action will be described with reference to FIGS. 4a, 4b, 4c and 4d. A second polysilicon 360 is deposited on an insulator formed by growing a gate oxide layer, and the reset polysilicon 360 is connected to a reset circuit V _reset , and a low potential 48 is applied.
0 is reset polysilicon 360 by applying to the reset circuit V _{re The set,} reset all the P anode and the conductive parasitic MOS transistor formed by the active-type pixel detectors close to the same potential. The following figure shows the details of the parasitic MOS transistor and the reset action.
This is described in 6a, 6b and 6c.

FIGS. 6a, 6b and 6c show three active pixel detectors 500a, 500b, 500c on a row in an active pixel detector array in a row and column configuration. The PMOS transistor M1 515a of each of the active pixel detectors 500a, 500b, 500c,
The gate electrodes 505a, 505b, 505c of 515b, 515c are connected to a _row enable circuit V _row by a common row polysilicon 335, and the reset polysilicon 360 and each active pixel detector 50 are connected.
The reset polysilicon 360 of 0a, 500b, and 500c is interconnected and connected to a reset control circuit V _reset 535. The peripheral coupling area 520 is formed by implanting a P impurity into the semiconductor substrate 305 at the end of the row active pixel detector, and the peripheral coupling area 520 is connected to a bias power supply V _{P +} 330. The oxide layer 365 formed by growing the gate oxide layer is composed of the reset polysilicon layer 360 and the P anode 330
Isolate a, 330b, 330c.

Each P anode 330a, 330b, 330c is connected to the PMOS transistor M of each active pixel detector 500a, 500b, 500c.
1 If the bias of the reset circuit V _reset 530 is low potential, the drain / source electrodes of 515a, 515b, 515c
Each PMOS of each active pixel detector 500a, 500b, 500c
The transistors M1 515a, 515b, and 515c are turned on to reset the potentials of all the P anodes 330a, 330b, and 330c to the bias power supply V _{P +} 530 having the same potential as the peripheral coupling area.
By positioning the V _T implant 535 in the channel area of a parasitic MOS transistor P1 550, it sets the critical potential of the parasitic MOS transistor P1 550 to the desired value. The implant is an enhancement of the parasitic MOS transistor.
(enhancement) type or depletion type M
N impurity or P depending on whether the transistor is an OS transistor
Determined as impurities.

As described in the related art, the operation of the parasitic transistor P1 550 can partially eliminate the image delay by making the potentials of all the P anodes in the row equal to the peripheral coupling area of the bias potential V _{P +} 530. . As shown in FIGS. 4c and 4d, during the readout period, the image charge Q _S 494 flows to the P base to form a base current, and activates the bipolar transistor with the P base of the transistor Q1 410 being positively biased. , The base current formed by the image charge Q _S 494 is amplified to become the emitter current I _SC and the detection amplifier 42
5 and collected by the detection amplifier 425, that is, the amplified video charge Q _S 494,
This is used to display the amplitude of the light quantum L1 334 that has impacted the light. The fact that the anode area of the photodiode D1420 is set to be larger than the base of the bipolar transistor Q1410 means that the injected minority carrier (electrons injected from the emitter) is restricted to the base of the bipolar transistor Q1410. And a photodiode D1 for preventing backflow from the P-channel MOS transistor to the anode of the photodiode D1 420.
This is because the same voltage as the anode voltage of 420 is provided at the base of the bipolar transistor Q1410.

A pixel with corresponding PNP bipolar transistors and NMOS transistors can be easily completed by injecting the silicon material with the polarity reversed. Therefore, the operating bias can be similarly inverted. Although the preferred embodiments of the present invention have been described above, the description does not limit the present invention. Since a person skilled in the art can make various changes and modifications within the spirit and scope of the present invention, the scope of protection of the present invention is defined by the appended claims. Based on

[Brief description of the drawings]

FIG. 1a is a plan view of a conventional photosensor cell.

FIG. 1b is a sectional view of a semiconductor substrate of a conventional photosensor cell.

FIG. 1c is a circuit diagram of the conventional photosensor cell shown in FIGS. 1a and 1b.

FIG. 1d is a timing diagram of the conventional photosensor cell shown in FIGS. 1a and 1b.

FIG. 2 is a circuit diagram illustrating two photosensor array cells for explaining image blurring due to an overflow current according to the related art.

FIG. 3 is a circuit diagram of a photosensor array cell for explaining a video delay caused by an excess current according to the related art.

FIG. 4a is a plan view of an active pixel detector of the present invention.

FIG. 4b is a sectional view of a semiconductor substrate of the active pixel detector of the present invention.

FIG. 4c is a circuit diagram of the active pixel sensor cell of the present invention shown in FIGS. 4a and 4b.

FIG. 4d is a timing diagram of the active pixel sensor array cell of the present invention.

FIG. 5 is a circuit diagram showing two cells for explaining the elimination of overflow current of the active pixel sensor array cell of the present invention.

FIG. 6a shows the active pixel sensor array cell 3 of the present invention.
The top view of a cell device.

FIG. 6b: 3 of the active pixel sensor array cell of the present invention
Sectional drawing of a cell device.

FIG. 6c is a circuit diagram illustrating a photodiode reset operation for reducing image delay in the active pixel sensor array cell of the present invention.

Claims (20)

[Claims] 1. An active pixel detector for collecting energy of light energy quanta and converting the light energy quanta into an electronic signal, wherein a cathode connected to a power supply device and the light quantum bombard to generate electric charge. A photodiode having an anode, a drain electrode connected to the anode of the photodiode, and a source and a gate electrode connected to a detector control circuit, wherein the detector control circuit selectively activates or deactivates the transistor. A MOS transistor for preventing the defocus of an image by flowing the charge through the transistor by activating the transistor, a collector connected to the power supply device, and a base connected to the MOS transistor to collect the charge when active. Having an emitter connected to an external circuit to transfer the electronic signal to the external circuit. By amplifying the charge, active type pixel detectors, characterized in that it comprises a bipolar transient scan to generate the electronic signal. 2. In the detector manufactured on a semiconductor substrate, a first conductive impurity is injected into a surface of the semiconductor substrate, and a well of a second conductive impurity is formed in the surface of the semiconductor substrate. The active pixel detector according to claim 1, wherein the active pixel detector is formed as follows. 3. The cathode of the photodiode is formed in the well in the surface of the semiconductor substrate, and the anode is configured to inject the impurity of the first conductivity type in the well into a first area. 3. The image display device according to claim 2, wherein the anode is formed larger than the base of the bipolar transistor, and restrains minority carriers remaining in the base in the base to reduce image delay. An active pixel detector as described. 4. The collector of the bipolar transistor is formed in the well in the semiconductor substrate, and the base is formed by implanting the impurity of the first conductivity type in the well into a second area. 4. The active pixel detector according to claim 3, wherein the emitter is formed by implanting the second conductivity type impurity into the third area in the base. 5. The MOS transistor has the first area of the first conductivity type impurity at the drain electrode, and the source electrode of the MOS transistor has a second area of the first conductivity type impurity. 5. The active pixel detector according to claim 4, wherein said gate electrode forms a channel zone by growing a gate oxide layer at an intermediate portion between all of said source electrode and said drain electrode. 6. The semiconductor device according to claim 5, wherein the emitter is connected to an external circuit by a metal internal connection line deposited on the insulating layer on the surface of the semiconductor substrate, and is in contact with the emitter. An active pixel detector according to claim 1. 7. An anode of a photodiode of an active detector adjacent to a row active pixel detector in an active pixel detector array having an anode of the photodiode as a drain electrode, and a gate electrode of the photodiode. 7. The device according to claim 6, further comprising a parasitic MOS transistor that connects to a reset circuit and conducts, thereby resetting the potential of the anode of the photodiode to prevent image delay on the active pixel detector. Active pixel detector. 8. A pixel detecting device comprising: (a) supplying power to each of the active pixel detectors of the plurality of active pixel detectors arranged in rows and columns; A photodiode having a cathode connected to the device and an anode which generates charges upon impact of photons; a drain electrode connected to the anode of the photodiode for preventing image blurring generated in an image array; and a source electrode. And a MOS transistor having a gate electrode and a collector connected to a power supply device, the MOS
A bipolar transistor comprising a base and an emitter for collecting the electric charge when the MOS transistor is activated, wherein the bipolar transistor is connected to the respective gate electrodes of the MOS transistors in each row; By activating or deactivating each MOS transistor in each row, the charge is transferred to the MOS transistor.
(C) connected to the emitter of the bipolar transistor of the active pixel detector on each column to detect and amplify the electronic signal, and to externally output the electronic signal. An image array comprising a plurality of detection amplifiers for transferring to a circuit, collecting energy of external reflected or emitted photons, converting the photon energy into an electronic signal and displaying the intensity of the photon energy. . 9. An active pixel sensor array in which a first conductive impurity is implanted into a surface of a semiconductor substrate, and a second conductive impurity well is implanted into the surface of the semiconductor substrate. The image array according to claim 8, wherein: 10. The cathode of the photodiode of each active pixel detector is formed in the well in the surface of the semiconductor substrate, and the anode has the impurity of the first conductive type in the cathode. To form a first area and make the anode larger than the base of the bipolar transistor, thereby restraining minority carriers concentrated on the base to the base, thereby reducing an image delay phenomenon. The image array according to claim 9, wherein: 11. The collector of the bipolar transistor of each active pixel detector, wherein the collector is the well formed in the semiconductor substrate, and the base is the impurity of the first conductivity type in the well. The emitter is formed in a second area into which the impurity of the second conductivity type is implanted in the second area. Item 11. The image array according to Item 10. 12. The drain electrode of the MOS transistor of each active pixel detector has the first area having the impurity of the first conductivity type, and the source electrode has the impurity of the first conductivity type. 12. The second area of claim 11, wherein the gate electrode is formed of a channel area of all gate oxide layers deposited between all the source electrodes and the drain electrodes. Image array. 13. The semiconductor device according to claim 12, wherein the emitter is connected to a detection amplifier by a metal interconnect line deposited on the insulating layer on the surface of the semiconductor substrate, and is in contact with the emitter. Image array according to 1. 14. An active pixel detector, wherein the anode of the photodiode is a drain electrode, and the anode of the photodiode of the active detector adjacent to the row active pixel detector in the active pixel detector array is a source. 9. The image array according to claim 8, further comprising a parasitic MOS transistor serving as an electrode, further comprising a gate electrode. 15. A method of connecting the gate electrode of the parasitic MOS transistor to a reset circuit and resetting the anode of each photodiode of each row active pixel detector to the same potential by activating the parasitic MOS transistor. 15. The image array according to claim 14, wherein the problem of image delay on the image array is solved by: 16. A method of manufacturing an active pixel detector for collecting photon energy and converting the photons into an electronic signal on a semiconductor substrate having a first conductivity type impurity, comprising the steps of: Forming a well in the semiconductor substrate in the mask area, implanting impurities of the second conductivity type into the semiconductor substrate, and (b) growing an electric field oxide layer outside the area to form the active pixel detector. (C) masking the semiconductor substrate to form a photodiode in the well, implanting a first conductive type impurity to form an anode of the photodiode, and forming the well into the well. (D) masking the semiconductor substrate, implanting a first conductivity type impurity to form a base, and masking the semiconductor substrate; Injecting second conductivity type impurity to form the emitter, the Note, the wells and the collector of the bipolar transistor. (e) depositing a gate oxide layer on the channel area of the anode to form a drain electrode of the MOS transistor; A method of manufacturing a semiconductor device, comprising: forming a gate electrode on the gate oxide layer by depositing first polysilicon using the base as a source electrode of the MOS transistor. 17. A method in which the gate electrode is connected to a detection control circuit to activate or deactivate the MOS transistor, so that charges formed by the photons impacting on the anode flow to the base of the bipolar transistor. 17. The method for manufacturing a semiconductor device according to claim 16, wherein: 18. The semiconductor of claim 16, wherein the anode is made larger than the base of the bipolar transistor to reduce image delay by constraining minority carriers of the base to the base. Element manufacturing method. 19. A method for forming a parasitic MOS transistor, comprising: (a) forming a parasitic gate oxide layer of the parasitic MOS transistor by growing an insulator; and (b) forming a second polysilicon on the parasitic gate oxide layer. Depositing silicon to form a gate of the parasitic MOS transistor; (c) a drain electrode of the parasitic MOS transistor,
17. The anode of the photodiode, wherein a source electrode of the parasitic MOS transistor is the anode of the photodiode formed on the semiconductor substrate in proximity to an active pixel detector.
3. The method for manufacturing a semiconductor device according to item 1. 20. Connecting the gate electrode of the parasitic MOS transistor to a reset circuit and supplying a reset signal to activate the parasitic MOS transistor, reset the anode to a predetermined potential, and 17. The method for manufacturing a semiconductor device according to claim 16, wherein an image delay of the pixel detector is eliminated.