RU2494497C2 - Mos-diode cell of solid radiation detector - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: invention relates to semiconductor coordinate detectors of radiation particles. A MOS-diode cell of a solid radiation detector comprises a MOS-transistor, a bus of high positive (negative) power supply voltage and an output bus. The MOS-transistor is a depleted transistor of n (p) conductivity type (i.e. has an inbuilt channel), at the same time its gate area is connected to the common power supply bus, a drain - to the output bus, and the gate is connected to an anode (cathode) of the diode and to the first output of the resistor, the diode cathode (anode) is connected to the bus of high positive (negative) power supply voltage, the second output of the resistor is connected to the bus of negative (positive) shift voltage. Also a structure (a functionally integrated structure) of the MOS-diode cell of the solid radiation detector is proposed.

EFFECT: increased quality of detection.

8 cl, 10 dwg

Description

The invention relates to semiconductor coordinate detectors of radiation particles.

Known cells (pixels) for monolithic radiation detectors based on pin diode [1], diode-capacitive CMOS cell [2], DEPMOS-MOS transistor with substrate control [3, 4], bipolar transistor structures [3, 4] or functionally integrated BI-MOS structure [5].

disadvantages

The diode cell [1] does not provide signal amplification in a pixel and, therefore, the speed and sensitivity of the detector. Diode-capacitive CMOS cell [2], DERMOS - MOS cell have a low slope and a relatively high noise level due to control over the substrate, which limits their spectral sensitivity. Bipolar transistor structures have a reduced breakdown voltage due to the floating base potential and gain nonlinearity at a low signal level (current density).

The closest in technical essence is the integrated BI-MOS cell of the radiation detector [5]. This circuit and cell design (pixels) is selected as a prototype.

The electrical circuit of the cell contains a MOS transistor, a bus of high positive (negative) supply voltage, an output bus (see drawing 1 of figure 1).

The design of the detector cell (see Fig. 2) of the prototype (functionally integrated BI-MOS structure) contains a semiconductor substrate of the first type of conductivity, on the lower surface of which there is a substrate electrode connected to a high positive (negative) supply voltage bus, and on the top surface - a thin dielectric layer on which the gate electrode of the MOS transistor is located, the region of the 2nd type of conductivity is also located in the substrate, in which the region of the 1st type of conductivity is located, on the surface which is the electrode connected to the output bus.

This cell also does not have the best detection quality due to the low sensitivity and non-linearity of the amplification of the bipolar transistor, which leads to a distortion of the spectrum during detection, especially for “deep” penetrating and weakly interacting radiation particles (electrons, gamma and X-ray quanta), because:

- the sensitivity of the cell structure is proportional to the value (depth) of the space charge region (SCR) (see drawing 1 of FIG. 2) in the substrate, which in turn depends on the magnitude of the supply voltage determined by the breakdown voltage of the emitter-collector of the bipolar transistor. It (especially in the “floating” base mode) is much less than the breakdown voltage of the collector p-n junction (p-i-n-diode) [6, 7];

- amplification by the bipolar structure of small "ionization" currents formed by weakly interacting particles is much less than the maximum and is non-linear [8].

The technical result of the invention is to improve the quality of detection, i.e. spectral resolution, sensitivity and linearity of the radiation detector.

The technical result is achieved due to:

- an electrical circuit (see drawing 2 of FIG. 3), in which the MOS transistor is a conductivity type n (p) depleted transistor (i.e., has an integrated channel), its gate region is connected to a common power bus, and the drain to the output bus and the gate is connected to the anode (cathode) of the diode and to the first output of the resistor, the cathode (anode) of the diode is connected to the bus of high positive (negative) supply voltage, the second output of the resistor is connected to the bus of negative (positive) bias voltage;

- n-MOS cell design (functionally integrated structure) of the radiation detector cell, containing in the semiconductor substrate regions of the 1st conductivity type two regions of the 2nd conductivity type, forming anodes (cathodes) of the first and second diodes, respectively, on the surface of which there are corresponding electrodes the first and second anode (cathode), and the electrode of the anode (cathode) of the first diode is connected to the first electrode of a polysilicon resistor located on a thick dielectric and located on a thin die ektrike polysilicon gate n (p) MOS transistor with integrated channel, the second electrode of the resistor connected to the bus of the negative (positive) displacement voltage. Moreover, the region of the 2nd type of conductivity of the anode (cathode) of the second diode is simultaneously the gate region of the "pocket" n (p) of the type of conductivity n (p) of the MOS transistor with an integrated channel in which the drain and source regions of the first type of conductivity are located, on which respectively the drain and source electrodes are located, connected respectively to the output bus and the common power bus.

- CMOS cell design (functionally integrated structure, see Fig.6) additionally contains in the gate region of the "pockets" n (p) type of conductivity, the second gate region of the pocket "n (p) type of conductivity n (p) MOS transistor, which are the drain and source regions of the 2nd type of conductivity, on which respectively the drain and source electrodes are connected, respectively connected to the output bus and the source of additional positive (negative) supply voltage.

It should be canceled that, in particular, the case of an “embedded” channel in the transistor may be absent, however, the sensitivity of the detector cell is sharply reduced.

It should be noted that the presence in the cell (pixel) of a functionally integrated diode MOS structure allows it to be very compact, and the use of a p-i-n diode (see Fig. 4) increases the SCR by 4-5 times and practically eliminates the non-linearity of low current amplification.

In order to simultaneously measure 2 coordinates

- the electric circuit (see Fig. 7) further comprises a second n (p) MOS transistor with a built-in channel, its gate, source and gate region being connected to the corresponding regions of the first MOS transistor, and the drain to the second output bus.

In order to improve performance

- the electric circuit (see Fig. 8) additionally contains the third and fourth amplifying MOS transistors and a second resistor, the gate region of the third transistor connected to the source region of the first transistor, the source region to the common bus, and the drain region to the first output bus, and the region the gate of the fourth transistor is connected to the source region of the second transistor, the source region to the common bus, and the drain region to the second output bus, the gate region of the third and fourth MOS transistors are connected to the common bus through the second res torus.

In order to expand the scope

- the electric circuit (see Fig. 9) additionally contains the address and discharge buses, the second - the amplifying MOS transistor, the third - the address (selection) MOS transistor and the fourth - MOS transistor - zero, while the source of the first-depleted MOS transistor is connected to the gate of the second - the amplifying transistor and the drain of the fourth - the MOS transistor - zero, the source of which is connected to the common bus, and the gate - to the reset bus, while the source of the amplifying transistor is connected to the common bus, and its drain - to the source of the third transistor and, the drain of which is connected to the bit line and the gate - to the address bus.

The invention is illustrated by the drawings:

The electrical circuit for the prototype

Figure 1 shows the electrical circuit of the prototype of the integrated BI-MOS cell radiation detector of the prototype, containing MOS - T1 and bipolar - T2 transistors.

Integrated Circuit for Prototype

Figure 2 presents a section of the cell structure of the prototype and its topological drawing (top view). The structure contains a semiconductor substrate 1 of the first (n) type of conductivity, which forms the collector region of the BI-MOS structure. The lower part of the substrate 1 is heavily doped and forms a layer 2 to create an ohmic contact to the collector electrode 3. In the region of the collector substrate 1, there is a base region 4 of the second (p) type of conductivity. In the region of the base 4, there is an emitter region 5 of the first (n) type of conductivity, on which the emitter electrode 6 is located. On the surface of the collector-substrate region 1 there is a dielectric layer 7, on the surface of the dielectric layer 7 there is an electrically conductive gate electrode 8.

Electrical circuits for the invention

Figure 4, 6-10 shows options for electrical circuits of the invention - MOS diode cells of the radiation detector.

The electrical circuit of figure 3 contains:

- the first MOS transistor - T1 is a conductivity type n (p) depleted transistor (i.e., has an integrated channel), its source and gate region are connected to a common power bus, the drain to the output bus is X, and the gate is connected to the anode (cathode) ) of the diode and with the first output of the resistor - R1, the cathode (anode) of the diode is connected to the bus of a high positive (negative) supply voltage + Vdd. the second output of the resistor is connected to the bus negative (positive) bias voltage - Vcc.

The electrical circuit in figure 4 contains:

- additional p (n) MOS transistors, the gate of which is connected to the gate p (n) of the MOS transistor, the drain with the drain of both transistors is connected to the output bus, the source p (n) of the MOS transistor is connected to the positive (negative) power bus.

The electrical circuit in Fig.7 contains:

- the second MOS transistor T2 with n (p) type of conductivity with an integrated channel, and its gate, source and gate region are connected to the corresponding areas of the first MOS transistor - T1, and the drain with the second output bus is Y.

The electrical circuit in Fig. 8 contains:

the third is T3 and the fourth is T4 amplifying MOS transistors, the second resistor is R2, and the gate region of the third transistor - T3 is connected to the source region of the first transistor - T1, the source region to the common bus, and the drain region to the first output bus - X, and the region the gate of the fourth transistor - T4 is connected to the source region of the second transistor - T2, the source region is to the common bus, and the drain region to the second output bus is Y, the first output of the second resistor R2 is connected to the gates of the third and fourth amplifying transistor - T3, T4, and the second conclusion to the general bus.

The electrical circuit in figure 9 contains:

- additional reset bus - R (zeroing), address - S, bit - Q bus, the second - amplifying MOS transistor - T2, the third - address \ selection \ MOS transistor - T3 and the fourth - MOS transistor - T4 - zero, while the source of the first - depleted MOS transistor - T1 is connected to the gate of the second - amplifying T2 transistor and the drain of the fourth - MOS transistor - T4 - zero, the source of which is connected to the common bus, and the gate with the reset bus is R, while the source of the amplifying transistor is T2 connected to a common bus, and its drain to the source of the third trans ora selection T3, a drain of which is connected to the bit line - Q, a gate to the address bus - S.

The electric circuit in figure 10, similar to figure 3, 4 further comprises a pulse counter of radiation particles

The integrated circuit of the invention is shown in figure 5.

The functionally integrated structure of the integrated circuit of the n-MOS cell contains a semiconductor substrate of the first type of conductivity - 1, on the lower surface there is a heavily doped layer of the first type of conductivity - 2, on which the electrode of the substrate - 3, connected to the high positive bus ( negative) of the supply voltage + Vdd, and on the upper surface of the substrate is a thin dielectric layer - 7, on which the gate electrode of the MOS transistor - 8 is located, the region of the 2nd type of conductivity - 4 is also located in the substrate, which is located under the gate region of the MOS transistor, in which the region of the 1st type of conductivity is located, 5, which is the drain region of the MOS transistor, on the surface of which the electrode is located, 6 connected to the output bus X, and the region of the 1st type of conductivity, 9, is the source region The MOS transistor, and on its surface and the surface of the region of the 2nd type of conductivity - 4 is an electrode - 10, connected to a common bus. On the surface of the substrate - 1 is a thick dielectric - 11, on its surface there is a polysilicon resistor - 12, on the surface of which there are two electrodes, the first - 13 is connected to the gate electrode - 8, the second - 14 is connected to a negative \ positive source the supply voltage is Vcc, in pos. 1 there is a second region of the 2nd type of conductivity, which forms the anode (cathode) of pin diode 15, on its surface there is an electrode - 16, connected to the gate electrode - 8 and the first electrode - 13 resistors

- a functionally integrated structure of an integrated circuit of a CMOS cell containing an additional gate region of "pocket" n (p) of conductivity type - 17, in which drain regions - 18 and source - 19 n (p) are located - MOS transistors on which electrodes are respectively located 20, 21. On the surface of the "pocket" 17 there is a gate dielectric - 22 and a polysilicon gate - 23, on the surface of which there is a gate electrode - 24, on the surface of the pocket there is a pocket electrode - 25 connected to the source of positive power + Vcc.

MOS diode cell of the radiation detector works as follows (diagram in Fig. 3, design in Fig. 5).

When passing through the substrate 1 of a radiation particle (Fig. 2), for example, a relativistic electron, electron-hole pairs are formed along its track in the space charge region (SCR) of the pin junction formed by the substrate - 1 n-type and the anode - 4 p + diodes -type of conductivity, and partially in the quasi-neutral region. The electron-hole pairs formed by the radiation particle in the CCW are separated by the field of positive voltage + Vdd and form the ionization current of the pin diode - D, which, flowing through the resistor - R to the negative voltage power supply - Vc, creates a positive voltage drop on it, which opens depleted n-MOS transistor "with integrated channel". The current flowing through the MOS transistor will create an output bus X signal about its arrival time, energy (spectrum) and coordinate.

An important circumstance should be noted. The ionization current flows only through the resistor and anode of the first diode, since it has a lower potential - Vc than the anode of the second diode, which is the gate region of the MOS transistor. Moreover, it must have an integrated channel, otherwise it will not open with a small voltage (0.01-1 mV), created by the ionization current of weakly interacting particles [7].

When registering "heavy" particles, for example, atomic nuclei, a conventional "enriched" MOS transistor (without an integrated channel) can be used.

The circuit in figure 4 works in a similar way, only 2 transistors of a different type of conductivity can reduce the energy consumption of the detector.

The circuit in Fig. 7 works in a similar way, however, the presence of a signal from the second transistor - T2 allows you to determine the second coordinate of the particle’s entry into the detector.

The circuit in Fig. 8 works in a similar way, but the presence of amplifying transistors T3 and T4 allows amplifying the signals from transistors T1 and T2, thereby accelerating the recharging time of the output buses X and Y and, accordingly, the speed of the pixel detector matrix.

The circuit in Fig. 9 works in a similar way to the circuit in Fig. 7, i.e. the signal on the output bus - X allows you to determine the time of arrival of the particle, its energy and coordinate (or 2nd coordinates, see Fig.7). In this case, the signal, falling on the gate of the amplifying transistor T2, is stored for some time (equal to the relaxation time of the charge) in the capacitance C formed by the gate capacitance - the position of the transistor T3. The current state of the transistor T3 (the value of its resistance) is read out on the bit - bus Q by the transistor T3 when it is opened by applying a signal on the address bus S. The transistor T4 serves to set the cell to its original state - zeroing by sending a reset signal to the bus R.

The presence of an additional three transistors also allows the function of "storing" the signal from one or more particles, which can be read out after some time. This circumstance is important when registering high-intensity radiation fluxes (P> 100M X-ray / s), when sampling information on a single quantum in the "real" time scale is very problematic (i.e., exceeds 1G bits per crystal).

It should be noted that the source of the transistor T2 can be connected to another bus, for example, to the power bus.

The circuit in Fig. 10 works in a similar way as the circuits of Figs. 3, 4, while connecting the counter allows you to determine the number of quantum particles entering the detector pixel.

An example of a specific implementation.

The two-dimensional matrix of detector pixel cells can be performed according to the standard n-MOS (or CMOS) technology used in the manufacture of integrated circuits, for example, along the following technological route:

a) the formation of an n + - contact region - 2 to the silicon wafer - 1 with a resistance of p _v ~ 5 kΩ / cm with an orientation of 100, for example, diffusion of phosphorus in the opposite direction of the plate;

b) oxidation of the silicon surface and the formation in thick oxide — 11 windows for p + regions — 4, 15 using the first photolithography process and the formation of boron atoms by implantation and the subsequent mode of annealing and distillation of the impurity into the depth of the substrate;

c) oxidation of the silicon surface, the formation of a thin gate oxide — 7 and deposition of a polycrystalline silicon layer on the wafer surface and the operation of the second photolithography — polysilicon cladding — 12;

d) carrying out 3 photolithographs and subsequent implantation of arsenic in polysilicon, i.e. the formation of the gate region - 8 and the drain regions, the source of the n-type MOS transistor, followed by thermal annealing;

d) in the formation of a resistor by implanting phosphorus in polysilicon and subsequent annealing;

f) in the deposition of a low-temperature dielectric and the formation in it of the 4th photolithography of contact windows;

g) the deposition of aluminum and the 5th photolithography of wiring (clipping) of aluminum.

Test bipolar transistors made using this technology had a breakdown voltage of V ke not more than 50 V, pin V diodes above 300 V, depleted MOS transistors had a threshold voltage of V _T = -1.0 V, and ordinary transistors enriched Vt = + 1.0 V [8 ].

Literature

1. D. Patti etal United Slates Patent No. US6.465.857.B1 Date Oct. 15.2002. US 006465857B1.

2. I.Peric; "A novel monolithic pixelated particle detector implemented in high-voltage CMOS technology." Nucl. Inst. Meth. Band A 582. pp. 876-885. August 2007

3. J. Kemmer, G. Lutz: Nucl. Instrum. Methods A 273. 588-598 (1988).

4. Murashev B.H. and others. "Coordination detector of relativistic particles" invention patent No. 2197036 from 01.20, 2003 priority from 02.19.2000.

5. Integrated BI-MOS cell radiation detector. RF patent No. 2383968 dated March 20, 2006

6.S. and. Physics of semiconductor devices. Moscow because of the World. 1984 1.1.

7. D.L. Volkov, D.E. Karmanov. V.N. Murashev. S.A. Legotin, R.A. Mukhamedshin. and A.P. Chubcnko. A New Position-Sensitive Silicon Pixel Detector Based on Bipolar Transistors // INSTRUMENTS AND EXPERIMENTAL TECHNIQUES. 2009.No. 52, pp. 655-664.

8. V.N. Murashev, S.A. Legotin. O.M. Orlov. A.S. KoroEchenko. and P.A. Ivshin, A silicon position-sensitive detector of charged particles and radiations on the basis of functionally integrated structures with nano-micron active regions // INSTRUMENTS AND EXPERIMENTAL TECHNIQUES. 2010, No. 53.657-662.

Claims (8)

1. The MOS diode cell of a monolithic radiation detector contains a MOS transistor, a bus of high positive (negative) supply voltage, an output bus, characterized in that the MOS transistor is a depletion transistor of an n (p) -type of conductivity (that is, it has an integrated channel ), while its gate region is connected to a common power bus, the drain to the output bus, and the gate is connected to the anode (cathode) of the diode and to the first output of the resistor, the cathode (anode) of the diode is connected to the bus of a high positive (negative) supply voltage, Torah terminal of the resistor connected to the bus of the negative (positive) displacement voltage. 2. MOS diode cell of a monolithic radiation detector according to claim 1, characterized in that it contains an additional transistor of n (p) -type conductivity, and its gate is connected to the gate of the first n (p) MOS transistor, the drain to the drain of the first transistor, source and a gate region to an additional source of positive (negative) supply voltage. 3. MOS diode cell of a monolithic radiation detector according to claim 1, characterized in that it contains a second, depleted n (p) -type MOS transistor, and its source, gate region and gate are connected to the corresponding areas of the first MOS transistor the drain is connected to a second output bus. 4. MOS diode cell of a monolithic radiation detector according to claim 3, characterized in that it further comprises a third and fourth amplifying MOS transistors and a second and additional resistors, the gate region of the third transistor connected to the source region of the first transistor, the source region to the common bus, and the drain area to the first output bus, and the gate region of the fourth transistor is connected to the source region of the second transistor, the source region to the common bus, and the drain region to the second output bus, the gate region of the third and even The second MOS transistors are connected to a common bus via a second resistor. 5. The MOS diode cell of the monolithic radiation detector according to claim 1, characterized in that it further comprises a reset bus, an address and a discharge bus, the second is an amplifying MOS transistor, the third is an address (selection) MOS transistor and the fourth MOS transistor is zero while the source of the first - depleted MOS transistor is connected to the gate of the second - amplifying transistor and the drain of the fourth MOS transistor is zero, the source of which is connected to a common bus, and the gate with a reset bus, while the source of the amplifying transistor is connected to bus, and its drain to the source of the third selection transistor, the drain of which is connected to the discharge bus, and the gate to the address bus. 6. MOS diode cell of a monolithic radiation detector according to claim 1, or 2, or 3, characterized in that the first MOS transistor is connected to a pulse counter of radiation particles. 7. Design (functionally integrated structure) of a MOS diode cell of a monolithic radiation detector containing a semiconductor substrate of the 1st type of conductivity, on the lower surface there is a heavily doped layer of the 1st type of conductivity, on which the substrate electrode connected to the high positive bus ( negative) supply voltage, and on the upper surface there is a thin dielectric layer on which the gate electrode of the MOS transistor is located, a region of the second type of conductivity is also located in the substrate the type in which the region of the 1st type of conductivity is located, on the surface of which an electrode is connected to the output bus, characterized in that it contains two regions of the 2nd type of conductivity in the semiconductor substrate of the 1st type of conductivity, forming anodes (cathodes), respectively the first and second diodes, on the surface of which there are corresponding electrodes of the first and second anodes (cathodes), the electrode of the anode (cathode) of the first diode connected to the first electrode of a polysilicon resistor located on a thick m dielectric, and located on a thin dielectric polysilicon gate n (p) of the MOS transistor with an integrated channel, the second electrode of the resistor is connected to the bus of negative (positive) bias voltage, while the region of the 2nd type of conductivity of the anode (cathode) of the second diode is simultaneously the gate region n (p) of the MOS transistor with an integrated channel in which the drain and source regions of the first type of conductivity are located, on which respectively the drain and source electrodes are connected, respectively connected to the output busbar and common power bus. 8. The design (functionally integrated structure) of the MOS diode cell of the monolithic radiation detector according to claim 7, characterized in that it further comprises in the gate region the "pockets" of an n (p) -type of conductivity, the second gate region of the "pocket" of n (p) the conductivity type n (p) of the MOS transistor, in which the drain and source regions of the 2nd type of conductivity are located, on which the drain and source electrodes are respectively connected, connected respectively to the output bus and the source of additional positive (negative) voltage food symptoms.

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