RU2532241C1 - Monolithic rapid coordinate detector of ionising particles - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: offered invention "Monolithic rapid coordinate detector of ionising particles" relates to semiconductor coordinate detectors of ionizing particles. The goals are achieved at the expense of the use of original circuit of the detector, where bipolar transistors, connected in a circuit with common collector, also due to functionally integrated monolithic design of the detector where the semiconductor substrate, generating the charge carriers, simultaneously appears to be a common collector area of bipolar structures of transistors.

EFFECT: purpose of invention is increase of speed and manufacturability of coordinate detector, that is especially important for creation of new generation of "detectors of trace neutrons" for detection of explosive substances, X-ray scanners for medical, customs and other applications characterised by higher quality of object images, compared with known analogues.

3 cl, 5 dwg

Description

The invention relates to semiconductor coordinate detectors (PCD) of ionizing particles used in nuclear physics devices, medicine, customs control, etc.

Known electrical circuits and designs of hybrid detectors that contain a detecting matrix consisting of strip or p - / - "structures and external amplifying and encoding electronic devices [1. D. Patti ot ab. “Semiconductor particle detector and method for IIS Manufacture)) Patent No.US 6,465,857, Bl, Date of patent Oct. 15. 2002; 2. Jan S. Iwanczyk "Semiconductor radiation detector" Patent No. 6,455,858, Date of patent Sep. 24. 2002; 3. Jan S. Iwanczyk “Semiconductor radiation detector with internal gain” Patent No. US 6,541,836 B2, Date of patent: Apr. 2003; 4. Y. Ikegami, et al., Nucl. Instr. and Meth. A (2007), in press.], Or monolithic detectors containing pixel arrays based on MOS structures and peripheral amplifying and encoding electronic devices based on CMOS circuits, placed in a single crystal - chip [5. Kemmer, J., Lutz, G. (1990) et al .: “Experimental confirmation of a new semiconductor detector principle)) Nucl. Instr. & Meth. A288 (1990) 92-98].

disadvantages

The former have a relatively high cost and complex assembly process, since a large number of connections between the matrix and external electronics are required, for example, for a mega-pixel matrix, their number is 2000.

The second ones do not provide the maximum speed of the detectors and obtain the best quality of radiation detection, because:

- MOS structures of pixel arrays have a high internal resistance, which leads to a delay of signals on the discharge buses of the arrays;

- the designs of the matrices and peripheral electronic circuits of the monolithic detector are significantly different, which complicates the technology of their joint manufacturing in a single chip, and most importantly, this leads to a deterioration in the parameters of the detecting matrix, and therefore the entire detector.

The closest in technical essence is a semiconductor coordinate monolithic detector based on functionally integrated bipolar transistor structures [6. Murashev V.N. and others "Coordinate-sensitive detector", patent for the invention No. 2133524 from 07.20.1999; 7. Murashov V.N. and others. “Coordination detector of relativistic particles”, patent for invention ”, No. 2197036 priority of 02.19.2000; 8. Murashov V.N., Legotin S.A., Didenko S.I. and others. "Integrated cell radiation detector based on a bipolar transistor with a mesh base", patent for the invention No. 2427942 from 04/08/2010; 9.V.N. Murashev, S.A. Legotin, A.S. Korolchenko, M.N. Orlova "The technology of manufacturing coordinate detectors" - Questions of atomic science and technology. Series: Physics of Radiation Exposure to Electronic Equipment, 2011., Issue No. 3, p.22-26], the electrical circuit and design of which is selected as a prototype [6. Murashev V.N. and others "Coordinate-sensitive detector", patent for the invention No. 2133524 from 07.20.1999; 9. V.N. Murashev, S.A. Legotin, A.S. Korolchenko, M.N. Orlova "The technology of manufacturing coordinate detectors" - Questions of atomic science and technology. Series: Physics of Radiation Exposure to Radio-Electronic Equipment, 2011, Issue No. 3, p.22-26].

The electrical circuit of the prototype contains a coordinate matrix pixel, consisting of two-emitter bipolar transistors with a common collector [9. V.N. Murashev, S.A. Legotin, A.S. Korolchenko, M.N. Orlova "The technology of manufacturing coordinate detectors" - Questions of atomic science and technology. Series: Physics of Radiation Exposure to Electronic Equipment, 2011., Issue No. 3, pp.22-26], with the first emitters of transistors connected to the bit coordinate buses of the rows X _j , and the second emitters, respectively, to the bit coordinate buses of the columns and bit the buses are connected to the gates of the MOS transistors of the peripheral amplifying and CMOS coding electronic circuits connected to the corresponding address buses of the rows Z _j and columns W _j .

The design of the prototype detector [7. Murashev V.N. and others. "Coordination detector of relativistic particles" patent for an invention ", No. 2197036 priority of 02/19/2000; 9. V.N. Murashov, S.A. Legotin, A.S. Korolchenko, M.N. Orlova "The technology of manufacturing coordinate detectors" - Questions of atomic science and technology. Series: Physics of Radiation Exposure to Electronic Equipment, 2011., Issue No. 3, pp.22-26] consists of a semiconductor substrate of the first type of conductivity, which is the common collector region of bipolar transistors, in which the base regions of the detector 2- pixel matrix are located the first conductivity type, in which there are regions of the first and second emitter 1st conductivity type, on which the respective electrodes are respectively connected to the bit buses coordinate X _j and Y _j, which in turn, subfamily dineny to the gates of the MOS transistors and the peripheral reinforcement encoding circuitry connected computer.

disadvantages

The design of, for example, a silicon detector is complicated, because it contains peripheral CMOS circuits that are difficult to implement, even on silicon, and their manufacturing uses technological operations (high-temperature thermal annealing, etc.), which lead to a decrease in the lifetime of minority charge carriers in the substrate, and, consequently, the degradation of the parameters of the detecting matrix.

At the same time, it should be noted that it is technically impossible to implement the detector in one substrate from, for example, gallium arsenide containing a matrix of bipolar structures with a common collector and field transistors of peripheral circuits electrically isolated from it.

The technical result of the present invention is to increase the speed, reduce the size of the matrix, increase manufacturability and simplify the design of the integrated circuit of the coordinate detector.

It is known that the fastest circuit is a signal (power) amplifier circuit implemented on a bipolar transistor with a “common collector” - emitter follower (for example, in ESL or BI-CMOS logic circuits, etc.). Therefore, this monolithic integrated circuit has the highest possible speed.

EFFECT: improved performance is achieved by the fact that in the detector circuit electric circuit, the coordinate buses X _j and Y _{j of} the pixel matrix are connected to the bases of bipolar transistors with a common collector, peripheral amplifying and coding electronic circuits.

The technical result - reducing the size and simplification of the matrix, which is appropriate for a number of applications, for example, the “scanner line”, is achieved by the fact that in the electrical circuit of the detector (which is the limiting case of the matrix - consisting of one row), the coordinate buses Y _{j of the} matrix pixel are connected to the bases bipolar transistors with a common collector, peripheral amplifying and coding electronic circuits, and the only coordinate bus X ₁ - to the information bus Q.

It should be noted that in cases where information about the quantum energy is not required (it is known in advance), the electric circuit of the detector line and the design can be further simplified and reduced to be a pixel line of single-emitter transistors whose emitters are connected to Y coordinate buses _j , which are respectively connected to the bases of bipolar transistors with a common collector, peripheral amplifying and coding electronic circuits.

EFFECT: increased manufacturability and simplified design of a monolithic integrated circuit of the detector, bit coordinate buses X _j and Y _j connected to the bases of the corresponding bipolar transistors of peripheral amplifying and encoding electronic circuits, while their collector is also a common collector region formed by a type 1 substrate conductivity.

The difference of the claimed design from the known integrated circuits is that the matrix transistors and peripheral transistors form a single functionally integrated structure of an array of exactly the same bipolar transistors (included by the emitter follower circuit), performed using one simple technology, without the need for additional complex and dirty "technological operations for the formation, for example, CMOS circuits.

Achieving declared goals is especially important for creating a new generation of matrix “tagged neutron detectors” for detecting explosives [10. Bystritsky V. M. et al., DViN - stationary setup for identification of explosives, JINR Commun. El8-2007-142. Dubna, 2007; Physics of Particles and Atomic Nuclei, Letters. 2008, Vol.5, No. 5, pp.743-751] and improve the image quality of the "rulers of scanners" of x-rays for medical and customs applications.

The invention is illustrated by the drawings.

Figure 1 shows the electrical circuit of the detector. It contains a pixel matrix of two-emitter transistors - T _{1 the} first emitters that are connected to the bit coordinate coordinate lines of the rows X _j , and the second emitters, respectively, to the bit coordinate coordinate lines of the columns Y _j , the bit coordinate lines of the columns X _j and columns Y _{j are} connected to the bases of bipolar peripheral transistors - T ₂ , the collector, which is connected to a common power bus (+ V _dd ), and emitters to the corresponding address buses of the rows Z _j and columns W _j .

Figure 2 shows the design of the detector.

It contains a semiconductor substrate - 1 of the first (n) type of conductivity, which forms the collector region of the bipolar transistors of the matrix - T ₁ and peripheral devices - T ₂ , in which are located the areas from the bases - 2 of the second (p) type of conductivity, in which the regions are respectively located emitters - 3 of the first (n) type of conductivity, on which the corresponding electrodes are located - 4 connected to the corresponding discharge buses - 5, which are connected to the electrodes of the bases of peripheral transistors - 6, the electrode - 7 which emitters are connected us to address lines respectively - 8. The elements of the detector constructions - emitters bit lines isolated dielectrics - 9, 10, and the pin is n ⁺ -layer -11 on the reverse side of the substrate.

A monolithic integrated circuit of a high-speed coordinate detector of ionizing particles works as follows.

When an ionizing particle passes through a substrate - 1 (see Fig. 3, a), for example, a relativistic electron or alpha particle, electron-hole pairs form along its track, which are collected by the field mainly in the space charge region (SCR) formed by in the pn region of the collector-base junction of the transistor of the matrix T ₁ , when a positive voltage + Vdd is applied to the collector relative to the emitter, and partially in the quasi-neutral region (CCW).

The electron-hole pairs formed by the ionizing particle are separated by the field and form the primary ionization current of the collector pn junction - (I _and ), which is amplified by the bipolar structure of the transistor (pixels) tens to hundreds of times, forming the currents of the first and second emitters.

These currents flow through the corresponding j-pixels to the bit buses X _j and Y _j to the bases of the corresponding peripheral amplifying bipolar transistors - T ₂ , which, in turn, quickly amplify the signal and encrypt it in the binary address code of the row and column of the pixels into which ionizing particle.

The magnitude of the ionization current, and therefore the energy released by the ionizing particle, can be measured by an external amplifier with respect to the detector integrated circuit in the detector collector circuit, Fig. 3, b.

Figure 4 shows the electrical circuit of the detector. It consists of one line, the coordinate buses Y _{j of} which are connected to the bases of bipolar transistors with a common collector, peripheral amplifying and coding electronic circuits, and the coordinate bus X ₁ to the information bus - Q.

This electrical circuit works in a similar way, however, in this case, the ionization current is measured in the information bus - Q, which is more accurate due to the less influence of the leakage currents of the matrix transistors and an external signal amplifier is not required.

Figure 5 shows the electrical circuit of the detector containing a pixel string of single-emitter transistors, the emitters of which are connected to the coordinate bus Y _j , which are respectively connected to the bases of bipolar transistors with a common collector, peripheral amplifying and encoding electronic circuits.

This circuitry works in a similar way.

An example of a specific implementation.

The detector can be made using a simple standard technology used in the manufacture of bipolar integrated circuits, which consists in performing the following technological operations:

a) the formation of an n ⁺ - contact region to the collector - 11, for example, by diffusion of phosphorus in the opposite direction of the silicon wafer - 1 with a specific resistance ρ _v ~ 5 kOhm · cm;

b) oxidation of the silicon surface and formation in the oxide - 10 windows for the base regions - 2 using the photolithography process, the formation of base regions by implantation of boron atoms with subsequent annealing and acceleration of the base impurity into the depth of the substrate;

c) deposition of a polycrystalline silicon-4 layer on the wafer surface followed by implantation of, for example, arsenic atoms, thermal firing and acceleration of arsenic from polysilicon to a substrate, i.e. formation of the emitter region and polysilicon photolithography for forming the emitter regions - 3 and the emitter electrode - 4;

d) deposition of the 2nd layer of the dielectric — 9, the formation of contact windows in it, the deposition of aluminum — 10 and the formation of ohmic contacts to the matrix by photolithography: emitters — 4 pixels, collector — 11 and base — 6.

Claims (3)

1. A monolithic high-speed coordinate detector of ionizing particles, the electrical circuit of which contains a coordinate matrix of pixels consisting of two-emitter bipolar transistors with a common collector, while the first emitters of the transistors are connected to the bit coordinate buses of the lines X _j , and the second emitters, respectively, to the bit coordinate buses columns Y _j that are connected to transistors of peripheral amplifying and coding electronic circuits connected to the corresponding address line buses Z _j and columns W _j , characterized in that the coordinate buses X _j and Y _{j of the} matrix of pixels are connected to the bases of bipolar transistors with a common collector, peripheral amplifying and coding electronic circuits. 2. The detector according to claim 1, characterized in that the structure contains in a semiconductor substrate of the 1st type of conductivity, which is the common collector region of bipolar transistors, in which are located the pixel base region of the matrix of the detector of the 2nd type of conductivity, in which the regions of the first and second emitters 1st conductivity type, on which the respective electrodes are respectively connected to the bit buses coordinate X _j and Y _j, which in turn are connected to peripheral transistors Wuxi itelnyh and encoding circuitry connected to respective address lines of rows Z _j and column W _j, wherein the bit coordinate bus X _j and Y _j are connected to the bases of the respective bipolar transistors of peripheral reinforcement and coding circuitry, with their collector as a common collector region formed by a substrate of the first type of conductivity. 3. The detector according to claim 1, characterized in that it consists of a single line pixel of single-emitter transistors, the emitters of which are connected to the coordinate bus Y _j , which, respectively, are connected to the bases of bipolar transistors with a common collector, peripheral amplifying and encoding electronic circuits.

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