JP3447326B2 - Solid-state imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-pixel mixed MOS type solid-state image pickup device, and more particularly to a solid-state image pickup device which achieves high sensitivity by utilizing an avalanche multiplication effect.

SUMMARY OF THE INVENTION The present invention is a multi-pixel mixed type M
In the OS-type solid-state image sensor, when the photoelectrically converted accumulated charges are mixed, the pixel mixing FET causes an avalanche multiplication action of the charges, so that the sensitivity is high.
It is possible to realize a high-gain solid-state imaging device.

[0003]

2. Description of the Related Art Conventionally, a multi-pixel mixed MOS type solid-state image pickup device has been used as a means for improving the aperture ratio of the solid-state image pickup device and realizing a higher resolution and a larger number of pixels.

[0004]

However, the conventional multi-pixel mixed type MOS solid-state image pickup device has a problem that a charge amount larger than the charge generated by photoelectric conversion cannot be taken out as a photodiode output.

Further, in such a multi-pixel mixed type MOS solid-state image pickup device, if the photoelectric conversion part and the amplification part are separated from each other, the external noise and the switching noise caused by the wiring are caused by the theory of noise. Therefore, in order to realize an image pickup device with high S / N (signal-to-noise ratio), it is necessary to provide a signal amplification section closer to the photoelectric conversion section, and the arrangement of elements by that much. There was a problem that the margin was reduced.

Therefore, in order to solve such a problem,
Although an amplifier is provided at the output of the solid-state image pickup device, such a method has a problem that an S / N larger than the S / N of the image pickup device itself cannot be obtained.

As another method, high sensitivity (high SN
In order to realize the purpose of (ratioing), a solid-state image sensor using an APD (avalanche photodiode) having a photocurrent multiplying action has already been proposed in the photodiode itself.
(H.Komobuchi, M.Morimoto, andT.Ando, IEEE Electron De
vice Letters, vol.10, no.5 May, 1989).

However, the method of using such an APD has a problem that the element structure and the circuit configuration become complicated.

In view of the above-mentioned circumstances, the present invention has a simpler structure and circuit configuration than the APD, but has an avalanche multiplication mechanism for accumulated charges in the vicinity of the light-receiving pixel so that a larger amount of charge than that generated by photoelectric conversion can be obtained. It is an object of the present invention to provide a solid-state image sensor that can be taken out as an output.

[0010]

In order to achieve the above-mentioned object, the present invention provides a solid-state image pickup device for performing photoelectric conversion by arranging a plurality of unit pixel sensors in a grid pattern, and each of the unit pixel sensors has multiple pixels. A mixed charge type FET is formed between the photodiodes constituting each unit pixel sensor, and the accumulated charge mixing FET is formed to have an avalanche multiplication of the accumulated charge depending on the impurity concentration of the source and drain regions of the accumulated charge mixing FET. A process for providing a sufficient concentration difference or a process for providing a potential difference sufficient to cause avalanche multiplication of stored charges in the potentials of the source and drain regions of the stored charge mixing FET when the stored charges are mixed is performed by the unit pixel sensor. It is characterized in that a pixel-mixed MOS type solid-state element is configured.

[0011]

[0012]

In the present invention having the above-mentioned structure, when the photoelectrically converted accumulated charges are mixed, the charge multiplication action is performed by the channel region of the accumulated charge mixing FET formed between the photodiodes, and photoelectric conversion is performed. A charge amount larger than the generated charge is taken out as a photodiode output.

In the second aspect of the invention, when the photoelectrically converted accumulated charges are transferred from the photodiodes to the vertical transfer path, the charge multiplication action is performed by the potential difference sufficient to cause the avalanche multiplication, and the photoelectric conversion is performed. A charge amount larger than the generated charge is taken out as a photodiode output.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a solid-state image sensor according to the present invention.
It is a circuit diagram which shows the schematic structure of the unit pixel sensor of one Example of a 2 pixel mixing type solid-state image sensor.

The unit pixel sensor 1 of the solid-state image pickup device shown in this figure is a sensor which constitutes a two-pixel mixed type AMI (Amplified MOS Imager) formed on a P-type substrate as the solid-state image pickup device. A first A-side photodiode 2 and a first B-side photodiode 3 which are configured to have a small dose amount and whose anodes are connected to the P-type substrate to generate charges according to the amount of incident light. , These first A side and first B side photodiodes 2,
The impurity concentration (dose amount) is higher than that of No. 3, and the anode is connected to the P-type substrate, and
The cathode is connected to the n-layer, and the impurity concentration between the source and drain of the second photodiode 4 that generates electric charges according to the amount of incident light and the impurity concentration between the source and drain become a concentration difference sufficient to cause avalanche multiplication of accumulated charges. A side for mixing stored charges, which is configured such that the gate is connected to the A-side field selection line 5, the source is connected to the cathode of the first A-side photodiode 2, and the drain is connected to the cathode of the second photodiode 4. And a FET 6.

Further, the unit pixel sensor 1 is configured so that the impurity concentration between the source and the drain has a concentration difference sufficient to cause avalanche multiplication of the accumulated charges, like the accumulated charge mixing A-side FET 6. The gate is connected to the B-side field selection line 7, and the source is the first
The stored charge mixing B-side FET 8 connected to the cathode of the B-side photodiode 3 and the drain thereof connected to the cathode of the second photodiode 4, the gate thereof connected to the reset selection line 9, and the drain thereof connected to the read voltage line. 1
A signal which is connected to 0 and whose source is connected to the cathode of the second photodiode 4 and whose gate is connected to the anode of the second photodiode 4 and whose drain is connected to the lead voltage line 10. The amplification FET 12 and the gate are connected to the vertical selection line 13, and the drain is the signal amplification FET 12
And a pixel selection FET 15 whose source is connected to the signal output line 14.

Next, the signal reading operation of the unit pixel sensor 1 will be described with reference to the circuit shown in FIG.

First, in the unit pixel sensor 1, the accumulated charge mixing A-side FET 6 and the accumulated charge mixing B-side FET 8 are used.
And 2 are used as charge mixing FETs of two pixels, and the accumulated charge mixing A-side FET 6 and the accumulated charge mixing B-side FET 8 are alternately switched for each field at the time of imaging, and
Either the accumulated charge of the A-side photodiode 2 or the accumulated charge of the first B-side photodiode 3 is mixed with the accumulated charge of the second photodiode 4.

In this case, in the initial state, the first A side,
The first B-side photodiodes 2 and 3 are depleted, and the second photodiode 4 is set to the reset voltage.

After that, when the second photodiode 4 receives light, holes of the photoexcited electron-hole pairs flow out to the substrate side, and the electrons move to the n-layer side (point A) of the second photodiode. , The potential at point A decreases according to the incident light.

In the first field (field A), a selection pulse is applied to the A-side field selection line 5 to turn on the accumulated charge mixing A-side FET 6 to turn on the first A field.
The accumulated charge of the side photodiode 2 flows into the side of the second photodiode 4 having a lower potential,
It is mixed with the accumulated charges of the photodiode 4 and the potential at the point A decreases.

Similarly to the operation of the second photodiode 4, when the first A-side photodiode 2 receives the light, the potential at the point B decreases according to the incident light.

Similarly, when the first B side photodiode 3 side receives light, the potential at point C decreases in accordance with the incident light.

This potential change is a signal amplification FET.
The pixel selection FET 1 is applied by the read pulse applied to the vertical selection line 13 to the pixel selection FET 12 after being amplified and amplified.
5 is switched and read out as a video signal to the outside through the signal output line 14.

Next, a reset pulse is applied to the reset selection line 9 to turn on the reset FET 11 and the second
The accumulated charge of the photodiode 4 is canceled.

Then, the next field (field B)
Then, a selection pulse is applied to the B-side field selection line 7 to turn on the accumulated charge mixing B-side FET 8, and the accumulated charge of the first B-side photodiode 3 flows into the side of the second photodiode 4 having a lower potential. The charge accumulated in the second photodiode 4 is mixed, and the potential at the point A is lowered.

Thereafter, similar to the operation of the field A, the potential change is applied to the gate of the signal amplification FET 12 to be amplified, and the read pulse applied to the vertical selection line 13 switches the pixel selection FET 15 to output a signal. After being read out to the outside as a video signal via the line 14, a reset pulse is applied to the reset selection line 9 to turn on the reset FET 11, and the charge accumulated in the second photodiode 4 is canceled.

Next, the avalanche multiplication operation of the unit pixel sensor 1 will be described with reference to the potential diagrams shown in FIGS.

First, in FIGS. 2 and 3, the first A side photodiode 2 and the second photodiode 4 shown in FIG.
Of the potential states with the first B-side photodiode 3, the potential state in the first field (field A) is shown, the energy potential for electrons is represented by the vertical axis, and the energy of the electrons becomes higher as it goes up. ing.

In the unit pixel sensor 1 shown in FIG. 1, due to the difference between the impurity dose amount for the first A side and first B side photodiodes 2 and 3 and the impurity dose amount for the second photodiode 4, the first A side, The potential depth of the first B-side photodiodes 2 and 3 becomes shallower than the potential depth of the second photodiode 4, so that the potentials of the first A-side and first B-side photodiodes 2 and 3 are located near the ground level, and
The difference between the depth of the potential in the first A side and first B side photodiodes 2 and 3 and the potential with respect to the reset voltage of the second photodiode 4 is ΔE.

When light is incident on the unit pixel sensor 1 shown in FIG. 1, the photoelectrically converted charges Q1 are accumulated in the first A side and first B side photodiodes 2 and 3 as shown in FIG. The photoelectrically converted electric charge Q2 is accumulated in 4.

In this state, if the accumulated charge mixing A-side FET 6 is turned on before the reading operation of the second photodiode 4, the charge Q1 of the first A-side photodiode 2 becomes
It flows into the side of the second photodiode 4 having a lower potential and is mixed with the charge Q2.

Then, when the charges Q1 and the charges Q2 are mixed, the potential difference ΔE required for causing the avalanche multiplication is ΔD.
As it approaches EBKd, the A-side FET6 for mixing accumulated charge
Carrier multiplication M occurs due to the avalanche at the gate channel and drain junction of the. This can be empirically expressed by the following equation.

M = 1 / {1- (ΔE / ΔEBKd) ⁿ } At this time, in an actual silicon example, the coefficient n is often “4”, and the potential required for avalanche multiplication to occur. Depth difference ΔEBKd is given as a function of the impurity concentration difference between the source and drain and the applied voltage difference.

Assuming that the amount of charge increased by this avalanche multiplication is ΔQ1, the charge (Q1 + Q2) generated by photoelectric conversion by using the multiplication when the charges Q1 and Q2 are mixed as shown in FIG. Larger charge (Q
1 + Q2 + ΔQ1) can be taken as an output.

FIG. 4 is a circuit configuration diagram in the case where the unit pixel sensors 1 shown in FIG. 1 are arranged in a matrix to form an area sensor.

The area sensor 21 shown in this drawing has a plurality of unit pixel sensors 1 arranged in a matrix so that the first A side photodiode 2 and the first B side photodiode 3 are shared with each other, and each unit pixel thereof. The reset vertical scanning circuit 20 for sequentially turning on / off each reset FET 11 constituting the sensor 1 and each pixel selection FET 15 constituting each unit pixel sensor 1 are sequentially turned on / off.
A vertical scanning circuit 16 for reading which is turned off, a horizontal scanning circuit 17 which sequentially generates a reading pulse for each horizontal position,
A plurality of signals are sequentially turned on / off by the read pulse output from the horizontal scanning circuit 17 and sequentially selected from the signal output lines 14 constituting the unit pixel sensors 1 and output from the output terminal 18 to the outside. Horizontal scanning FET1
9 and 9.

While the reading vertical scanning circuit 16 sequentially turns on each unit pixel sensor 1 line by line, the horizontal scanning circuit 17 causes each horizontal scanning FE to be turned on.
T19 is sequentially turned on in the horizontal direction, and the signals output from each unit pixel sensor 1 of the turned on line are sequentially selected and output from the output terminal 18 to the outside.

In parallel with this operation, each unit pixel sensor 1 is sequentially reset line by line by the reset vertical scanning circuit 20 at a predetermined timing.

In this case, each unit pixel sensor 1 shown in FIG.
The area sensor 21 is configured by the above, and the first A-side and first B-side photodiodes 2 and 3 that configure each unit pixel sensor 1
When the respective charges of 1 and the charge of the second photodiode 4 are mixed, the charges are avalanche-multiplied by the accumulated charge mixing A-side FET 6 and the accumulated charge mixing B-side FET 8, which is simpler than the APD. With such a structure and circuit configuration, an avalanche multiplication mechanism for accumulated charges is provided in the vicinity of the light receiving pixel, and a charge amount larger than the charges generated by photoelectric conversion can be taken out as an output.

However, in the unit pixel sensor 1 of FIG. 1, the accumulated charges of the first A side photodiode 2 and the first B side photodiode 3 are avalanche multiplied, but the accumulated charges of the second photodiode 4 are not avalanche multiplied. Therefore, horizontal line unevenness may occur.

Therefore, in order to eliminate such inconvenience, the second photodiode 4 constituting each unit pixel sensor 1 may be shielded from light.

By doing so, the accumulated charge Q2 of the second photodiode 4 can be made negligible as shown in FIG. 5, whereby the charge Q1 of the first A-side photodiode 2 becomes the charge of the second photodiode 4. When mixed with Q2, the second photodiode 4 as shown in FIG.
It is possible to make the electric charge Q2 of the above substantially zero and prevent the horizontal line unevenness from occurring.

However, with this method, the number of horizontal lines is halved (226 in the case of the current NTSC system).
It is necessary to double the number of pixels in the horizontal line.

In the above-described embodiment, the impurity concentration is changed to increase the potential difference ΔE between the source and drain of the accumulated charge mixing A-side FET 6 and the accumulated charge mixing B-side FET 8. However, in order to increase the difference ΔE more effectively, the bias voltages of the first A side and first B side photodiodes 2 and 3 and the second photodiode 4 may be separately applied.

As one method in this case, in FIG. 1, the read voltage VRD applied to the read voltage line 10 is set to a higher potential, and as shown in FIG. The potential of 4 should be made lower.

As a result, the first A side photodiode 2
When the charge Q1 of the second photodiode 4 is mixed with the charge Q2 of the second photodiode 4, a charge amount (Q1 + Q2 + ΔQ) larger than the charge (Q1 + Q2) generated by photoelectric conversion as shown in FIG.
1) can be taken as an output.

In addition to this method, the first A
The bias wirings of the first and second B-side photodiodes 2 and 3 and the second photodiode 4 may be separated.

FIG. 9 is a circuit diagram of a unit pixel sensor 1b to which such a method for separating the bias wiring is applied. In this figure, the same parts as those in FIG. 1 are designated by the same reference numerals.

The unit pixel sensor 1b shown in this figure is different from the unit pixel sensor 1 shown in FIG.
To increase the potential of the side photodiodes 2 and 3,
Two new bias selection lines 25 and 26 and two bias FETs 27 and 28 are provided, and the bias selection line 2
5, 26 makes the reset level of the first A side and first B side photodiodes 2 and 3 a lower bias voltage,
As a result, the first A side and first B side photodiodes 2, 3
By setting the potential at the bottom of the second photodiode 4 to a higher potential level, the difference ΔE between the potentials of the first A side and first B side photodiodes 2 and 3 and the potential of the second photodiode 4 can be further increased, and FIGS. As in the case of, the read voltage VRD applied to the read voltage line 10 is set to a high potential level, and the potential of the second photodiode 4 is made deeper than the potentials shown in FIGS. 2 and 3. Is.

In this case, after the pixels are mixed by the reading mechanism (not shown), the accumulated charge mixing A-side FET is used.
6 is kept off, the bias FET 27 is turned on to turn on the first A side and first B side photodiodes 2, 3
It is set lower than the reset level of.

As a result, in this embodiment, as shown in FIGS. 10 and 11, the first field (field A
As is clear from the potential states of the first A-side photodiode 2, the second photodiode 4, and the first B-side photodiode 3 in (1), the first A-side photodiode 1 and the first B-side photodiode 2, The potential of 3 can be increased.

As a result, the difference Δ in potential between the first A side and first B side photodiodes 2 and 3 and the potential of the second photodiode 4 with respect to the reset voltage.
E can be increased, avalanche multiplication can be easily realized, and the charge ΔQ1 generated by avalanche multiplication can be increased.

In each of the above embodiments, the first
The present invention will be described with reference to an example of a two-pixel mixed type AMI in which charges are increased by using the Abarache multiplication that occurs when the charges stored in the A-side and first B-side photodiodes 2 and 3 are mixed into another second photodiode 4. However, the present invention may be applied to a so-called multi-pixel mixed type AMI in which the accumulated charges of two or more photodiodes are mixed with another one or more photodiodes.

Further, in each of the above-mentioned embodiments, the p-type substrate is used as the semiconductor substrate.
A similar circuit may be configured using a mold substrate.

In each of the above embodiments, the AM
Although the example applied to I is shown, it may be applied to a general MOS type image sensor.

In each of the above embodiments, the first
Avalanche multiplication that occurs when the charges stored in the A-side and first B-side photodiodes 2 and 3 are mixed with another second photodiode is used. However, the present invention is applied to a CCD type solid-state imaging device, and When transferring the converted accumulated charges from the second photodiode 4 to the vertical transfer path, a potential difference sufficient to cause avalanche multiplication may be provided.

[0059]

As described above, according to the present invention, when the photoelectrically converted accumulated charges are mixed, the channel region of the accumulated charge mixing FET formed between the photodiodes has a charge multiplication effect. As a result, a charge amount larger than the charge generated by photoelectric conversion can be taken out as a photodiode output, which makes it possible to realize a solid-state image sensor with higher sensitivity and higher S / N than ever before.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a schematic configuration of a unit pixel sensor of an embodiment of a two-pixel mixed type solid-state imaging device among solid-state imaging devices according to the present invention.

FIG. 2 is a diagram showing a potential state before pixel mixing in a first field of the unit pixel sensor shown in FIG.

3 is a diagram showing a potential state after pixel mixing in the first field of the unit pixel sensor shown in FIG.

FIG. 4 is a circuit configuration diagram when the unit pixel sensors shown in FIG. 1 are arranged in a matrix to form an area sensor.

5 is a diagram showing a potential state before pixel mixing in a first field when the second photodiode of each unit pixel shown in FIG. 4 is shielded from light.

6 is a diagram showing a potential state after pixel mixing in the first field when the second photodiode of each unit pixel shown in FIG. 4 is shielded from light.

7 is a diagram showing a potential state before pixel mixing in the first field when the read voltage VRD of each unit pixel shown in FIG. 4 is set high.

8 is a diagram showing a potential state after pixel mixing in the first field when the read voltage VRD of each unit pixel shown in FIG. 4 is set high.

FIG. 9 is a circuit diagram showing a schematic configuration of a unit pixel sensor of another embodiment of a two-pixel mixed type solid-state imaging device of the solid-state imaging devices according to the present invention.

10 is a diagram showing a potential state before pixel mixing in the first field when the read voltage VRD of each unit pixel shown in FIG. 9 is set high.

11 is a diagram showing a potential state after pixel mixing in the first field when the read voltage VRD of each unit pixel shown in FIG. 9 is set high.

[Explanation of symbols]

1 unit pixel sensor 2 First A side photodiode (photodiode) 3 First B side photodiode (photodiode) 4 Second photodiode (photodiode) 5 A side field selection line 6 A side FET for mixing accumulated charge 7 B side field selection line 8 B-side FET for mixing accumulated charge 9 Reset selection line 10 Lead voltage line 11 Reset FET 12 Signal amplification FET 13 Vertical selection line 14 Signal output line 15 Pixel selection FET

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Claims (2)

(57) [Claims] 1. A solid-state image sensor for performing photoelectric conversion by arranging a plurality of unit pixel sensors in a grid pattern, wherein each unit pixel sensor is of a multi-pixel mixed type, and each of the photodiodes constituting each unit pixel sensor is In the meantime, a process for forming a stored charge mixing FET and providing a concentration difference in the impurity concentration of the source and drain regions of the stored charge mixing FET that is sufficient to cause avalanche multiplication of the stored charge, or the stored charge when the stored charge is mixed A multi-pixel mixed type MOS solid-state element is configured by the unit pixel sensor, by performing a process of providing a potential difference sufficient to cause avalanche multiplication of accumulated charges in the source and drain regions of the mixing FET. Solid-state image sensor. 2. The solid-state image pickup device according to claim 1, wherein among the photodiodes forming the unit pixel sensor, the photodiodes on the mixed side are shielded from light.