JP4212623B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus, and more particularly to an imaging apparatus including a multiplication unit for multiplying electrons.

  2. Description of the Related Art Conventionally, a CCD (Charge Coupled Device) image sensor (imaging device) including a multiplication unit for multiplying electrons is known (see, for example, Patent Document 1).

  FIG. 12 is a cross-sectional view showing the structure of a conventional CCD image sensor disclosed in Patent Document 1. First, referring to FIG. 12, in a conventional CCD image sensor, a gate oxide 102 is formed on the surface of a silicon substrate 101. Also, four gate electrodes 103 to 106 are provided in a predetermined region on the upper surface of the gate oxide 102 with a predetermined interval. The gate electrodes 103 to 106 are configured to be supplied with four-phase clock signals Φ1 to Φ4. In addition, a pixel separation barrier, a temporary storage well, a charge transfer barrier, and a charge integration well are formed in the transfer channel 107 below the gate electrodes 103 to 106, respectively. The pixel separation barrier has a function of separating the temporary accumulation well from the charge accumulation well of the adjacent pixel and transferring electrons of the charge accumulation well of the adjacent pixel to the temporary accumulation well. The temporary storage well has a function of temporarily storing electrons transferred from adjacent pixels. The charge transfer barrier separates the temporary storage well from the charge integration well and has a function of transferring electrons stored in the temporary storage well to the charge integration well. In addition, the charge accumulation well has a function of accumulating electrons transferred from the temporary accumulation well, and also has a function as a multiplication region for multiplying electrons by impact ionization due to an electric field. Note that the charge accumulation well and the gate electrode 106 constitute a multiplication unit. That is, a high electric field region 109 adjusted to a high potential is formed at the interface between the charge transfer barrier and the charge integration well, and electrons accumulated in the temporary storage well are injected into the high electric field region 109. The injected electrons gain energy from the high electric field region 109. The electrons that have gained energy collide with lattice atoms of the silicon substrate 101 while moving in the high electric field region 109, and electrons and holes are generated by the collision. Of the generated electrons and holes, only the electrons are collected in the charge accumulation well by the electric field in the high electric field region 109. As a result, electron multiplication is performed. The multiplication of the electrons is performed in the process of transferring the electrons generated by the photodiode 108 in the light receiving region.

  Next, the multiplication operation of the conventional CCD image sensor will be described with reference to FIG.

  First, an H level clock signal Φ1 is supplied to the gate electrode 103 to turn on the gate electrode 103 and turn off the gate electrode 106 of the adjacent pixel. As a result, electrons accumulated in the charge accumulation well of the adjacent pixel are transferred to the pixel separation barrier.

  Then, an H level clock signal Φ 2 is supplied to the gate electrode 104 to turn on the gate electrode 104, and an L level clock signal Φ 1 is supplied to the gate electrode 103 to turn off the gate electrode 103. As a result, the electrons transferred to the pixel isolation barrier are transferred to the temporary storage well.

  Next, an H level clock signal Φ 4 is supplied to the gate electrode 106 to turn on the gate electrode 106. As a result, a high voltage is applied to the gate electrode 106, and a high electric field region 109 is formed at the interface between the charge transfer barrier and the charge integration well. Thereafter, with the gate electrode 106 kept on, an L level clock signal Φ4 is supplied to the gate electrode 104 to turn off the gate electrode 104, whereby the electrons accumulated in the temporary accumulation well are prevented from becoming a charge transfer barrier. Is transferred to the charge accumulation well. Thereby, the transferred electrons are multiplied by impact ionization by a high electric field, and the multiplied electrons are accumulated in the charge integration well. Note that, since a constant voltage is supplied to the gate electrode 105, the charge transfer barrier is adjusted to a predetermined potential and is constant.

  FIG. 13 is a cross-sectional view when the structure of the conventional CCD image sensor shown in FIG. 12 is applied to a CMOS (Complementary Metal Oxide Semiconductor) image sensor (imaging device). Referring to FIG. 13, in a CMOS image sensor to which a conventional CCD image sensor structure is applied, an n-type impurity region 201a is formed in a predetermined region near the surface of silicon substrate 201, and on the surface of silicon substrate 201. Gate oxide 202 is formed in a region corresponding to n-type impurity region 201a. Further, in addition to four gate electrodes 203 to 206 having the same functions as those of a conventional CCD image sensor, electrons are transferred to the floating diffusion region 208 to a predetermined region on the upper surface of the gate oxide 202, and data is transferred. A gate electrode 207 for reading out is provided. In addition, a CMOS image sensor to which the structure of a conventional CCD image sensor is applied includes a photodiode 209 that generates electrons, a floating diffusion region 208, and the five gate electrodes 203 to 207 in one pixel. Yes.

Japanese Patent No. 3484261

  However, in the conventional CCD image sensor shown in FIG. 12, in order to transfer electrons (carriers) transferred from the photodiode 108 to a charge integration well which is a multiplication region for multiplying electrons, pixel separation is performed. There is an inconvenience that three gate electrodes 103 to 105 are required for forming the barrier, the temporary storage well, and the charge transfer barrier, respectively. Therefore, there is a problem that it is difficult to reduce the size of the imaging device (CCD image sensor). In addition, when the structure of the conventional image sensor is applied to a CMOS image sensor, the electrons (carriers) generated by the photodiode 209 are multiplied to increase the number of electrons as in the case of the conventional CCD image sensor. There is an inconvenience that three gate electrodes 203 to 205 for forming a pixel separation barrier, a temporary storage well, and a charge transfer barrier are necessary for transferring to the charge integration well which is the multiplication region. Therefore, even when the structure of the conventional CCD image sensor is applied to a CMOS image sensor, there is a problem that it is difficult to reduce the size of the imaging device (CMOS image sensor), as in the case of the conventional CCD image sensor. .

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an image pickup device capable of multiplying carriers and miniaturizing the apparatus. Is to provide a device.

Means for Solving the Problems and Effects of the Invention

In order to achieve the above object, an imaging apparatus according to one aspect of the present invention has a photoelectric conversion function, a carrier storage unit for storing carriers generated by photoelectric conversion, and a carrier by impact ionization by an electric field. Provided between the multiplication unit including a multiplication electrode that applies a voltage for generating an electric field for multiplication, and between the carrier storage unit and the multiplication electrode so as to be adjacent to the carrier storage unit and the multiplication electrode The first transfer electrode is provided. The carrier of the present invention means an electron or a hole.

  In the imaging apparatus according to the one aspect, as described above, one first transfer electrode is provided between the carrier storage unit and the multiplication electrode so as to be adjacent to the carrier storage unit and the multiplication electrode, thereby providing a carrier. By applying a voltage to the first transfer electrode provided between the storage unit and the multiplication electrode, the carriers stored in the carrier storage unit are transferred to the multiplication unit that multiplies the carriers by impact ionization due to an electric field. Therefore, the carrier can be transferred from the carrier accumulating unit in which the carriers are accumulated to the multiplying unit for multiplying the carrier with only one first transfer electrode. For this reason, the number of gate electrodes can be reduced, unlike the case of using three gate electrodes, in order to perform temporary storage of carriers and transfer operation to the multiplication unit, thereby downsizing the apparatus. be able to. Further, by providing the multiplication unit for multiplying the carrier, the carrier transferred to the multiplication unit can be multiplied by the impact ionization by the electric field of the multiplication unit. In addition, by configuring the carrier accumulation unit for accumulating carriers so as to have a photoelectric conversion function, it is not necessary to provide a separate photoelectric conversion unit, so that the element can be further reduced in size.

In the imaging apparatus according to the aforementioned aspect preferably, after the voltage capable of multiplying the carrier by impact ionization is applied to the multiplication electrodes, to transfer from the carrier accumulating portion to the multiplication unit carrier the voltage of the first transfer electrode is configured that are controlled. If comprised in this way, by controlling the voltage of one 1st transfer electrode, while having a photoelectric conversion function, a carrier is carried from the carrier storage part in which the carrier was accumulate | stored to the multiplication part which multiplies a carrier. Since the data can be transferred, the carrier can be transferred from the carrier accumulating unit in which the carriers are accumulated to the multiplying unit for multiplying the carrier with one electrode. Therefore, unlike the case where three gate electrodes are used to temporarily store carriers generated by photoelectric conversion and transfer operations to the multiplication unit, the number of gate electrodes can be reduced. In addition, the apparatus can be miniaturized.

In this case, preferably, the carriers are multiplied by impact ionization to return to the carrier accumulating portion, a voltage of the first transfer electrodes and the multiplication electrodes is controlled, it returned from the multiplication unit to the carrier accumulating portion carrier and it is configured to again to transfer to the multiplication unit, the voltage of the first transfer electrodes that are controlled. If comprised in this way, since the multiplication operation | movement of the carrier by impact ionization can be performed in multiple times, the multiplication factor of a carrier can be improved. For this reason, the number of carriers generated by the carrier storage unit having a photoelectric conversion function can be increased more effectively.

In the imaging apparatus for controlling the voltages of the first transfer electrode and the multiplication electrode so that the carriers multiplied by the impact ionization are returned to the carrier storage unit, preferably, the multiplication electrode is connected to the adjacent first transfer electrode. after less than the voltage that is applied is applied, the voltage of the first transfer electrode is configured that are controlled so as to transfer the carrier from the multiplication unit to the carrier storage unit. With this configuration, the potential of the transfer channel under the multiplication electrode is adjusted to a potential smaller than the potential of the transfer channel under the first transfer electrode, so that the carriers accumulated in the transfer channel under the multiplication electrode Can be easily transferred to the transfer channel under the first transfer electrode, and the carrier transferred to the transfer channel under the first transfer electrode can be easily transferred by controlling the voltage of the first transfer electrode. Can be transferred to.

  In the imaging device according to the one aspect described above, preferably, a carrier number voltage conversion unit that converts a current due to the multiplied carrier into a voltage, and a read electrode for performing carrier transfer to the carrier number voltage conversion unit And a carrier storage unit, a multiplication unit having a multiplication electrode, a first transfer electrode, a carrier number voltage conversion unit, and a readout electrode. Thus, it is possible to reduce the size by including a carrier storage unit, a multiplication unit having a multiplication electrode, one first transfer electrode, a carrier number voltage conversion unit, and a readout electrode in one pixel. A possible CMOS image sensor can be provided.

  In the imaging apparatus further including the carrier number voltage conversion unit and the readout electrode, preferably, the readout electrode is adjacent to the multiplication electrode and the carrier number voltage conversion unit between the multiplication electrode and the carrier number voltage conversion unit. Is provided. If comprised in this way, the carrier accumulate | stored in the transfer channel under a multiplication electrode can be easily transferred to a carrier number voltage conversion part by applying a voltage to a read-out electrode.

  In the imaging apparatus further including the carrier number voltage conversion unit and the readout electrode, preferably, the readout electrode is adjacent to the carrier accumulation unit and the carrier number voltage conversion unit between the carrier accumulation unit and the carrier number voltage conversion unit. Is provided. With this configuration, carriers generated by the photoelectric conversion function of the carrier storage unit can be discharged from the carrier storage unit via the readout electrode and the carrier number voltage conversion unit, so that the read operation starts after the imaging period has elapsed. In the meantime, the carriers generated in the carrier storage unit can be easily discharged. Thereby, even when the time from the lapse of the imaging period until the reading operation is started is different for each pixel, the carrier generated in the carrier accumulation unit after the imaging period is started until the reading operation is started, Since it can be suppressed that the signal corresponding to the signal after the imaging time elapses is mixed into the carrier, the imaging time of each pixel even when the time from the elapse of the imaging period to the start of the reading operation varies depending on each pixel. The signal after elapse can be read out accurately.

  The imaging apparatus according to the above aspect preferably further includes a second transfer electrode provided on the carrier storage unit so as to be adjacent to the first transfer electrode. With this configuration, by controlling the voltage applied to the second transfer electrode, the carriers accumulated in the carrier accumulation unit can be easily transferred to the transfer channel below the first transfer electrode, and the first Carriers located in the transfer channel below the transfer electrode can be easily transferred to the carrier storage unit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of the embodiment, a case where the present invention is applied to a passive CMOS image sensor which is an example of an imaging apparatus will be described.

(First embodiment)
FIG. 1 is a plan view showing the overall configuration of a CMOS image sensor according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the structure of the CMOS image sensor according to the first embodiment shown in FIG. It is. 3 is a plan view showing a pixel of the CMOS image sensor according to the first embodiment shown in FIG. 1, and FIG. 4 shows a configuration of the CMOS image sensor according to the first embodiment shown in FIG. FIG. First, the structure of the CMOS image sensor according to the first embodiment will be described with reference to FIGS.

  As shown in FIG. 1, the CMOS image sensor according to the first embodiment includes an imaging unit 2 including a plurality of pixels 1, a row selection register 3, and a column selection register 4. In addition, as shown in FIG. 2, the pixel 1 includes a p-type silicon substrate 10, a gate insulating film 11, one transfer gate electrode 12, one multiplication gate electrode 13, and one readout gate electrode 14. A gate electrode, a photodiode portion (PD) 15, a floating diffusion region 16 composed of an n-type impurity region, and an element isolation region 17 are configured. The gate insulating film 11 is formed on the surface of the p-type silicon substrate 10 at a predetermined interval. The transfer gate electrode 12, the multiplication gate electrode 13, and the read gate electrode 14 are formed in a predetermined region on the upper surface of the gate insulating film 11 with a predetermined interval. The photodiode portion 15 is formed in the vicinity of the surface of the p-type silicon substrate 10 and has a function of generating electrons according to the amount of incident light and accumulating the generated electrons. The photodiode unit 15 is an example of the “carrier storage unit” in the present invention, and the floating diffusion region 16 is an example of the “carrier number voltage conversion unit” in the present invention. The read gate electrode 14 is an example of the “read electrode” in the present invention.

  Here, in the first embodiment, the transfer gate electrode 12 is formed between the photodiode portion 15 and the multiplication gate electrode 13 so as to be adjacent to the photodiode portion 15 and the multiplication gate electrode 13. The transfer gate electrode 12 is an example of the “first transfer electrode” in the present invention, and the multiplication gate electrode 13 is an example of the “multiplication electrode” in the present invention.

The floating diffusion region 16 made of an n-type impurity region is formed on the surface of the p-type silicon substrate 10 and is provided for converting a charge signal generated by transferred electrons into a voltage. The floating diffusion region 16 is formed so as to face the photodiode portion 15 and to be adjacent to the read gate electrode 14 through the transfer gate electrode 12, the multiplication gate electrode 13 and the read gate electrode 14. A transfer channel 19 made of an n-type impurity region is formed near the surface of the p-type silicon substrate 10 located between the photodiode portion 15 and the floating diffusion region 16. The transfer channel 19 has an impurity concentration (n ⁻ ) lower than the impurity concentration (n ⁺ ) of the floating diffusion region 16. The element isolation region 17 is near the surface of the p-type silicon substrate 10 and is formed between the photodiode portion 15 and the floating diffusion region 16 of the adjacent pixel 1. The element isolation region 17 has a function of suppressing electrons generated by the photodiode portion 15 of the adjacent pixel 1 from entering the floating diffusion region 16 in the pixel 1. As shown in FIG. 2, the gate insulating film 11 is formed on the surface of the p-type silicon substrate 10 in the region where the photodiode portion 15, the floating diffusion region 16 and the element isolation region 17 are formed. Absent.

  Further, as shown in FIG. 3, the transfer gate electrode 12, the multiplication gate electrode 13 and the read gate electrode 14 are respectively provided with wiring layers 20, 21 and 22 for supplying a clock signal for voltage control. They are electrically connected via contact parts 12a, 13a and 14a. In addition, a signal line 18 for extracting a signal is electrically connected to the floating diffusion region 16 through a contact portion 16a.

  In addition, as shown in FIG. 2, when an ON signal (H level signal) of the clock signal is supplied to the transfer gate electrode 12, the multiplication gate electrode 13, and the read gate electrode 14, the transfer gate electrode 12 and A voltage of about 2.9 V is applied to the read gate electrode 14, and a voltage of about 24 V is applied to the multiplication gate electrode 13. As a result, the potential of the transfer channel 19 under the transfer gate electrode 12 and the transfer channel 19 under the read gate electrode 14 are adjusted to about 4 V, and the transfer channel 19 under the multiplication gate electrode 13 is , The state is adjusted to a high potential of about 25V. In the state where the off signal (L level signal) of the clock signal is supplied, the transfer channel 19 under the transfer gate electrode 12, the transfer channel 19 under the multiplication gate electrode 13, and the readout gate electrode 14 All of the transfer channels 19 are in a state where the potential is adjusted to about 1V. Further, the photodiode portion 15 and the floating diffusion region 16 are in a state in which the potential is adjusted to about 3 V and about 5 V, respectively.

  Here, in the first embodiment, as illustrated in FIG. 2, the photodiode unit 15 has a function of generating electrons by photoelectric conversion and storing the generated electrons. Further, the transfer gate electrode 12 has a function of transferring electrons accumulated in the photodiode portion 15 to the transfer channel 19 below the multiplication gate electrode 13 by applying a voltage. Further, by applying a high voltage of about 24V to the multiplication gate electrode 13, the transfer channel 19 under the multiplication gate electrode 13 is adjusted to a high potential (about 25V). As a result, a high electric field region 19 a to which a high electric field is applied is formed at the boundary between the transfer channel 19 below the transfer gate electrode 12 and the transfer channel 19 below the multiplication gate electrode 13. When the electrons accumulated in the photodiode portion 15 are transferred and reach the high electric field region 19a, the transferred electrons are multiplied by impact ionization due to the high electric field in the high electric field region 19a. Further, the multiplication gate 25 is constituted by the multiplication gate electrode 13 and the transfer channel 19 below the multiplication gate electrode 13.

Further, the read gate electrode 14 has a function of transferring a charge signal due to electrons multiplied by the high electric field region 19a to the floating diffusion region 16 for reading as a voltage signal when a voltage is applied. As shown in FIG. 4, the CMOS image sensor according to the first embodiment is a reset gate transistor for extracting a signal for each column of a plurality of pixels 1 arranged in a matrix (matrix) in the imaging unit 2. 23, a transistor Tr1, a selection transistor Tr2 connected to the transistor Tr1, and one transistor Tr3. The reset gate transistor 23 has a function of resetting the voltage of the signal line 18 to the reset voltage V _RD (about 5 V) after reading and holding the floating diffusion region 16 in an electrically floating state at the time of reading. . A reset signal is supplied to the gate of the reset gate transistor 23. Further, a reset voltage V _RD (about 5 V) is applied to the drain of the reset gate transistor 23. The source of the reset gate transistor 23 is connected to the signal line 18. The signal line 18 is connected to the gate of the transistor Tr1, the power supply voltage V _DD is connected to the drain of the transistor Tr1, and the drain of the selection transistor Tr2 is connected to the source of the transistor Tr1. . A column selection line is connected to the gate of the selection transistor Tr2, and an output line is connected to the source of the selection transistor Tr2. The drain of the transistor Tr3 is connected to the output line, and the source of the transistor Tr3 is grounded. A predetermined voltage for causing the transistor Tr3 to function as a constant current source is applied to the gate of the transistor Tr3. Further, a source follower circuit is configured by the transistor Tr1 and the transistor Tr3 in each column.

  Next, a read operation of the CMOS image sensor according to the first embodiment will be described with reference to FIG. First, by supplying an H level signal to the wiring layer 22 of a predetermined row, the readout gate electrode 14 of the pixel 1 for one row of the imaging unit 2 is turned on. As a result, electrons generated by the photodiode portion 15 of the pixel 1 for one row are read out to the signal line 18. In this state, since the selection transistor Tr2 is in an off state, no current flows through the source follower circuit including the transistors Tr1 and Tr3. From this state, by sequentially supplying an H level signal to the column selection line, the selection transistor Tr2 is sequentially turned on for each column of pixels 1 of the imaging unit 2. As a result, a current flows sequentially through the transistor Tr1, the selection transistor Tr2, and the transistor Tr3 in each column, so that a signal for each pixel 1 is output. When all outputs are completed, the reset gate transistor 23 is turned on to reset the potential of the signal line 18. By repeating the above operation, the read operation of the CMOS image sensor according to the first embodiment is performed.

  FIG. 5 is a cross-sectional view for explaining the multiplication operation of the CMOS image sensor according to the first embodiment shown in FIG. FIG. 6 is a signal waveform diagram for explaining the multiplication operation of the CMOS image sensor according to the first embodiment shown in FIG. Next, the multiplication operation of the CMOS image sensor according to the first embodiment of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 5, when light is incident on the photodiode unit 15, electrons are generated in the photodiode unit 15 by photoelectric conversion in the period A of FIG. 6. Next, in the period B of FIG. 6, the potential of the transfer channel 19 under the multiplication gate electrode 13 is set to about 25 V by turning on the multiplication gate electrode 13 while keeping the transfer gate electrode 12 in the off state. adjust. At this time, the potential of the transfer channel 19 below the transfer gate electrode 12 is adjusted to about 1V. Since the potential of the photodiode unit 15 is adjusted to about 3 V, the generated electrons are not transferred to the transfer channel 19 below the transfer gate electrode 12 having a lower potential than the photodiode unit 15, and thus the photodiode The state is accumulated in the unit 15.

  Next, in the period C in FIG. 6, the multiplication gate electrode 13 is kept on and the transfer gate electrode 12 is turned on. That is, the transfer channel 19 under the transfer gate electrode 12 is adjusted to a potential of about 4V while the transfer channel 19 under the multiplication gate electrode 13 is adjusted to a high potential of about 25V. Thereby, the electrons accumulated in the photodiode portion 15 are transferred to the transfer channel 19 below the transfer gate electrode 12 adjusted to a potential (about 4 V) higher than the potential (about 3 V) of the photodiode portion 15. At the same time, the electrons transferred to the transfer channel 19 below the transfer gate electrode 12 are multiplied by a multiplication gate adjusted to a potential (about 25 V) higher than the potential (about 4 V) of the transfer channel 19 below the transfer gate electrode 12. It is transferred to the transfer channel 19 under the electrode 13. At this time, electrons transferred from the transfer channel 19 under the transfer gate electrode 12 to the transfer channel 19 under the multiplication gate electrode 13 are transferred to the transfer channel 19 under the transfer gate electrode 12 and the transfer channel under the multiplication gate electrode 13. While moving in the high electric field region 19a formed at the boundary with 19, energy is obtained from the high electric field of the high electric field region 19 a, and the energy-obtained electrons collide with silicon atoms to generate electrons and holes. (Electron impact) causes new electrons to be generated. Thereafter, the electrons transferred from the photodiode portion 15 and the electrons generated by impact ionization are accumulated in the transfer channel 19 below the multiplication gate electrode 13 by the electric field of the high electric field region 19a.

  FIG. 7 is a cross-sectional view for explaining the reverse transfer operation of the CMOS image sensor according to the first embodiment shown in FIG. FIG. 8 is a signal waveform diagram for explaining the reverse transfer operation of the CMOS image sensor according to the first embodiment shown in FIG. Next, the reverse transfer operation of the CMOS image sensor according to the first embodiment of the present invention will be described with reference to FIGS. Note that the reverse transfer operation refers to an operation of transferring electrons accumulated in the transfer channel 19 under the multiplication gate electrode 13 to the photodiode unit 15.

  First, in the period D of FIG. 8, the transfer gate electrode 12 is turned on and the multiplication gate electrode 13 is turned off. As a result, as shown in FIGS. 7 and 8, the transfer channel 19 under the transfer gate electrode 12 is set to about 1V while the potential of the transfer channel 19 under the transfer gate electrode 12 is adjusted to about 4V. The potential is adjusted. For this reason, the electrons accumulated in the transfer channel 19 under the multiplication gate electrode 13 are adjusted to a potential (about 4 V) higher than the potential (about 1 V) of the transfer channel 19 under the multiplication gate electrode 13. The data is transferred to the transfer channel 19 below the gate electrode 12. Next, in the period E of FIG. 8, the multiplication gate electrode 13 is turned off and the transfer gate electrode 12 is also turned off. As a result, the transfer channel 19 under the multiplication gate electrode 13 is in a state in which the potential is adjusted to about 1V, and the transfer channel 19 under the transfer gate electrode 12 is also in the state in which the potential is adjusted to about 4V. The potential is adjusted to about 1 V, which is the same as that of the transfer channel 19 under the gate electrode 13. The photodiode portion 15 is adjusted to a potential (about 3 V) higher than the potential (about 1 V) of the transfer channel 19 under the transfer gate electrode 12 and the potential (about 1 V) of the transfer channel 19 under the multiplication gate electrode 13. It is in the state that was done. For this reason, the electrons transferred to the transfer channel 19 below the transfer gate electrode 12 are transferred to the photodiode unit 15 that is adjusted to a higher potential. In this way, the electrons accumulated in the transfer channel 19 below the multiplication gate electrode 13 are transferred to the photodiode unit 15. Then, the electrons transferred to the photodiode unit 15 are transferred again from the photodiode unit 15 to the transfer channel 19 below the multiplication gate electrode 13 through the high electric field region 19a by the multiplication operation. The multiplication operation and the reverse transfer operation are repeated. Thereby, multiplication of electrons is repeated, and the multiplied electrons are accumulated in the transfer channel 19 below the multiplication gate electrode 13 as a charge signal. In addition, the charge signal due to the electrons thus multiplied and accumulated is read out as a voltage signal through the floating diffusion region 16 and the signal line 18 as in the above-described reading operation.

  In the first embodiment, as described above, one transfer gate electrode 12 is provided between the photodiode portion 15 and the multiplication gate electrode 13 so as to be adjacent to the photodiode portion 15 and the multiplication gate electrode 13. By applying a voltage to the transfer gate electrode 12 provided between the photodiode portion 15 and the multiplication gate electrode 13, the electrons accumulated in the photodiode portion 15 are increased by impact ionization due to an electric field. Since it can be transferred to the high electric field region 19a to be doubled, only one transfer gate electrode 12 can transfer electrons from the photodiode portion 15 in which electrons are accumulated to the high electric field region 19a for multiplying electrons. It can be carried out. Therefore, unlike the case where three gate electrodes are used to temporarily store electrons and transfer them to the high electric field region 19a, the number of gate electrodes can be reduced. can do.

  In the first embodiment, a voltage capable of multiplying electrons by impact ionization is applied to the multiplication gate electrode 13, and then transferred from the photodiode portion 15 to the high electric field region 19a. By configuring so as to control the voltage of the gate electrode 12, by controlling the voltage of one transfer gate electrode 12, from the photodiode portion 15 in which electrons are accumulated to the high electric field region 19a for multiplying electrons. Electrons can be transferred from only the single transfer gate electrode 12 to the high electric field region 19a for multiplying the electrons from the photodiode portion 15 where the electrons are stored. . Therefore, unlike the case where three gate electrodes are used to temporarily store electrons and transfer them to the high electric field region 19a, the number of gate electrodes can be reduced. It can be downsized.

  In the first embodiment, the voltages of the transfer gate electrode 12 and the multiplication gate electrode 13 are controlled so that the electrons multiplied by impact ionization are returned to the photodiode unit 15, and the transfer under the multiplication gate electrode 13 is performed. By configuring the voltage of the transfer gate electrode 12 so that the electrons returned from the channel 19 to the photodiode portion 15 are transferred again to the high electric field region 19a, the electron multiplication operation by impact ionization can be performed. Since it can be performed a plurality of times, the electron multiplication factor can be improved. For this reason, the number of electrons generated by the photodiode unit 15 can be increased more effectively.

  In the first embodiment, a voltage smaller than the voltage applied to the adjacent transfer gate electrode 12 is applied to the multiplication gate electrode 13, and then the photodiode channel is transferred from the transfer channel 19 below the multiplication gate electrode 13. 15 so that the voltage of the transfer gate electrode 12 is controlled so as to transfer electrons to 15, so that the potential of the transfer channel 19 under the multiplication gate electrode 13 becomes equal to the potential of the transfer channel 19 under the transfer gate electrode 12. Therefore, the electrons accumulated in the transfer channel 19 below the multiplication gate electrode 13 can be easily transferred to the transfer channel 19 below the transfer gate electrode 12, and the transfer gate electrode 12 By controlling the voltage, electrons transferred to the transfer channel 19 below the transfer gate electrode 12 can be easily transferred to the photodiode unit 15. It can be sent.

  In the first embodiment, the readout gate electrode 14 is provided between the multiplication gate electrode 13 and the floating diffusion region 16 so as to be adjacent to the multiplication gate electrode 13 and the floating diffusion region 16. By applying a voltage to the electrode 14, electrons accumulated in the transfer channel under the multiplication gate electrode 13 can be easily transferred to the floating diffusion region 16.

(Second Embodiment)
FIG. 9 is a cross-sectional view illustrating a structure of a CMOS image sensor according to the second embodiment of the present invention. Referring to FIG. 9, in the second embodiment, unlike the first embodiment, the structure of a CMOS image sensor including a pixel 30 formed so that the photodiode portion 15 is adjacent to the readout gate electrode 14 will be described. To do.

As a cross-sectional structure of the pixel 30 of the CMOS image sensor according to the second embodiment, as shown in FIG. 9, an element isolation region 17 is formed on the surface of the p-type silicon substrate 10 to isolate each pixel 30. Yes. In addition, the surface of the p-type silicon substrate 10 of each pixel 30 surrounded by the element isolation region 17 is sandwiched with a transfer channel 31 composed of an n-type impurity region at a predetermined interval from one of the element isolation regions 17. A photodiode portion 15 is formed. In addition, a floating diffusion region 16 is formed on the surface of the p-type silicon substrate 10 of each pixel 30 so as to sandwich a transfer channel 32 composed of an n-type impurity region at a predetermined interval from the photodiode portion 15. Yes. Further, the transfer channels 31 and 32 have an impurity concentration (n ⁻ ) lower than the impurity concentration (n ⁺ ) of the floating diffusion region 16. The floating diffusion region 16 is formed adjacent to the other of the element isolation regions 17.

  Here, in the second embodiment, the gate insulating film 33 is formed on the upper surface of the transfer channel 31. In a predetermined region on the upper surface of the gate insulating film 33, a transfer gate electrode 12 and a multiplication gate electrode 13 are formed at a predetermined interval. The transfer gate electrode 12 is formed so as to be adjacent to the photodiode portion 15, and the multiplication gate electrode 13 is formed so as to be adjacent to one of the element isolation regions 17. A gate insulating film 34 is formed on the upper surface of the transfer channel 32. A read gate electrode 14 is formed in a predetermined region on the upper surface of the gate insulating film 34. The read gate electrode 14 is formed between the photodiode portion 15 and the floating diffusion region 16 so as to be adjacent to the photodiode portion 15 and the floating diffusion region 16. Further, the multiplication gate 35 is constituted by the multiplication gate electrode 13 and the transfer channel 31 under the multiplication gate electrode 13.

  In the second embodiment, the transfer channel 31 below the transfer gate electrode 12 is adjusted to a potential of about 4 V when the on signal (H level signal) of the clock signal is supplied to the transfer gate electrode 12. In addition, when an off signal (L level signal) of the clock signal is supplied to the transfer gate electrode 12, the potential is adjusted to about 1V. The transfer channel 31 under the multiplication gate electrode 13 is adjusted to a potential of about 25 V when the on signal (H level signal) of the clock signal is supplied to the multiplication gate electrode 13, and When the clock signal OFF signal (L level signal) is supplied to the double gate electrode 13, the potential is adjusted to about 1V. The transfer channel 32 under the read gate electrode 14 is adjusted to a potential of about 4 V when the on signal (H level signal) of the clock signal is supplied to the read gate electrode 14, and the read gate electrode 14 When the clock signal OFF signal (L level signal) is supplied to 14, the potential is adjusted to about 1V.

  The remaining structure of the second embodiment is the same as that of the first embodiment.

  FIG. 10 is a circuit diagram for explaining an imaging operation of the CMOS image sensor according to the second embodiment of the present invention. Next, an imaging operation of the CMOS image sensor according to the second embodiment will be described with reference to FIGS.

  First, the photodiode portions 15 of all the pixels 30 are initialized. Specifically, as shown in FIG. 10, all the reset gate transistors 23 and the read gate electrode 14 are turned on to discharge electrons accumulated in the photodiode portion 15.

  Next, imaging is performed in all the pixels 30. Specifically, all the reset gate transistors 23 and the read gate electrode 14 are turned off. At this time, all the transfer gate electrodes 12 are turned off. Thereby, electrons generated according to the amount of incident light are accumulated in the photodiode unit 15.

  Next, after a predetermined imaging period has elapsed, a multiplication operation similar to that in the first embodiment is performed in all the pixels 30. Then, after the multiplication operation is performed a plurality of times, the multiplied electrons are accumulated in the transfer channel 31 (see FIG. 9) under the multiplication gate electrode 13. At this time, all the transfer gate electrodes 12 are in an off state.

  Next, the read operation of the accumulated electrons is performed for each row. Specifically, all the read gate electrodes 14 and the reset gate transistors 23 are turned on. Thus, electrons generated in the photodiode unit 15 are discharged while the reading operation for each row is performed. Thereafter, all the reset gate transistors 23 are turned off, and the read gate electrodes 14 in the row where the read operation is not performed are turned off, thereby bringing the floating diffusion region 16 into an electrically floating state. Next, the transfer gate electrode 12 is turned on and the multiplication gate electrode 13 is turned off, so that electrons accumulated in the transfer channel 31 under the multiplication gate electrode 13 are transferred under the transfer gate electrode 12. Transferred to channel 31. Then, by turning off the transfer gate electrode 12, electrons transferred to the transfer channel 31 below the transfer gate electrode 12 are transferred to the photodiode section 15 and the transfer channel 32 below the read gate electrode 14 (see FIG. 9). To the floating diffusion region 16. As a result, a signal corresponding to the electrons supplied to the floating diffusion region 16 appears on the signal line 18. Next, by sequentially turning on the selection transistor Tr2 in each column, current flows sequentially through the transistor Tr1, the selection transistor Tr2, and the transistor Tr3 in each column, so that each pixel in the row where reading is performed is performed. A signal for every 30 is output.

  Next, the readout operation for each row is performed on all rows, thereby completing the imaging operation of the CMOS image sensor.

  In the second embodiment, as described above, the read gate electrode 14 is provided between the photodiode portion 15 and the floating diffusion region 16 so as to be adjacent to the photodiode portion 15 and the floating diffusion region 16, thereby enabling each row. During the reading operation, electrons generated in the photodiode portion 15 can be easily discharged. Thereby, even when the time from the elapse of the imaging period to the start of the reading operation varies depending on each pixel 30, the electrons generated in the photodiode unit 15 during the reading operation of each row are captured in the imaging time. Since it is possible to prevent the electrons accumulated in the transfer channel 31 below the multiplication gate electrode 13 corresponding to the signal after the elapse of time from being mixed, the time until the reading operation is started after the imaging period has elapsed Even when the pixel 30 differs, a signal corresponding to electrons after the imaging time of each pixel 30 can be read out accurately. That is, a CMOS image sensor having a global shutter function can be obtained.

  The remaining effects of the second embodiment are similar to those of the aforementioned first embodiment.

(Third embodiment)
FIG. 11 is a cross-sectional view illustrating a structure of a CMOS image sensor according to a third embodiment of the present invention. With reference to FIG. 11, in the third embodiment, unlike the first embodiment, a structure of a CMOS image sensor including a pixel 40 in which a transfer gate electrode 42 is formed on a photodiode portion 15 will be described.

  As shown in FIG. 11, the cross-sectional structure of the pixel 40 of the CMOS image sensor according to the third embodiment is that a gate insulating film 41 is formed on the upper surface corresponding to the photodiode portion 15 and the transfer channel 19 of the p-type silicon substrate 10. Is formed. A transfer gate electrode 42 is formed in a region corresponding to the photodiode portion 15 on the upper surface of the gate insulating film 41. The transfer gate electrode 42 is an example of the “second transfer electrode” in the present invention. Further, in a region corresponding to the transfer channel 19 on the upper surface of the gate insulating film 41, the transfer gate electrode 12, the multiplication gate electrode 13, and the read gate electrode 14 are formed in order from the photodiode portion 15 side at a predetermined interval. Has been. The transfer gate electrode 42 is configured to be supplied with a voltage of about 2.9 V by being supplied with an ON signal (H level signal) of the clock signal. When a voltage of about 2.9V is applied to the transfer gate electrode 42, the photodiode portion 15 below the transfer gate electrode 42 is adjusted to a potential of about 4V. When the clock signal OFF signal (L level signal) is supplied to the transfer gate electrode 42, the photodiode portion 15 is adjusted to a potential of about 1V.

  The remaining structure of the third embodiment is similar to that of the aforementioned first embodiment.

  Next, an electron transfer operation of the CMOS image sensor according to the third embodiment will be described with reference to FIG.

  First, in the imaging period, the transfer gate electrode 42 is turned on and the transfer gate electrode 12 is turned off. As a result, the photodiode portion 15 is adjusted to a potential of about 4V, and the transfer channel 19 under the transfer gate electrode 12 is adjusted to a potential of about 1V. Accordingly, electrons generated according to the amount of incident light are accumulated in the photodiode unit 15.

  When electrons accumulated in the photodiode portion 15 are transferred to the transfer channel 19 below the transfer gate electrode 12, the transfer gate electrode 12 is turned on and the transfer gate electrode 42 is turned off. As a result, the transfer channel 19 under the transfer gate electrode 12 is adjusted to a potential of about 4V, and the photodiode portion 15 is adjusted to a potential of about 1V. Therefore, the electrons accumulated in the photodiode portion 15 are transferred to the transfer channel 19 below the transfer gate electrode 12 adjusted to a higher potential.

  On the other hand, when electrons located in the transfer channel 19 below the transfer gate electrode 12 are transferred to the photodiode unit 15, the transfer gate electrode 42 is turned on and the transfer gate electrode 12 is turned off. As a result, the photodiode portion 15 is adjusted to a potential of about 4V, and the transfer channel 19 under the transfer gate electrode 12 is adjusted to a potential of about 1V. Accordingly, electrons located in the transfer channel 19 below the transfer gate electrode 12 are transferred to the photodiode unit 15 adjusted to a higher potential.

  In the third embodiment, as described above, by providing the transfer gate electrode 42 on the photodiode portion 15, the electrons accumulated in the photodiode portion 15 can be easily transferred under the transfer gate electrode 12 by the transfer gate electrode 42. In addition to being able to transfer to the transfer channel 19, electrons located in the transfer channel 19 below the transfer gate electrode 12 can be easily transferred to the photodiode unit 15.

  The remaining effects of the third embodiment are similar to those of the aforementioned first embodiment.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the first to third embodiments, an example in which the present invention is applied to a passive type CMOS image sensor which is an example of an imaging apparatus has been described. The present invention may be applied to an active type CMOS image sensor other than the CMOS image sensor.

  In the first to third embodiments, an example in which the present invention is applied to a CMOS image sensor which is an example of an imaging apparatus has been described. However, the present invention is not limited thereto, and is applied to an imaging apparatus other than a CMOS image sensor. May be. For example, the present invention may be applied to a CCD image sensor that is an imaging device other than a CMOS image sensor.

  In the first to third embodiments, the example in which the imaging device is formed on the p-type silicon substrate is shown. However, the present invention is not limited to this, and a p-type impurity diffusion region is formed on the n-type silicon substrate. You may use what was formed as a board | substrate.

  In the first to third embodiments, an example is shown in which electrons are used as carriers. However, the present invention is not limited to this, and the conductivity type of the substrate impurities and the polarity of the applied voltage are all reversed. Alternatively, holes may be used as carriers.

  In the first to third embodiments, the example in which the common reset gate transistor 23 is provided for each column has been described. However, the present invention is not limited thereto, and a reset gate transistor may be provided for each pixel. .

  In the first to third embodiments, the example in which the reading operation is performed for each row has been described. However, the present invention is not limited to this, and the reading operation may be performed for each column.

1 is a plan view showing an overall configuration of a CMOS image sensor according to a first embodiment of the present invention. It is sectional drawing which showed the structure of the CMOS image sensor by 1st Embodiment shown in FIG. FIG. 2 is a plan view showing pixels of the CMOS image sensor according to the first embodiment shown in FIG. 1. FIG. 2 is a circuit diagram showing a configuration of a CMOS image sensor according to the first embodiment shown in FIG. 1. FIG. 5 is a cross-sectional view for explaining a multiplication operation of the CMOS image sensor according to the first embodiment shown in FIG. 1. FIG. 6 is a signal waveform diagram for explaining a multiplication operation of the CMOS image sensor according to the first embodiment shown in FIG. 1. FIG. 5 is a cross-sectional view for explaining a reverse transfer operation of the CMOS image sensor according to the first embodiment shown in FIG. 1. It is a signal waveform diagram for demonstrating the reverse transfer operation | movement of the CMOS image sensor by 1st Embodiment shown in FIG. It is sectional drawing which showed the structure of the CMOS image sensor by 2nd Embodiment of this invention. It is a circuit diagram for demonstrating the imaging operation of the CMOS image sensor by 2nd Embodiment of this invention. It is sectional drawing which showed the structure of the CMOS image sensor by 3rd Embodiment of this invention. It is sectional drawing which showed the structure of the conventional CCD image sensor. FIG. 13 is a cross-sectional view when the structure of the conventional CCD image sensor shown in FIG. 12 is applied to a CMOS image sensor.

Explanation of symbols

1, 30, 40 pixels 12 transfer gate electrode (first transfer electrode)
13 Multiplication gate electrode (multiplication electrode)
14 Read gate electrode (read electrode)
15 Photodiode section (carrier storage section)
16 Floating diffusion area (carrier voltage converter)
25, 35 Multiplier 42 Transfer gate electrode (second transfer electrode)

Claims (8)

A carrier storage unit that has a photoelectric conversion function and stores carriers generated by photoelectric conversion;
A multiplication unit including a multiplication electrode for applying a voltage for generating an electric field for multiplying carriers by impact ionization by an electric field;
An imaging apparatus comprising: a first transfer electrode provided adjacent to the carrier storage unit and the multiplication electrode between the carrier storage unit and the multiplication electrode. After the voltage that can be multiplied by impact ionization carrier is applied to the multiplier electrode, the voltage of the first transfer electrode to transfer the carrier to the multiplying part from the carrier accumulating portion is controlled and it is configured so that Ru is, the imaging apparatus according to claim 1. The carriers are multiplied by the impact ionization back to the carrier accumulating portion, a voltage of the first transfer electrodes and the multiplication electrodes is controlled,
The carrier returned to the carrier storage unit from the multiplying section is configured to again to forward to the multiplier section, the voltage of the first transfer electrodes that are controlled, according to claim 2 Imaging device. The multiplication electrodes, after the voltage lower than the voltage applied to the first transfer electrode adjacent is applied, the first transfer from the multiplier section so as to transfer the carrier to the carrier storage unit voltage electrodes are configured such that are controlled, the imaging apparatus according to claim 3. A carrier number voltage converter for converting the multiplied carrier number into a voltage;
A read electrode for transferring carriers to the carrier number voltage converter,
5. The device according to claim 1, wherein the carrier storage unit, the multiplication unit having the multiplication electrode, the first transfer electrode, the carrier number voltage conversion unit, and the readout electrode are included in one pixel. The imaging device described.   The imaging device according to claim 5, wherein the readout electrode is provided between the multiplication electrode and the carrier number voltage conversion unit so as to be adjacent to the multiplication electrode and the carrier number voltage conversion unit. .   The imaging device according to claim 5, wherein the readout electrode is provided between the carrier storage unit and the carrier number voltage conversion unit so as to be adjacent to the carrier storage unit and the carrier number voltage conversion unit. .   The imaging device according to claim 1, further comprising a second transfer electrode provided adjacent to the first transfer electrode on the carrier storage unit.

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