JP2009130669A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus capable of suppressing an increase of noises. <P>SOLUTION: The CMOS image sensor (imaging apparatus) includes: an electron accumulating part 3b for accumulating electrons; an accumulation gate electrode 10 for accumulating electrons in the electron accumulating part 3b; a transfer gate electrode 9 for transferring electrons to the electron accumulating part 3b; a floating diffusion area 5 for converting electrons to voltages; a readout gate electrode 11 for transferring electrons accumulated in the electron accumulating part 3b to the floating diffusion area 5; and a transfer channel 3 provided to a lower part of each electrode for forming a path for transferring electrons. Impurity concentration of the transfer channel 3 under the accumulation gate electrode 10 is higher than the impurity concentration of the transfer channel 3 under the transfer gate electrode 9 and the readout gate electrode 11. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an imaging apparatus, and more particularly, to an imaging apparatus provided with an electrode for generating an electric field for accumulating signal charges.

  2. Description of the Related Art Conventionally, an imaging device including an electrode for generating an electric field for accumulating electrons (signal charges) is known (for example, see Non-Patent Document 1).

  Non-Patent Document 1 discloses that a photodiode for converting light incident by photoelectric conversion into electrons, an electrode for reading out charges accumulated in the photodiode, and for converting the accumulated electrons into an electrical signal. A conventional general CMOS image sensor having a floating diffusion region is disclosed.

Basics and Applications of CCD / CMOS Image Sensors (P.189-P.191) CQ Publisher Kazuya Yonemoto (issued February 1, 2004)

  In the conventional general CMOS image sensor as described in Non-Patent Document 1, when the incident light is low illuminance, since the signal charge is small, the readout noise becomes dominant, and the SN ratio (signal to noise ratio). Has the disadvantage of lowering. On the other hand, there is a method of accelerating electrons by applying a high voltage to the accumulated electrons and increasing (multiplying) the electrons by colliding with lattice atoms in the impurity region which is an electron holding region. Conceivable. However, in the conventional general CMOS image sensor, an electrode having a large capacity for holding electrons is not provided. Therefore, when electrons (signal charges) are increased (multiplied), the multiplied electrons are increased. It is considered that there are cases where all (signal charge) cannot be retained. As a result, the ratio of the noise (Noise) to the signal (Signal) in the S / N ratio becomes large, which causes a problem that the noise in the CMOS image sensor relatively increases.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an imaging apparatus capable of suppressing an increase in noise.

  In order to achieve the above object, an imaging apparatus according to one aspect of the present invention stores a signal charge, transfers a charge storage part, and a first electrode for storing the signal charge in the charge storage part. The second electrode for transferring the signal charge to the charge storage unit, the voltage conversion unit for converting the signal charge to a voltage, and the first electrode and the voltage conversion unit are provided and stored in the charge storage unit. A third electrode for transferring the signal charge to the voltage converter, and an impurity region provided at least below the first electrode, the second electrode, and the third electrode for forming a path for transferring the signal charge The impurity concentration of the region corresponding to the lower part of the first electrode in the impurity region is at least higher than the impurity concentration of the region corresponding to the lower part of the second and third electrodes.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view showing the overall configuration of a CMOS image sensor according to a first embodiment of the present invention. 2 and 3 are sectional views showing the structure of the CMOS image sensor according to the first embodiment shown in FIG. 4 is a plan view showing a pixel of the CMOS image sensor according to the first embodiment shown in FIG. 1, and FIG. 5 shows a circuit configuration of the CMOS image sensor according to the first embodiment shown in FIG. It is the circuit diagram shown. First, the structure of the CMOS image sensor according to the first embodiment will be described with reference to FIGS. In the first embodiment, a case where the present invention is applied to an active CMOS image sensor which is an example of an imaging apparatus will be described.

  As shown in FIG. 1, the CMOS image sensor according to the first embodiment includes an imaging unit 51 including a plurality of pixels 50 arranged in a matrix (matrix), a row selection register 52, and a column selection register 53. I have.

As a cross-sectional structure of the pixel 50 of the CMOS image sensor according to the first embodiment, as shown in FIGS. 2 and 3, the surface of the p-type well region 1 formed on the surface of an n-type silicon substrate (not shown). In addition, an element isolation region 2 for isolating each pixel 50 is formed. Further, a photodiode portion (PD) is provided on the surface of the p-type well region 1 of each pixel 50 surrounded by the element isolation region 2 at a predetermined interval so as to sandwich the transfer channel 3 made of an n ⁻ -type impurity region. A floating diffusion region 5 (FD) composed of 4 and n-type impurity regions is formed. The transfer channel 3 and the floating diffusion region 5 are examples of the “impurity region” and the “voltage converter” in the present invention, respectively.

  The photodiode unit 4 has a function of generating electrons in accordance with the amount of incident light and storing the generated electrons. The photodiode portion 4 is formed adjacent to the element isolation region 2 and adjacent to the transfer channel 3. The floating diffusion region 5 has a function of holding a charge signal due to transferred electrons and converting the charge signal into a voltage. The floating diffusion region 5 is formed adjacent to the element isolation region 2 and adjacent to the transfer channel 3. Thus, the floating diffusion region 5 is formed so as to face the photodiode portion 4 through the transfer channel 3.

A gate insulating film 6 made of SiO ₂ is formed on the upper surface of the transfer channel 3. On the gate insulating film 6, the transfer gate electrode 7, the multiplication gate electrode 8, the transfer gate electrode 9, the storage gate electrode 10, and the read gate electrode 11 are provided from the photodiode portion 4 side to the floating diffusion region 5. It is formed in this order toward the side. In addition, a reset gate electrode 12 is formed via a gate insulating film 6 at a position sandwiching the floating diffusion region 5 with the readout gate electrode 11 and faces the floating diffusion region 5 with the reset gate electrode 12 interposed therebetween. A reset drain region 13 is formed at the position. The transfer channel 3 under the multiplication gate electrode 8 is provided with an electron multiplication unit 3a, and the transfer channel 3 under the storage gate electrode 10 is provided with an electron storage unit 3b. Note that the multiplication gate electrode 8, the transfer gate electrode 9, the storage gate electrode 10 and the readout gate electrode 11 are respectively the “fourth electrode”, “second electrode”, “first electrode” and “third” of the present invention. It is an example of an “electrode”. The electron multiplying unit 3a is an example of the “charge increasing unit” in the present invention, and the electron accumulating unit 3b is an example of the “charge accumulating unit” in the present invention.

  The transfer gate electrode 7 is formed between the photodiode portion 4 and the multiplication gate electrode 8. The read gate electrode 11 is formed between the storage gate electrode 10 and the floating diffusion region 5. The read gate electrode 11 is formed adjacent to the floating diffusion region 5.

Here, in the first embodiment, the impurity concentration in the region under the storage gate electrode 10 (electron storage unit 3 b) of the transfer channel 3 is higher than the impurity concentration in the region under the electrode other than the storage gate electrode 10. It is configured. Specifically, for example, under the condition that the gate insulating film 6 has a thickness of about 50 nm, the peak concentration of the impurity in the impurity region (transfer channel 3) under the electrode other than the storage gate electrode 10 is about 8.5 × 10. ^In contrast to ¹⁶ cm ⁻³ , the impurity peak concentration in the impurity region (electron accumulating portion 3 b) under the storage gate electrode 10 is configured to be about 2.5 × 10 ¹⁷ cm ⁻³ . . Further, for example, As (arsenic) or the like is implanted as an impurity, and the depth of the peak concentration is configured to be about 0.1 μm from the surface of the transfer channel 3. Thereby, when the same level signal is supplied to each electrode (when the same voltage is applied), the potential of the transfer channel 3 under the storage gate electrode 10 is changed to the transfer channel 3 under the electrode other than the storage gate electrode 10. It is configured to be higher than the potential.

  As shown in FIGS. 3 and 4, the transfer gate electrode 7, the multiplication gate electrode 8, the transfer gate electrode 9, the storage gate electrode 10 and the read gate electrode 11 are respectively connected to the contact portions 7a, 8a, 9a, Wiring layers 20, 21, 22, 23, and 24 that supply clock signals Φ1, Φ2, Φ3, Φ4, and Φ5 for voltage control are electrically connected via 10a and 11a. The wiring layers 20, 21, 22, 23, and 24 are formed for each row, and the transfer gate electrode 7, the multiplication gate electrode 8, the transfer gate electrode 9, and the storage gate of the plurality of pixels 50 in each row. The electrode 10 and the read gate electrode 11 are electrically connected to each other. The floating diffusion region 5 is electrically connected to a signal line 25 for taking out a signal through a contact portion 5a.

  Further, as shown in FIG. 3, the transfer gate electrode 7, the transfer gate electrode 9, the storage gate electrode 10 and the read gate electrode 11 are respectively connected to the clock signals Φ1, Φ3, When ON signals (H level signals) of Φ4 and Φ5 are supplied, a voltage of about 2.9 V is applied to the transfer gate electrode 7, the transfer gate electrode 9, the storage gate electrode 10 and the read gate electrode 11. It is comprised so that. The voltage applied when an ON signal (H level signal) is supplied to each of the transfer gate electrode 7, the transfer gate electrode 9, the storage gate electrode 10 and the read gate electrode 11 is the It is an example of “a voltage of 2”.

  Here, in the first embodiment, when a voltage of about 2.9 V is applied to the transfer gate electrode 7, the transfer gate electrode 9, the storage gate electrode 10 and the read gate electrode 11 (when an H level signal is supplied). ), The transfer channel 3 under the transfer gate electrode 7, under the transfer gate electrode 9 and under the read gate electrode 11 is adjusted to a potential of about 4 V, and under the storage gate electrode 10 having a high concentration. The transfer channel 3 (electron accumulating unit 3b) is adjusted to a potential of about 6V.

  Further, when the ON signal (H level signal) of the clock signal Φ 2 is supplied from the wiring layer 21 to the multiplication gate electrode 8, a voltage of about 24 V is applied to the multiplication gate electrode 9. Has been. Thus, when the ON signal (H level signal) of the clock signal Φ2 is supplied to the multiplication gate electrode 9, the transfer channel 3 under the multiplication gate electrode 9 is adjusted to a high potential of about 25V. It is configured to be in a state. The voltage applied when the ON signal (H level signal) is supplied to the multiplication gate electrode 8 is an example of the “third voltage” in the present invention.

  The transfer gate electrode 7, the multiplication gate electrode 8, the transfer gate electrode 9, the storage gate electrode 10 and the read gate electrode 11 are supplied to the off signals (L level signals) of the clock signals Φ1, Φ2, Φ3, Φ4 and Φ5, respectively. ) Is supplied, a voltage of about 0 V is applied to the transfer gate electrode 7, the multiplication gate electrode 8, the transfer gate electrode 9, the storage gate electrode 10 and the read gate electrode 11. . At this time, in the first embodiment, in the transfer channel 3, the transfer channel 3 under the transfer gate electrode 7, under the multiplication gate electrode 8, under the transfer gate electrode 9 and under the read gate electrode 11 is at a potential of about 1.5V. In addition to the adjusted state, the potential of the transfer channel 3 (electron storage unit 3b) under the storage gate electrode 10 configured to be high in concentration is configured to be adjusted to a potential of about 3.5V. ing. The voltage applied when an off signal (L level signal) is supplied to each electrode is an example of the “first voltage” in the present invention.

  As described above, in the first embodiment, the potential (about 3.5 V) of the storage gate electrode 10 when the off signal is supplied is below the transfer gate electrode 9 and the readout gate electrode 11 when the off signal is supplied. The transfer channel 3 is configured to be higher than the potential (about 1.5 V). Further, the potential (about 3.5 V) of the storage gate electrode 10 when the off signal is supplied is the potential of the transfer channel 3 below the transfer gate electrode 9 and the readout gate electrode 11 when the on signal is supplied (about 3.5V). It is configured to be smaller than about 4V).

  The floating diffusion region 5 is adjusted to have a potential of about 5V. The reset drain region 13 is adjusted to have a potential of about 5 V and has a function as a discharge unit for electrons held in the floating diffusion region 5.

  Further, the transfer gate electrode 7 is supplied with an ON signal, so that the electrons generated by the photodiode unit 4 are transferred to the transfer channel 3 below the multiplication gate electrode 8 via the transfer channel 3 below the transfer gate electrode 7. It has the function to transfer to the electron multiplier part 3a located in. The transfer channel 3 below the transfer gate electrode 7 is connected to the photodiode portion 4 and the transfer channel below the multiplication gate electrode 8 when an off signal (L level signal) is supplied to the transfer gate electrode 7. 3 (electron multiplying unit 3a) functions as a separation barrier.

  Further, the multiplication gate electrode 8 is configured such that a high electric field is applied to the electron multiplication section 3 a located in the transfer channel 3 below the multiplication gate electrode 8 when an ON signal is supplied. Then, the electrons transferred from the photodiode portion 4 through the transfer channel 3 under the transfer gate electrode 7 are accelerated by a high electric field generated in the electron multiplying portion 3a, and by impact ionization with lattice atoms in the impurity region. It is configured to be multiplied.

  Further, the transfer gate electrode 9 is supplied with an ON signal so that the transfer channel 3 under the multiplication gate electrode 8 (electron multiplication unit 3a) and the electrons provided in the transfer channel 3 under the storage gate electrode 10 are supplied. It has a function of transferring electrons to and from the storage unit 3b. In addition, the transfer gate electrode 9 is supplied with an off signal so that electrons are transferred between the electron multiplying portion 3a under the multiplying gate electrode 8 and the electron accumulating portion 3b under the accumulating gate electrode 10. It functions as a charge transfer barrier for suppression.

  Further, the read gate electrode is supplied with an ON signal (H level signal), thereby transferring electrons accumulated in the transfer channel 3 (electron accumulating portion 3 b) under the accumulation gate electrode 10 to the floating diffusion region 5. It has a function. Further, when an OFF signal (L level signal) is supplied to the read gate electrode 11, the function of distinguishing the transfer channel 3 (electron accumulating portion 3 b) and the floating diffusion region 5 below the accumulation gate electrode 10 is provided. Have.

  4 and 5, each pixel 50 includes a transfer gate electrode 7, a multiplication gate electrode 8, a transfer gate electrode 9, a storage gate electrode 10, a read gate electrode 11, and a reset gate. A reset gate transistor Tr1, including an electrode 12, an amplification transistor Tr2, and a pixel selection transistor Tr3 are provided. A photodiode portion 4 is connected to the transfer gate electrode 7. A reset gate line 30 is connected to the reset gate electrode 12 of the reset gate transistor Tr1 through a contact portion 12a, and a reset signal is supplied. The drain (reset drain 13) of the reset gate transistor Tr1 is connected to the power supply potential (VDD) line 31 through the contact portion 13a. The floating diffusion region 5 constituting the source of the reset gate transistor Tr1 and the source of the read gate electrode 11 and the gate 40 of the amplification transistor Tr2 are connected by a signal line 25 through contact portions 5a and 40a. Further, the drain of the pixel selection transistor Tr3 is connected to the source of the amplification transistor Tr2. The row selection line 32 is connected to the gate 41 of the pixel selection transistor Tr3 via a contact portion 41a, and the output line 33 is connected to the source via a contact portion 42.

  The CMOS image sensor according to the first embodiment is configured to reduce the number of wirings and the number of transistors for decoding by performing the above circuit configuration. As a result, the entire CMOS image sensor can be reduced in size. By performing this circuit configuration, on / off control of the read gate electrode 11 is performed for each row, while on / off control of gate electrodes other than the read gate electrode 11 is performed for the entire pixel 50.

  6 and 8 are signal waveform diagrams for explaining electron transfer and multiplication operations of the CMOS image sensor according to the first embodiment of the present invention. 7 and 9 are potential diagrams for explaining an electron transfer operation and a multiplication operation of the CMOS image sensor according to the first embodiment of the present invention. Next, the electron transfer operation and the multiplication operation of the CMOS image sensor according to the first embodiment will be described with reference to FIGS.

  First, when light enters the photodiode unit 4, electrons are generated in the photodiode unit 4 by photoelectric conversion. 6 and FIG. 7, a voltage of about 2.9 V is applied to the transfer gate electrode 7 after a voltage of about 24 V is applied to the multiplication gate electrode 8. Thus, the potential of the transfer channel 3 under the transfer gate electrode 7 is adjusted to about 4V while the potential of the transfer channel 3 under the multiplication gate electrode 8 is adjusted to a high potential of about 25V. At this time, the electrons generated by the photodiode portion 4 (about 3 V) are below the multiplication gate electrode 8 having a higher potential (about 25 V) via the transfer channel 3 (about 4 V) below the transfer gate electrode 7. Are transferred to the transfer channel 3 (electron multiplier 3a) and electrons are multiplied by impact ionization in the electron multiplier 3a.

  Next, in period B, after a voltage of about 2.9 V is applied to the transfer gate electrode 9, a voltage of about 0 V is applied to the multiplication gate electrode 8. As a result, electrons are transferred from the electron multiplier 3a (about 1.5 V) below the multiplication gate electrode 8 to the transfer channel 3 below the transfer gate electrode 9 having a higher potential (about 4 V). In the period C, a voltage of about 0 V is applied to the transfer gate electrode 9. Thereby, electrons are transferred from the transfer channel 3 under the transfer gate electrode 9 to the transfer channel 3 (electron storage unit 3b) under the storage gate electrode 10 having a higher potential (about 3.5 V). At this time, in the first embodiment, the state in which electrons are accumulated in the electron accumulation unit 3b is maintained in a state in which the off voltage is applied to each electrode.

  Then, during period D, a voltage of about 2.9 V is applied to the read gate electrode 11, whereby the potential of the transfer channel 3 under the read gate electrode 11 is adjusted to a state of about 4V. At this time, since the transfer channel 3 (electron accumulating portion 3b) under the storage gate electrode 10 is adjusted to a potential of about 3.5V, electrons pass through the transfer channel 3 (about 4V) under the read gate electrode 11. Thus, the data is transferred to the floating diffusion region 5 that is adjusted to a higher potential. Thus, the electron transfer operation is completed.

  In the electron multiplication operation, electrons are stored in the transfer channel 3 (electron storage unit 3b) under the storage gate electrode 10 by performing the operations in the periods A to C in FIGS. In the period E shown in FIGS. 8 and 9, the multiplication gate electrode 8 is turned on, and in the period F, the transfer gate electrode 9 is turned on. Thereby, after the transfer channel 3 (electron multiplier 3a) under the multiplication gate electrode 8 is adjusted to a potential of about 25V, the transfer channel 3 under the transfer gate electrode 9 is adjusted to a potential of about 4V. become. At this time, in the first embodiment, since the storage gate electrode 10 is maintained in the off state, the potential of the transfer channel 3 (electron storage unit 3b) under the storage gate electrode 10 is maintained at about 3.5V. ing. Therefore, the electrons accumulated in the electron accumulating portion 3b are transferred via the transfer channel 3 (about 4V) under the transfer gate electrode 9 to the transfer channel 3 (electron multiplying portion) under the multiplication gate electrode 8 having a higher potential. 3a) is transferred to (about 25V). As described above, in the first embodiment, the transfer operation and increase of the electrons stored in the transfer channel 3 (electron storage unit 3b) under the storage gate electrode 10 are performed while the off signal is supplied to the storage gate electrode 10. Double operation is performed.

  Further, the electrons are multiplied as described above by being transferred to the electron multiplier 3a. Then, in the period G, the multiplication operation is completed by turning off the transfer gate electrode 9. Control is performed so that the operations in the above-described periods A to C and periods E to G (electron transfer operation between the electron multiplying unit 3a and the electron accumulating unit 3b) are performed a plurality of times (for example, about 400 times). As a result, the electrons transferred from the photodiode unit 4 are multiplied by about 2000 times. Further, the charge signal due to the electrons thus multiplied and accumulated is read out as a voltage signal through the floating diffusion region 5 and the signal line 25 by the above-described reading operation.

  In the first embodiment, as described above, the impurity concentration of the transfer channel 3 (electron storage unit 3b) under the storage gate electrode 10 is higher than the impurity concentration of the transfer channel 3 under the electrodes other than the storage gate electrode 10. With this configuration, when the same voltage is applied to each electrode (when a signal of the same level is supplied), the potential of the electron storage unit 3b becomes larger than the potential of the transfer channel 3 below each electrode. Therefore, a larger amount of electrons can be held. Therefore, since the signal amount with respect to the readout noise is increased by multiplying the electrons, the SN ratio at the time of low illuminance can be improved. In addition, since the multiplied electrons can be held, it is possible to suppress an increase in noise due to an increase in the ratio of noise to signal in the SN ratio.

  In the first embodiment, the potential (about 3.5 V) of the transfer channel 3 (electron storage unit 3b) under the storage gate electrode 10 when the off signal is supplied is the same as that when the off signal is supplied. By configuring the transfer channel 3 to be higher than the potential (about 1.5 V) of the transfer channel 3 below the transfer gate electrode 9 and the read gate electrode 11, the electron storage unit 3b can be turned on without turning on the storage gate electrode 10. Can hold electrons. At this time, the potential (about 1.5 V) of the transfer channel 3 below the transfer gate electrode 9 and the readout gate electrode 11 is lower than the potential (about 3.5 V) of the electron storage portion 3b. The potential barrier in the transfer channel 3 under the gate electrode 9 and under the readout gate electrode 11 is increased. Therefore, it is possible to reliably suppress the movement of electrons from the electron storage unit 3b. Further, electrons can be held while the storage gate electrode 10 is in an off state. That is, electrons can be reliably held in a state where no voltage is applied to the storage gate electrode 10.

  In the first embodiment, the potential (about 3.5 V) of the transfer channel 3 (electron storage unit 3b) under the storage gate electrode 10 when the off signal is supplied is the same as that when the on signal is supplied. By being configured to be lower than the potential (about 4 V) of the transfer channel 3 below the read gate electrode 11, the potential difference between the off-state electron storage portion 3b and the floating diffusion region 5 when the read gate electrode 11 is on. Can be formed, and electrons can be transferred more easily. That is, the electron transfer efficiency can be increased by the potential difference between the off-state electron storage portion 3b and the floating diffusion region 5.

  In the first embodiment, the potential (about 3.5 V) of the transfer channel 3 (electron storage unit 3b) under the storage gate electrode 10 when the off signal is supplied is the same as that when the on signal is supplied. By configuring so as to be lower than the potential (about 4 V) of the transfer channel under the transfer gate electrode 9, electrons can be transferred to the electron multiplier section 3a while the storage gate electrode 10 is kept off. Therefore, the electrons stored in the electron storage unit 3b can be easily multiplied.

  In the first embodiment, the electron multiplication operation by the transfer of electrons from the electron storage unit 3b to the electron multiplication unit 3a and the electron multiplication unit in the state where the off signal is supplied to the storage gate electrode 10 By performing the transfer operation of electrons from 3a to the electron storage unit 3b alternately and repeatedly, both the transfer operation and the multiplication operation of the electrons are performed with the storage gate electrode 10 kept in the OFF state. be able to. Therefore, the complication of the control can be suppressed accordingly.

(Second Embodiment)
10 and 12 are signal waveform diagrams for explaining an electron transfer operation and a multiplication operation of the CMOS image sensor according to the second embodiment of the present invention. FIGS. 11 and 13 are potential diagrams for explaining an electron transfer operation and a multiplication operation of the CMOS image sensor according to the second embodiment of the present invention. Referring to FIGS. 10 to 13, in the second embodiment, in the configuration of the CMOS image sensor in the first embodiment, an ON signal is supplied to storage gate electrode 10 to perform an electron transfer operation and a multiplication operation. An example will be described. The configuration of the second embodiment is the same as that of the first embodiment.

  First, the electron transfer operation of the CMOS image sensor according to the second embodiment will be described. As shown in FIGS. 10 and 11, by performing the operations in the period A and the period B of the first embodiment described above, the electrons generated by the photodiode unit 4 reach the transfer channel 3 below the transfer gate electrode 9. Transferred. In the period H, the storage gate electrode 10 is turned on and the transfer gate electrode 9 is turned off. Thereby, after the transfer channel 3 (electron accumulating portion 3b) under the storage gate electrode 10 is adjusted to a potential of about 6V, the transfer channel 3 under the transfer gate electrode 9 is adjusted to a potential of about 1.5V. become. Then, the electrons transferred to the transfer channel 3 below the transfer gate electrode 9 are transferred to the electron storage unit 3b having a higher potential. Next, in period I, after the read gate electrode 11 is turned on and the storage gate electrode 10 is turned off, the transfer channel 3 under the read gate electrode 11 is adjusted to a potential of about 4 V. The transfer channel 3 under the storage gate electrode 10 is adjusted to a potential of about 3.5V. As a result, electrons are transferred to the floating diffusion region 5 via the transfer channel 3 below the read gate electrode 11 in the electron storage portion 3b. Thus, the electron transfer operation is completed.

  Next, the electron multiplication operation of the CMOS image sensor according to the second embodiment will be described. As shown in FIG. 12 and FIG. 13, by performing the operations of the period A, the period B, and the period H of the first and second embodiments described above, the storage gate electrode 10 is turned on and the storage gate electrode 10 Electrons are stored in the lower electron storage unit 3b. At this time, by setting the multiplication gate electrode 8 to the ON state in the period J, the electron multiplication section 3a under the multiplication gate electrode 8 is adjusted to a potential of about 25V. In the period K, after the transfer gate electrode 9 is turned on, the storage gate electrode 10 is turned off. Thereby, after the transfer channel 3 under the transfer gate electrode 9 is adjusted to a potential of about 4V, the potential of the electron storage portion 3b under the storage gate electrode 10 is adjusted to about 3.5V. As described above, electrons are transferred from the electron accumulating unit 3b to the electron multiplying unit 3a via the transfer channel 3 below the transfer gate electrode 9. In the period L, the transfer gate electrode 9 is turned off, so that the transfer channel 3 under the transfer gate electrode 9 is adjusted to a potential of about 1.5V. Further, the electrons are multiplied by being transferred to the electron multiplier 3b.

  As described above, in the second embodiment, the transfer operation and multiplication operation of electrons are performed by turning on the storage gate electrode 10. As in the first embodiment, the operations of period A, period B, and period H to period L (transfer operation between the electron multiplying unit 3a and the electron accumulating unit 3b) are performed a plurality of times (for example, about 400 times). As a result, the electrons transferred from the photodiode unit 4 are multiplied by about 2000 times.

  In the second embodiment, as described above, by configuring the storage gate electrode 10 to be in an ON state and storing electrons, the electron storage unit 3b is configured to have a high potential as the concentration is increased. Therefore, a large amount of electrons can be held in the electron storage unit 3b accordingly. Therefore, even if the electrons are multiplied to a larger amount, they can be reliably held. At this time, the potential difference between the transfer channel 3 below the transfer gate electrode 9 and the read gate electrode 11 to which the OFF signal is supplied and the electron storage unit 3b is compared with the potential difference when the storage gate electrode 10 is turned on. Become bigger. Accordingly, since the potential barrier of the transfer channel 3 below the transfer gate electrode 9 and the read gate electrode 11 becomes relatively large, electrons can be reliably held in the electron storage portion 3b.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the first and second embodiments, an active type CMOS image sensor that amplifies a charge signal in each pixel 50 is shown as an example of an imaging apparatus. However, the present invention is not limited to this, and each pixel The present invention is also applicable to a passive type CMOS image sensor that does not amplify a charge signal.

  In the first and second embodiments, when the transfer gate electrode 7, the transfer gate electrode 9, and the read gate electrode 11 are in the on state, the transfer under the transfer gate electrode 7, the transfer gate electrode 9, and the read gate electrode 11 is performed. Although an example in which the channel 3 is adjusted to a potential of about 4 V is shown, the present invention is not limited to this, and the transfer is performed when the transfer gate electrode 7, the transfer gate electrode 9, and the read gate electrode 11 are in the on state. The transfer channel 3 under the gate electrode 7, the transfer gate electrode 9, and the read gate electrode 11 may be adjusted to different potentials. In this case, it is necessary to control the potential of the transfer channel 3 under the transfer gate electrode 9 and the readout gate electrode 11 in the ON state to be higher than the potential of the transfer channel 3 under the storage gate electrode 10 in the OFF state. There is.

  In the first and second embodiments, the transfer channel 3, the photodiode portion 4, and the floating diffusion region 5 are formed on the surface of the p-type well region 1 formed on the surface of the n-type silicon substrate (not shown). However, the present invention is not limited to this, and the transfer channel 3, the photodiode portion 4, and the floating diffusion region 5 may be formed on the surface of the p-type silicon substrate.

  In the first and second embodiments, electrons are used as signal charges. However, the present invention is not limited to this, and the substrate impurity conductivity type and the applied voltage polarity are all reversed. Thus, holes may be used as signal charges.

  In the first and second embodiments, the example in which As (arsenic) is implanted to increase the concentration of the transfer channel 3 under the storage gate electrode 10 has been shown. However, the present invention is not limited to this. Dopes other than (arsenic) may be injected.

1 is a plan view showing an overall configuration of a CMOS image sensor according to a first embodiment of the present invention. It is sectional drawing in the CMOS image sensor by 1st Embodiment shown in FIG. FIG. 2 is a potential diagram in the CMOS image sensor according to the first embodiment shown in FIG. 1. FIG. 2 is a plan view showing pixels of the CMOS image sensor according to the first embodiment shown in FIG. 1. FIG. 2 is a circuit diagram showing a circuit configuration of the active CMOS image sensor according to the first embodiment shown in FIG. 1. It is a signal waveform diagram for demonstrating the transfer operation | movement of the electron in the CMOS image sensor by 1st Embodiment of this invention. FIG. 5 is a potential diagram for explaining an electron transfer operation of the CMOS image sensor according to the first embodiment of the present invention. It is a signal waveform diagram for demonstrating the electron multiplication operation | movement in the CMOS image sensor by 1st Embodiment of this invention. FIG. 6 is a potential diagram for explaining an electron multiplication operation in the CMOS image sensor according to the first embodiment of the present invention. It is a signal waveform diagram for demonstrating the transfer operation | movement of the electron in the CMOS image sensor by 2nd Embodiment of this invention. It is a potential diagram for demonstrating the transfer operation | movement of the electron of the CMOS image sensor by 2nd Embodiment of this invention. It is a signal waveform diagram for demonstrating the multiplication operation | movement of an electron in the CMOS image sensor by 2nd Embodiment of this invention. It is a potential diagram for demonstrating the electron multiplication operation | movement of the CMOS image sensor by 2nd Embodiment of this invention.

Explanation of symbols

3 Transfer channel (impurity region)
3a Electron multiplying part (charge increasing part)
3b Electron storage unit (charge storage unit)
5 Floating diffusion area (voltage converter)
8 Multiplication gate electrode (4th electrode)
9 Transfer gate electrode (second electrode)
10 Storage gate electrode (first electrode)
11 Read gate electrode (third electrode)

Claims (4)

A charge storage unit for storing and transferring signal charges; and
A first electrode for accumulating signal charges in the charge accumulator;
A second electrode for transferring a signal charge to the charge storage unit;
A voltage converter for converting the signal charge into a voltage;
A third electrode provided between the first electrode and the voltage conversion unit for transferring the signal charge stored in the charge storage unit to the voltage conversion unit;
An impurity region provided at least below the first electrode, the second electrode, and the third electrode for forming a path for transferring signal charges;
The imaging device, wherein an impurity concentration of a region corresponding to the lower portion of the impurity region below the first electrode is higher than at least an impurity concentration of a region corresponding to the lower portion of the second electrode and the third electrode. A first voltage at which the potential of the impurity region corresponding to the lower portion of the first electrode is lower than the potential of the impurity region corresponding to the lower portion of the third electrode. And is configured to apply a second voltage;
By applying the second voltage to the third electrode in a state where the first voltage is applied to the first electrode, the signal charge accumulated in the charge accumulating portion corresponds to the lower side of the third electrode. The imaging device according to claim 1, wherein the imaging device is configured to transfer to the voltage conversion unit via an impurity region to be processed. A charge increasing portion for increasing the signal charge accumulated in the accumulating portion by impact ionization; and
A fourth electrode for generating an electric field in the charge increasing portion for increasing the signal charge by impact ionization;
A first voltage at which the potential of the impurity region corresponding to the lower portion of the first electrode is lower than the potential of the impurity region corresponding to the lower portion of the second electrode. And is configured to apply a second voltage;
While the first voltage is applied to the first electrode, the second voltage is applied to the second electrode, and an electric field that increases signal charge due to the impact ionization is applied to the fourth electrode. By applying a third voltage to be generated in the part, the signal charge stored in the charge storage part is transferred to the charge increasing part via the impurity region corresponding to the lower part of the second electrode. The imaging device according to claim 1, wherein the imaging device is configured.   In the state where the first voltage is applied to the first electrode, the signal charge is increased by the transfer of the signal charge from the charge storage unit to the charge increase unit, and the charge increase unit to the charge storage unit The imaging apparatus according to claim 3, wherein the imaging apparatus is configured to alternately and repeatedly perform a signal charge transfer operation.

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