JP4006207B2 - Charge detection device, MOS solid-state imaging device including the same, and CCD solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a charge detection device, and more particularly to a charge detection device that receives a signal charge in a floating diffusion region formed on a semiconductor substrate and outputs an output signal corresponding to the potential of the floating diffusion region. The present invention also relates to a MOS solid-state imaging device and a CCD solid-state imaging device including such a charge detection device.
[0002]
[Prior art]
As a recent solid-state imaging device, as shown in FIG. 13, one photo is included in a plurality of pixel units 210 (only one is shown for simplicity) arranged on the surface of a semiconductor substrate (p-well) 20. A four-transistor CMOS image sensor including a diode 5 and four MOS transistors 1, 2, 3, and 4 is widely used. The photodiode (PD) 5 is formed by diffusing an n + layer 21 on the surface of the p-well 20. Note that a p ++ layer 25 is formed on the surface of the n ++ layer 21 to form a so-called buried structure. Reference numeral 6 denotes a cathode electrode connected to the n + layer 21 of the photodiode 5.
[0003]
In the pixel unit 210, the signal charge storage unit 7 having a floating diffusion region (FD) 22 formed at a predetermined distance from the photodiode 5, and further separated from the signal charge storage unit 7 by a predetermined distance. And the reset portion 19 formed of the n + layer 23 formed in the above manner. C _FD Indicates the junction capacitance between the floating diffusion region 22 and the p-well 20.
[0004]
In addition, between the photodiode 5 and the signal charge accumulating unit 7, there is SiO 2 ₂ A transfer transistor 1 having a gate electrode 32 formed through a film 31 is configured. Further, a reset transistor 2 having the same structure as that of the transfer transistor 1 is configured between the signal charge storage unit 7 and the reset unit 19. 3 is C _FD 4 is a driving transistor for amplifying the signal charge accumulated in the pixel unit 4, a readout transistor for selectively outputting the output voltage of the pixel unit 210 to the vertical signal line, and 8 for amplifying and outputting the signal charge of each pixel. The vertical signal lines 9 and 9 indicate load transistors that function as constant current sources. The drive transistor 3 and the load transistor 9 constitute a source follower circuit. The voltage VFD of the signal charge storage section 7 applied to the gate electrode of the drive transistor 3 is amplified by this source follower circuit and output to the vertical signal line 8. VRST is a reset voltage, and VDD is a power supply voltage.
[0005]
This CMOS image sensor is CMOS process compatible, that is, the MOS transistor in the pixel unit 210 is formed in the same process as the MOS transistor of the peripheral circuit. As a result, this CMOS image sensor is composed of one integrated circuit chip.
[0006]
This CMOS image sensor is driven as follows according to the operation timing shown in FIG. First, at time t0, the gate pulse ΦSEL of the read transistor 4 is turned on (a high level pulse is applied) to set the read state. Thereafter, the gate pulse ΦRST of the reset transistor 3 is turned on at time t1, and the potential VFD of the floating diffusion region 22 shown in FIG. 14 is set to the reset potential VRST (in other words, the signal charge in the signal charge storage unit 7 is changed). Empty). As a result, the image sensor outputs a dark voltage VRST2 shown in FIG. 3 as an output signal. During the accumulation period from the start of operation until ΦTG is turned on at time t2, when PD5 receives photons hν and generates carriers by photoelectric conversion, electrons (in the energy diagram) appear in n + layer 21 in PD5 shown in FIG. Are accumulated). However, an energy barrier is formed between the n + layer 21 of the PD 5 and the floating diffusion region 22 of the signal charge storage unit 7 due to the potential of the gate electrode 32 of the transfer transistor 1. Exists within. Next, at time t2 shown in FIG. 3, the gate pulse ΦTG of the transfer transistor 1 is turned on to remove the barrier immediately below the gate electrode 32, and the electrons in the PD5 are transferred to the floating diffusion region 22 all at once as shown in FIG. (In addition, since ΦTG is set so that the electrons in the PD 5 are completely transferred, no afterimage or noise is generated in the PD 5). When electrons are transferred to the floating diffusion region 22, the potential VFD of the floating diffusion region 22 changes according to the number of electrons (the voltage after the change is assumed to be Vsig). The voltage Vsig after the change is operated by the source follower circuit including the MOS transistor 3 and the constant current source 9 to the read transistor 4 which is turned on by the high level gate pulse ΦSEL via the source of the MOS transistor 3. Output. As a result, the bright-time signal voltage Vsig2 is output to the vertical signal line 8.
[0007]
An output circuit (not shown) connected to the vertical signal line 8 performs correlated double sampling (CDS), and performs amplification by taking the difference between the dark signal voltage VRST2 and the bright signal voltage Vsig2. Thereby, random kTC noise generated in the signal charge accumulating unit 7 by the above-described reset operation is removed. As a result, photoelectric conversion characteristics with good linearity can be obtained.
[0008]
[Problems to be solved by the invention]
By the way, with the development of semiconductor microfabrication technology, the power supply voltage of the MOS type solid-state imaging device tends to decrease in the future. Since the maximum signal voltage (the maximum signal that can be stored in the signal charge storage unit 7) decreases due to the decrease in the power supply voltage, the pixel unit 210 is equivalent to the dynamic range of the output signal (S / N ratio (signal-to-noise ratio)). There is a tendency that D cannot be secured.
[0009]
Here, measures such as providing a large number of booster circuits and power supplies can be considered. However, the provision of a booster circuit occupies the layout area and increases the chip cost. In addition, when a large number of power supplies are provided, a DC-DC converter or the like is required outside, which causes a problem that the power consumption and the number of parts of the entire camera increase.
[0010]
Therefore, an object of the present invention is a charge detection device that receives a signal charge in a floating diffusion region formed on a semiconductor substrate and outputs an output signal corresponding to the potential of the floating diffusion region. An object of the present invention is to provide a device capable of easily expanding the dynamic range of an output signal without incurring any of them.
[0011]
Another object of the present invention is to provide a MOS solid-state imaging device and a CCD solid-state imaging device including such a charge detection device.
[0012]
[Means for Solving the Problems]
In order to solve the above-described problems, a charge detection device according to the present invention includes a charge supply unit that supplies a signal charge formed on the surface of a semiconductor substrate,
A signal charge accumulating unit having a floating diffusion region formed on the surface of the substrate at a predetermined distance from the charge supply unit and capable of accumulating a signal charge by a junction capacitance between the floating diffusion region and the substrate; ,
A gate electrode provided on the substrate between the charge supply unit and the signal charge storage unit, and the signal charge from the charge supply unit according to a potential applied to the gate electrode; A transfer unit to transfer to,
Resetting means for resetting the signal charge stored in the signal charge storage unit,
In the charge detection device that outputs an output signal corresponding to the potential of the floating diffusion region of the signal charge storage unit,
The gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit are capacitively coupled so that the electrostatic potential of the floating diffusion region is deepened.
[0013]
In this specification, “supplying a signal charge” means generating a signal charge by itself such as a photoelectric conversion element and a signal charge received from another element such as a CCD (charge coupled device). Including the case of supplying
[0014]
Further, “capacitive coupling so that the electrostatic potential becomes deep” does not include coupling due to stray capacitance or the like that can substantially ignore the influence on the electrostatic potential (that is, potential). For example, when the dynamic range of the potential of the floating diffusion region is 1 volt (V), if the influence of capacitive coupling is 0.1 V or less, the capacitive coupling corresponds to “substantially negligible”. .
[0015]
In the charge detection device of the present invention, first, the potential of the floating diffusion region of the signal charge storage unit is set to the reset potential by the reset means. Next, for example, when the signal charge is an electron, a high level voltage is applied to the gate electrode of the transfer unit, and the signal charge from the charge supply unit is transferred to the signal charge storage unit. Then, an output signal corresponding to the potential of the floating diffusion region of the signal charge storage unit is output. At this time, since a high level voltage is applied to the gate electrode of the transfer unit, the static coupling of the floating diffusion region is caused by capacitive coupling between the gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit. Electric potential is deep. Therefore, the dynamic range of the output signal is expanded.
[0016]
This charge detection device has the same effect even when the signal charge is a hole. However, in order to transfer the signal charge from the charge supply unit to the signal charge storage unit, a low level voltage is applied to the gate electrode of the transfer unit.
[0017]
In one embodiment, the capacitive coupling between the gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit is formed by extending the gate electrode to the floating diffusion region. It is characterized by being.
[0018]
The charge detection device according to this embodiment is easily manufactured by changing the mask pattern of the gate electrode in a known manufacturing process.
[0019]
In the charge detection device of one embodiment, the capacitive coupling between the gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit includes a metal wiring electrically connected to the floating diffusion region. It is characterized by being formed to extend over the gate electrode made of a crystalline silicon layer.
[0020]
The charge detection device according to this embodiment is easily manufactured by changing the mask pattern of the metal wiring in a known manufacturing process.
[0021]
In one embodiment, the capacitive coupling between the gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit is floating on the gate electrode made of a first polycrystalline silicon layer. A second polycrystalline silicon layer electrically connected to the diffusion region is provided and formed.
[0022]
The charge detection device according to the embodiment is easily manufactured by changing the second polycrystalline silicon layer and the mask pattern of the metal wiring connected to the second polycrystalline silicon layer in a known manufacturing process. The
[0023]
The MOS type solid-state imaging device of the present invention is a MOS type solid-state imaging device having a plurality of unit cells arranged on a semiconductor substrate,
Each unit cell is
A photoelectric conversion section that is formed on the surface of the semiconductor substrate and generates a signal charge according to the amount of received light;
A signal charge accumulating portion having a floating diffusion region formed on the substrate surface by a predetermined distance from the above, and capable of accumulating signal charges by a junction capacitance between the floating diffusion region and the substrate;
A gate electrode provided on the substrate between the photoelectric conversion unit and the signal charge storage unit, and the signal charge from the photoelectric conversion unit is transferred to the signal charge storage unit according to a potential applied to the gate electrode; A transfer unit to transfer to,
Resetting means for resetting the signal charge stored in the signal charge storage unit;
Amplifying means for outputting an output signal corresponding to the potential of the floating diffusion region of the signal charge storage unit;
Reading means for reading out the output signal from the amplification means,
The gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit are capacitively coupled so that the electrostatic potential of the floating diffusion region is deepened.
[0024]
In the MOS type solid-state imaging device of the present invention, first, the potential of the floating diffusion region of the signal charge storage unit is set to the reset potential by the reset means. Next, for example, when the signal charge is an electron, a high level voltage is applied to the gate electrode of the transfer unit, and the signal charge from the photoelectric conversion unit is transferred to the signal charge storage unit. Then, an output signal corresponding to the potential of the floating diffusion region of the signal charge storage unit is output by the amplifying unit, and an output signal from the amplifying unit is read by the reading unit. At this time, since a high level voltage is applied to the gate electrode of the transfer unit, the static coupling of the floating diffusion region is caused by capacitive coupling between the gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit. Electric potential is deep. Therefore, the dynamic range of the output signal is expanded.
[0025]
The CCD solid-state imaging device of the present invention includes a plurality of photoelectric conversion elements arranged on the surface of a semiconductor substrate,
A CCD unit that sequentially transfers the charges generated by the photoelectric conversion elements along the substrate surface;
A signal charge storage that has a floating diffusion region formed on the substrate surface at a predetermined distance from the output stage of the CCD unit, and can store a signal charge by a junction capacitance between the floating diffusion region and the substrate. And
A gate electrode provided on the substrate between the output stage of the CCD unit and the signal charge storage unit, and the signal charge from the charge supply unit is converted into the signal charge according to the potential applied to the gate electrode; A transfer unit to transfer to the storage unit;
Resetting means for resetting the signal charge stored in the signal charge storage unit;
Amplifying means for outputting an output signal corresponding to the potential of the floating diffusion region of the signal charge storage unit;
Reading means for reading out the output signal from the amplification means,
The gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit are capacitively coupled so that the electrostatic potential of the floating diffusion region is deepened.
[0026]
In the CCD type solid-state imaging device of the present invention, first, the potential of the floating diffusion region of the signal charge storage unit is set to the reset potential by the reset means. Next, for example, when the signal charge is an electron, a high level voltage is applied to the gate electrode of the transfer unit, and the signal charge from the photoelectric conversion element via the CCD unit is transferred to the signal charge storage unit. Then, an output signal corresponding to the potential of the floating diffusion region of the signal charge storage unit is output by the amplifying unit, and an output signal from the amplifying unit is read by the reading unit. At this time, since a high level voltage is applied to the gate electrode of the transfer unit, the static coupling of the floating diffusion region is caused by capacitive coupling between the gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit. Electric potential is deep. Therefore, the dynamic range of the output signal is expanded.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
[0028]
(First embodiment)
FIG. 2 shows a schematic circuit configuration of a MOS type solid-state imaging device (CMOS image sensor) including a charge detection device according to an embodiment of the present invention. This CMOS image sensor includes a plurality of pixel units 10 arranged in a two-dimensional matrix on the surface of a semiconductor substrate (p-well 20 shown in FIG. 1), and a vertical shift register that selects a row direction based on a vertical clock. 13, a vertical signal line 16 connected to each pixel unit 10 arranged in the vertical direction, a vertical selection transistor 17 connected to the vertical signal line 16 for selecting the column direction, and the vertical selection transistor 17 on based on the horizontal clock. , A horizontal shift register 14 to be turned off, a horizontal signal line 18, and an output circuit 15. During one horizontal period determined by the horizontal clock, only the vertical selection transistors 17 of a certain column are turned on by the horizontal shift register 14 and the vertical selection transistors 17 of the remaining columns are turned off. That is, only the vertical signal line 16 in a certain column is conducted to the horizontal signal line 18 through the vertical selection transistor 17 in the on state, and the vertical signal lines 16 in the remaining columns are cut off from the horizontal signal line 18. During this one horizontal period, the output signals of the pixel units 10 in the rows sequentially selected by the vertical shift register 13 are read out to the output circuit 15 via the vertical signal line 16, the ON state vertical selection transistor 17, and the horizontal signal line 18. . When reading by voltage, CDS is performed by a correlated double sampling (CDS) circuit arranged for each column. When reading by current, CDS is performed by the output circuit 15 and output.
[0029]
FIG. 1 shows a circuit configuration in each pixel unit 10. For ease of understanding, the same elements as those in FIG. 13 are denoted by the same reference numerals. Similar to the pixel unit 210 shown in FIG. 13, the pixel unit 10 is of a four-transistor type including one photodiode 5 and four MOS transistors 1, 2, 3, and 4. A photodiode (PD) 5 as a charge supply unit or a photoelectric conversion unit is formed by diffusing an n + layer 21 on the surface of a p-well 20. Note that a p ++ layer 25 is formed on the surface of the n ++ layer 21 to form a so-called buried structure. Reference numeral 6 denotes a cathode electrode connected to the n + layer 21 of the photodiode 5.
[0030]
In the pixel unit 10, a signal charge storage unit 7 having a floating diffusion region (FD) 22 formed at a predetermined distance from the photodiode 5, and further spaced apart from the signal charge storage unit 7 by a predetermined distance. And the reset portion 19 formed of the n + layer 23 formed in the above manner. C _FD Indicates the junction capacitance between the floating diffusion region 22 and the p-well 20.
[0031]
In addition, between the photodiode 5 and the signal charge accumulating portion 7, there is ₂ A transfer transistor 1 is configured as a transfer section having a gate electrode 32 formed through a film 31. Further, a reset transistor 2 having the same structure as that of the transfer transistor 1 is configured between the signal charge storage unit 7 and the reset unit 19. A capacitor C is interposed between the gate electrode 32 of the transfer transistor 1 and the floating diffusion region 22 of the signal charge storage unit 7. _C Is added. It should be noted that the capacitor Cc is positively provided so that the electrostatic potential of the floating diffusion region 22 is deepened by the potential of the gate electrode 32, and is not simply a capacitive coupling due to the stray capacitance. .
[0032]
3 is C _FD 4 is a drive transistor for amplifying the signal charge accumulated in the pixel unit 4, a read transistor for selectively outputting the output voltage of the pixel unit 10 to the vertical signal line, and 8 for amplifying and outputting the signal charge of each pixel. Vertical signal lines (connected to the vertical signal line 16 in FIG. 1) and 9 indicate load transistors that function as constant current sources. The drive transistor 3 and the load transistor 9 constitute a source follower circuit. The voltage VFD of the signal charge storage section 7 applied to the gate electrode of the drive transistor 3 is amplified by this source follower circuit and output to the vertical signal line 8. VRST is a reset voltage, and VDD is a power supply voltage.
[0033]
The pixel unit 10 includes three horizontal drive pulses from the vertical shift register 13, that is, a pulse ΦTG for transferring signal charges accumulated in the photodiode 5 to the floating diffusion region 22, and C _FD Are input with a pulse ΦRST for initializing the signal charge accumulated in the signal, and a pulse ΦSEL for selectively outputting the output voltage of the pixel unit 10 to the vertical signal line 8.
[0034]
This CMOS image sensor is driven as follows according to the operation timing shown in FIG. 3 (that is, the same operation timing as in the conventional example). First, at time t0, the gate pulse ΦSEL of the read transistor 4 is turned on (high level is applied) to set the read state. Thereafter, the gate pulse ΦRST of the reset transistor 3 is turned on at time t1, and the potential VFD of the floating diffusion region 22 shown in FIG. 4 is set to the reset potential VRST (in other words, the signal charge in the signal charge storage unit 7 is changed). Empty). As a result, the image sensor outputs a dark voltage VRST2 shown in FIG. 3 as an output signal. During the accumulation period from the start of operation until ΦTG is turned on at time t2, when PD5 receives photons hν and generates carriers by photoelectric conversion, electrons (in the energy diagram) appear in n + layer 21 in PD5 shown in FIG. Are accumulated). However, an energy barrier is formed between the n + layer 21 of the PD 5 and the floating diffusion region 22 of the signal charge storage unit 7 due to the potential of the gate electrode 32 of the transfer transistor 1. Exists within. Next, at time t2 shown in FIG. 3, the gate pulse ΦTG of the transfer transistor 1 is turned on (high level VHi is applied) to remove the barrier immediately below the gate electrode 32, and as shown in FIG. Transfer to the floating diffusion region 22 at once (note that ΦTG is set so as to completely transfer the electrons in the PD 5, so no afterimage or noise occurs in the PD 5). When electrons are transferred to the floating diffusion region 22, the potential VFD of the floating diffusion region 22 changes according to the number of electrons (the voltage after the change is referred to as Vsig). The voltage Vsig after the change is operated by the source follower circuit including the MOS transistor 3 and the constant current source 9 to the read transistor 4 which is turned on by the high level gate pulse ΦSEL via the source of the MOS transistor 3. Output. As a result, the bright signal voltage Vsig2 is output to the vertical signal line 8.
[0035]
When reading by voltage, CDS is performed by a correlated double sampling (CDS) circuit arranged for each column. When reading by current, CDS is performed by the output circuit 15, and the dark signal voltage VRST2 and the light signal voltage Vsig2 are described above. The difference is taken and output. Thereby, random kTC noise generated in the signal charge accumulating unit 7 by the above-described reset operation and transfer operation is removed. As a result, photoelectric conversion characteristics with good linearity can be obtained.
[0036]
Here, in this CMOS image sensor, the capacitive coupling C between the gate electrode 32 and the floating diffusion region 22 when the gate pulse ΦTG of the transfer transistor 1 is turned on (high level VHi is applied). _C As a result, the electrostatic potential of the floating diffusion region 22 is deepened. Therefore, as indicated by D ′ in FIG. 5, the dynamic range of the output signal is expanded.
[0037]
For example, capacitive coupling C _C The potential difference ΔV is expressed by the following equation (1).
[0038]
ΔV = VHi × (C _C / (C _FD + C _C )) ... (1)
For example,
VHi = VDD = ΦRST = ΦTG = 3.3V
VRST = 2.3V
C _FD = 3fF
C _C = 3fF
Then,
ΔV = 1.65V
It becomes. That is, capacitive coupling C between the gate electrode 32 and the floating diffusion region 22 _C This increases the potential of the floating diffusion region 22 by 1.65V. And the dynamic range is expanded accordingly. In this example, considering the 3.3V drive, the dynamic range can be greatly expanded by 50%.
[0039]
In the prior art, from the viewpoint of not hindering amplification in the output circuit after reading, as can be seen from FIG. 13, the overlap between the gate electrode 32 and the floating diffusion region 22, 32 and the metal wiring 42 (connected to the floating diffusion region 22 via the contact 41) are eliminated as much as possible, and the accompanying capacitive coupling is eliminated. For this reason, the potential of the floating diffusion region 22 is not substantially affected, and the dynamic range D of the output signal is not expanded. However, if correlated double sampling (CDS) is performed, capacitive coupling C _C Since the influence of the potential shift due to is removed, capacitive coupling C _C The potential shift due to does not impair the linearity of the output signal. Focusing on this point has led to the creation of the present invention.
[0040]
Thus, according to this CMOS image sensor, the dynamic range of the output signal can be improved without increasing the drive voltage level. Conversely, if it is sufficient to ensure the same margin as in the conventional example, the drive voltage level can be lowered.
[0041]
6 to 10 show the capacitor C, respectively. _C The specific structure of is shown.
[0042]
In the example shown in FIG. 6, the capacitor C _C Is formed by extending the gate electrode 32 over the floating diffusion region 22. A gate insulating film 32 </ b> A exists between the gate electrode (indicated by reference numeral 32 </ b> A) extending over the floating diffusion region 22 and the floating diffusion region 22. Capacitor C _C Is constituted by a facing portion between the gate electrode 32 </ b> A and the floating diffusion region 22. In this case, the capacitor C _C Is easily manufactured by changing the mask pattern of the gate electrode in a known manufacturing process without increasing the area of the pixel unit.
[0043]
In the example shown in FIG. _C Is formed by extending a metal wiring 42 electrically connected to the floating diffusion region 22 via a contact 41 over the gate electrode 32 made of the first polycrystalline silicon layer. An interlayer insulating film (not shown) exists between the metal wiring (indicated by reference numeral 42A) extending to the gate electrode 32 and the gate electrode 32. Capacitor C _C Is constituted by a facing portion between the extended metal wiring 42 </ b> A and the gate electrode 32. In this case, the capacitor C _C Can be easily manufactured by changing the mask pattern of the metal wiring in a known manufacturing process without increasing the area of the pixel unit.
[0044]
In the example shown in FIG. _C Is electrically connected to the floating diffusion region 22 via the contact 41, the metal wiring 42A extending to the gate electrode 32, and the contact 41A on the gate electrode 32 made of the first polycrystalline silicon layer. A polycrystalline silicon layer 35 is provided. Interlayer insulating films (not shown) exist between the gate electrode 32 and the second polycrystalline silicon layer 35 and between the second polycrystalline silicon layer 35 and the metal wiring 42A, respectively. Capacitor C _C Is constituted by a facing portion between the second polycrystalline silicon layer 35 and the gate electrode 32. In this case, the capacitor C _C Is easily manufactured by changing the mask pattern of the second polycrystalline silicon layer, the contact, and the metal wiring in a known manufacturing process without increasing the area of the pixel unit.
[0045]
The example shown in FIG. 9 is a combination of the example of FIG. 6 and the example of FIG. Capacitor C _C Is a capacitance C formed by the opposing portion of the gate electrode 32A and the floating diffusion region 22. _C1 And a capacitor C formed by the opposing portion of the extended metal wiring 42A and the gate electrode 32A _C2 Are connected in parallel. In this case, the capacitor C _C Is easily manufactured by changing the mask pattern of the gate electrode and metal wiring in a known manufacturing process without increasing the area of the pixel unit.
[0046]
The example shown in FIG. 10 is a combination of the example of FIG. 6 and the example of FIG. Capacitor C _C Is a capacitance C formed by the opposing portion of the gate electrode 32A and the floating diffusion region 22. _C1 And a capacitor C formed by a facing portion between the second polycrystalline silicon layer 35 and the gate electrode 32A. _C3 Are connected in parallel. In this case, the capacitor C _C Can be easily manufactured by changing the mask pattern of the gate electrode, the second polycrystalline silicon layer, the contact, and the metal wiring in a known manufacturing process without increasing the area of the pixel unit.
[0047]
Thus, this CMOS image sensor is CMOS process compatible, that is, the MOS transistor in the pixel unit 10 is formed in the same process as the MOS transistor of the peripheral circuit. As a result, this CMOS image sensor is composed of one integrated circuit chip.
[0048]
(Second Embodiment)
FIG. 12 shows a schematic circuit configuration of a CCD solid-state imaging device (interline CCD image sensor) including a charge detection device according to an embodiment of the present invention. This CCD image sensor has a plurality of pixels 110 arranged in a two-dimensional matrix on the surface of a semiconductor substrate (p-well 120 shown in FIG. 11), and vertical transfer pulses ΦV1, ΦV2, and signal charges from the pixels 110. ..., a plurality of vertical CCDs 120 that are transferred to the vertical CCD based on ΦVm and sequentially transferred in the vertical direction, and signal charges from the vertical CCDs 120 are sequentially transferred in the horizontal direction based on the horizontal transfer pulses ΦH1, ΦH2,. A horizontal CCD 112 for transfer and an output circuit 115 for receiving and amplifying signal charges from the horizontal CCD 112 via a horizontal signal line 118 are provided. Each pixel 110 includes a photodiode as a photoelectric conversion element. The vertical CCD 120 and the horizontal CCD 112 constitute a transfer unit that transfers signal charges.
[0049]
As shown in FIG. 11, the output circuit 115 includes a signal charge storage unit 107 having a floating diffusion region (FD) 122 formed at a predetermined distance from the output stage (n-th stage) of the horizontal CCD 112, and A reset unit 119 composed of an n + layer 123 formed at a predetermined distance from the signal charge storage unit 107 is formed. C _FD Indicates the junction capacitance between the floating diffusion region 122 and the p-well 120.
[0050]
In addition, between the output stage (n-th stage) of the horizontal CCD 112 and the signal charge storage unit 107, SiO 2 ₂ A transfer transistor 101 is configured as a transfer unit having a gate electrode 132 formed through a film 131. Further, a reset transistor 102 having the same structure as that of the transfer transistor 1 is configured between the signal charge storage unit 107 and the reset unit 119. As in the first embodiment, a capacitor C is formed between the gate electrode 132 of the transfer transistor 101 and the floating diffusion region 122 of the signal charge storage unit 107. _C Is added. The capacitor Cc is positively provided so that the electrostatic potential of the floating diffusion region 122 is deepened by the potential of the gate electrode 132, and is not simply a capacitive coupling due to the stray capacitance.
[0051]
103 is C _FD A driving transistor for amplifying the signal charge accumulated in the pixel 104, a read transistor for selectively outputting the output voltage of the image sensor to the vertical signal line, and a signal 108 for amplifying and outputting the signal charge of each pixel An output signal line 109 indicates a load transistor that functions as a constant current source. The drive transistor 103 and the load transistor 109 constitute a source follower circuit. The voltage VFD of the signal charge storage unit 107 applied to the gate electrode of the driving transistor 103 is amplified by this source follower circuit and output to the output signal line 108. VRST is a reset voltage, and VDD is a power supply voltage.
[0052]
The output circuit 115 operates in the same manner as the pixel unit 110 in the first embodiment. First, the potential VFD of the floating diffusion region 122 of the signal charge storage unit 107 is set to the reset potential VRST by the reset pulse ΦRST. Next, a high level voltage ΦTG = VHi is applied to the gate electrode 132 of the transfer transistor 101, and the signal charge from the photodiode of the pixel 110 via the vertical CCD 120 and the horizontal CCD 112 is transferred to the signal charge storage unit 107. An output signal corresponding to the potential VFD of the floating diffusion region 122 of the signal charge storage unit 107 is output by the operation of the source follower circuit including the MOS transistor 103 and the constant current source 109, and the output signal is output by the read transistor 104. Is read out. The read signal is amplified by a circuit unit (not shown) by performing correlated double sampling (CDS).
[0053]
Here, in this CCD image sensor, the capacitive coupling C between the gate electrode 132 and the floating diffusion region 122 when the gate pulse ΦTG of the transfer transistor 101 is turned on (high level VHi is applied). _C As a result, the electrostatic potential of the floating diffusion region 122 is deepened. Therefore, the dynamic range of the output signal is expanded in the same manner as indicated by D ′ in FIG.
[0054]
Capacitor C _C The same structure as that shown in FIGS. 6 to 10 can be adopted. As a result, this CCD image sensor can be manufactured by a normal CCD process, and there is no need to change the process.
[0055]
【The invention's effect】
As is clear from the above, according to the charge detection device of the present invention, the dynamic range of the output signal can be easily expanded without causing a new problem.
[0056]
Further, according to the MOS type solid-state imaging device and the CCD type solid-state imaging device of the present invention, the dynamic range of the output signal can be easily expanded without causing a new problem.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a pixel unit included in a MOS type solid-state imaging device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a schematic circuit configuration when reading is performed with a voltage of the MOS type solid-state imaging device.
FIG. 3 is a diagram illustrating an operation timing of the MOS type solid-state imaging device.
FIG. 4 is a diagram showing a potential diagram at the time of resetting a diffusion region constituting the pixel unit.
FIG. 5 is a diagram showing a potential diagram at the time of transfer of diffusion regions constituting the pixel unit.
FIG. 6 is a diagram illustrating a structure example of a capacitor.
FIG. 7 is a diagram illustrating a structure example of a capacitor.
FIG. 8 is a diagram illustrating a structure example of a capacitor.
FIG. 9 is a diagram illustrating a structure example of a capacitor.
FIG. 10 is a diagram illustrating a structure example of a capacitor.
FIG. 11 is a diagram illustrating a configuration of an output circuit included in a CCD solid-state imaging device according to a second embodiment of the present invention.
FIG. 12 is a diagram showing a schematic circuit configuration of the CCD solid-state imaging device.
FIG.
FIG. 13 is a diagram illustrating a configuration of a pixel unit included in a conventional MOS solid-state imaging device.
FIG. 14 is a diagram showing a potential diagram at the time of transfer of a diffusion region constituting the pixel unit.
[Explanation of symbols]
1,101 Transfer transistor
3,103 Drive transistor
4,104 Read transistor
5 Photodiode
7,107 Signal charge storage unit
22,122 Floating diffusion region
32,132 Gate electrode
15,115 Output circuit

Claims (6)

A charge supply unit for supplying signal charges formed on the surface of the semiconductor substrate;
A signal charge accumulating unit having a floating diffusion region formed on the surface of the substrate at a predetermined distance from the charge supply unit and capable of accumulating a signal charge by a junction capacitance between the floating diffusion region and the substrate; ,
A gate electrode provided on the substrate between the charge supply unit and the signal charge storage unit, and the signal charge from the charge supply unit according to a potential applied to the gate electrode; A transfer unit to transfer to,
Resetting means for resetting the signal charge stored in the signal charge storage unit,
In the charge detection device that outputs an output signal corresponding to the potential of the floating diffusion region of the signal charge storage unit,
The charge detection device, wherein the gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit are capacitively coupled so that the electrostatic potential of the floating diffusion region is deepened. The charge detection device according to claim 1,
The capacitive coupling between the gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit is formed by extending the gate electrode to the floating diffusion region. . The charge detection device according to claim 1,
Capacitive coupling between the gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit is achieved by connecting a metal wiring electrically connected to the floating diffusion region on the gate electrode made of the first polycrystalline silicon layer. A charge detection device characterized in that the charge detection device is formed to extend up to. The charge detection device according to claim 1,
Capacitive coupling between the gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit is formed on the gate electrode made of the first polycrystalline silicon layer and electrically connected to the floating diffusion region. A charge detection device comprising two polycrystalline silicon layers. A MOS type solid-state imaging device having a plurality of unit cells arranged on a semiconductor substrate,
Each unit cell is
A photoelectric conversion section that is formed on the surface of the semiconductor substrate and generates a signal charge according to the amount of received light;
A signal charge accumulating portion having a floating diffusion region formed on the substrate surface by a predetermined distance from the above, and capable of accumulating signal charges by a junction capacitance between the floating diffusion region and the substrate;
A gate electrode provided on the substrate between the photoelectric conversion unit and the signal charge storage unit, and the signal charge from the photoelectric conversion unit is transferred to the signal charge storage unit according to a potential applied to the gate electrode; A transfer unit to transfer to,
Resetting means for resetting the signal charge stored in the signal charge storage unit;
Amplifying means for outputting an output signal corresponding to the potential of the floating diffusion region of the signal charge storage unit;
Reading means for reading out the output signal from the amplification means,
A MOS type solid-state imaging device, wherein the gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit are capacitively coupled so that the electrostatic potential of the floating diffusion region is deepened. A plurality of photoelectric conversion elements arranged on the surface of the semiconductor substrate;
A CCD unit that sequentially transfers the charges generated by the photoelectric conversion elements along the substrate surface;
A signal charge storage that has a floating diffusion region formed on the substrate surface at a predetermined distance from the output stage of the CCD unit, and can store a signal charge by a junction capacitance between the floating diffusion region and the substrate. And
A gate electrode provided on the substrate between the output stage of the CCD unit and the signal charge storage unit, and the signal charge from the charge supply unit is converted into the signal charge according to the potential applied to the gate electrode; A transfer unit to transfer to the storage unit;
Resetting means for resetting the signal charge stored in the signal charge storage unit;
Amplifying means for outputting an output signal corresponding to the potential of the floating diffusion region of the signal charge storage unit;
Reading means for reading out the output signal from the amplification means,
A CCD type solid-state imaging device, wherein the gate electrode of the transfer unit and the floating diffusion region of the signal charge storage unit are capacitively coupled so that the electrostatic potential of the floating diffusion region is deepened.

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