JP3354333B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a trench at an end of an isolation insulating film in contact with an impurity region.

[0002]

2. Description of the Related Art In recent years, demand for semiconductor storage devices has been rapidly expanding due to remarkable spread of information devices such as computers. Further, functionally, a memory having a large-scale storage capacity and capable of high-speed operation is required.
Along with this, technology development related to high integration and high-speed response or high reliability of semiconductor memory devices is being promoted.

[0003] Among semiconductor memory devices, there is a dynamic random access memory (DRAM) that can randomly input and output stored information. Generally, DRAM
Is composed of a memory cell array, which is a storage area for storing a large amount of storage information, and peripheral circuits necessary for input and output with the outside.

This memory cell array is formed by arranging a plurality of memory cells for storing unit storage information in a matrix. Also, the memory cell includes one MOS (Metal Oxide Semiconductor) transistor,
This shows a so-called one-transistor one-capacitor type memory cell composed of one capacitor connected to this. Since this type of memory cell has a simple structure, it is easy to improve the degree of integration of the memory cell array, and is widely used in large-capacity DRAMs. FIG.
Shows a sectional view of the memory cell, and FIG. 46 shows a plan view of the memory cell. It should be noted that the cross-sectional view of FIG. 45 shows a cross section taken along line XX in FIG. 46, and the plan view of FIG. 46 shows a plane taken along line YY of FIG.

The structure shown in FIGS. 45 and 46 is
1 shows a structure of a buried bit line stacked memory cell in which bit lines are buried.

The structure of the memory cell will be described with reference to FIGS. On the main surface of the p-type semiconductor substrate 1 made of silicon or the like, SiO _{2 is} used to define an active region.
An element isolation oxide film 2 is formed. In the active region defined by the isolation oxide film 2, one transfer gate transistor 100 and one stacked type capacitor 200 constitute a pair of memory cells.

[0007] Transfer gate transistor 100
Are first and second impurity regions 5, 6 forming source / drain regions formed on the main surface of semiconductor substrate 1.
And a gate electrode (word line) 4 made of polysilicon or the like with a gate oxide film 3 made of SiO ₂ or the like interposed on the main surface of the semiconductor substrate 1. The first impurity region 5 has a two-layer structure of a high-concentration impurity region 5a and a low-concentration impurity region 5b, and the second impurity region 6 is composed of a high-concentration impurity region. In addition, the gate electrode 4
Are covered with a sidewall insulating film 8 made of SiO ₂ or the like.

On semiconductor substrate 1, storage node contact hole 10 exposing second impurity region 6 and bit line contact hole 1 exposing first impurity region 5 are formed.
1 and a film thickness of about 8000Å made of SiO ₂ or the like.
About the first interlayer oxide film 9. The bit line 7 connected to the first impurity region 5 is formed in the bit line contact hole 11. This bit line 7
Is a doped polysilicon film 7 having a thickness of about 1000 °
a and a tungsten silicide film 7b having a thickness of about 1000 °.

On the first interlayer oxide film 9, a second interlayer oxide film 13 having a storage node contact hole 10 and made of SiO ₂ or the like and having a thickness of about 10,000 ° is formed. Storage node contact hole 10
Inside, a storage node (lower electrode) 12 made of polysilicon or the like having a thickness of about 6000 ° is formed on a second interlayer oxide film 13. Further, a dielectric film 14 is formed on the surface of the storage node 12, and a cell plate (upper electrode) 15 is formed on the dielectric film 14. This storage node 12 and dielectric film 14
And the cell plate 15 constitute the stacked type capacitor 200. A wiring layer 17 is formed above the cell plate 15 with a third interlayer oxide film 16 interposed.

Next, a method of manufacturing a memory cell having the above structure will be described with reference to FIGS.

First, referring to FIG. 47, isolation oxide film 2 is formed in a predetermined region on the main surface of semiconductor substrate 1 by using the LOCOS method. Thereafter, referring to FIG. 48, a gate electrode 4 having a predetermined shape made of polysilicon or the like is formed in a predetermined region on semiconductor substrate 1 with a gate oxide film 3 made of SiO ₂ or the like interposed therebetween.

Referring to FIG. 49, a resist film 20 is formed on semiconductor substrate 1 so that a predetermined region between gate electrodes 4 arranged in parallel is exposed. Then, using this resist film 20 as a mask, n
A type impurity is implanted under the conditions of an implantation amount of about 2.3 × 10 ¹³ cm ² and an implantation energy of about 35 keV to form a low concentration impurity region 5b.

Referring to FIG. 50, a sidewall 8 is formed on gate electrode 4 by depositing SiO ₂ on semiconductor substrate 1 and performing anisotropic etching. Thereafter, referring to FIG. 51, using sidewall 8 as a mask, an n-type impurity such as phosphorus is implanted into the main surface of semiconductor substrate 1 at an implantation amount of 4.0 × 10 ¹³ cm ² and an implantation energy of about 40 keV. Implanted under the conditions, and the high concentration impurity region 5
a and the high concentration impurity region 6 are formed. This allows
A first impurity region 5 including a high-concentration impurity region 5a and a low-concentration impurity region 5b;
Impurity region 6 is completed.

Referring to FIG. 52, a first interlayer oxide film 9 made of SiO ₂ or the like having a thickness of about 8000 ° is deposited by a CVD method so as to cover semiconductor substrate 1.

Referring to FIG. 53, a resist film 22 having an opening above the first impurity region 5 is formed on the first interlayer oxide film 9. Then, the resist film 22
Is used as a mask to open a bit line contact hole 11 by a self-aligned contact method.

Next, referring to FIG.
Is removed, a doped polysilicon film 7a having a thickness of about 1000.degree. And a tungsten silicide film 7 having a thickness of about 1000.degree.
The bit line 7 is formed by depositing b and patterning it into a predetermined shape.

Referring to FIG. 55, a second interlayer oxide film 13 made of SiO ₂ or the like and having a thickness of about 10,000 ° is formed on first interlayer oxide film 9. Then, this second
On the interlayer oxide film 13, a resist film 23 having an opening above the second impurity region 6 is formed.
Using storage mask 3 as a mask, a storage node contact hole 10 is opened in first interlayer oxide film 9 and second interlayer oxide film 13 by a self-aligned contact method.

Referring to FIG. 56, polysilicon or the like is deposited in storage node contact hole 10 to form storage node 12 having a thickness of about 6000 ° on second interlayer oxide film 13. .

Next, referring to FIG. 57, a dielectric film 14 and a cell plate 15 are deposited on storage node 12. Thus, a stacked type capacitor 200 including the storage node 12, the dielectric film 14, and the cell plate 15 is completed. Thereafter, referring to FIG. 58, a third layer made of SiO ₂ or the like
An interlayer oxide film 16 is formed, and a wiring layer 17 having a predetermined shape is formed on the third interlayer oxide film 16 to complete the memory cell shown in FIG.

[0020]

Here, the above-mentioned DR
AM stores data by storing charge in a capacitor. For example, when "H" data is stored, a current leak from the storage node becomes a problem, so that the DRAM needs to be refreshed periodically. This DR
The period of the refresh operation of the AM is preferably long. However, as the integration degree of the DRAM increases, the capacity of the capacitor of the memory cell decreases, so that the period tends to become shorter. Therefore, even if the degree of integration of the DRAM increases, it is necessary to prevent the leakage of the current from the storage node in order to maintain the refresh operation cycle longer.

Referring now to FIG. 59, a description will be given of a current leak path from a storage node in the above-described memory cell structure.

The leakage path of current from storage node 12 is as follows: (i) leakage from second impurity region 6 to semiconductor substrate 1 (ii) leakage from second impurity region 6 under gate electrode 4 to first impurity region 5 Leak (iii) There are three leaks to the cell plate 15.

The most dominant of the leak paths is considered to be (i) leak from the second impurity region 6 to the semiconductor substrate 1. Leakage into the semiconductor substrate 1 is the same as leakage when a reverse bias potential is applied to the pn junction, but when the isolation oxide film 2 is formed on the semiconductor substrate 1 or when the first and second impurity regions 5 are formed. , 6 during the step of implanting impurities into the semiconductor substrate 1, so-called crystal defects are introduced.
If this crystal defect is formed just at the pn junction, a new leak path will be formed in this region. As a result, the charge stored in the capacitor is discharged through this leak path, and the data retention of the DRAM becomes defective.

In particular, many crystal defects 2b are generated in the edge portion of the isolation oxide film 2, that is, in a region of a bird's beak 2a. As a method for removing the crystal defects 2b, it is possible to remove them by performing a heat treatment for removing the crystal defects after the impurity implantation step. However, as the degree of integration of the DRAM increases, a low-temperature process is required, and it has become difficult to completely remove the crystal defects.

The present invention has been made to solve such a problem. By providing a groove at an edge portion of an isolation oxide film in contact with a drain region, crystal defects in this region are removed, and current is reduced. An object of the present invention is to provide a semiconductor memory device capable of preventing a leak beforehand and a method of manufacturing the same.

[0026]

A semiconductor memory device according to the present invention has a semiconductor substrate having a main surface, an isolation insulating film for defining an active region on the main surface of the semiconductor substrate, and a semiconductor substrate formed on the main surface. A first conductive layer, and an impurity region formed to a predetermined depth in the active region on the main surface;
An insulating layer covering the semiconductor substrate and having an opening exposing the impurity region; a second conductive layer connected to the impurity region in the opening; and an isolation layer on the impurity region side. A groove provided at an end and communicating with the semiconductor substrate. Further, the insulating layer is embedded in the groove.

[0027]

According to the semiconductor memory device of the present invention, a groove communicating with the semiconductor substrate is provided at the end of the isolation insulating film in contact with the impurity region, and the insulating layer is embedded in the groove. . By providing the groove in this manner, crystal defects at the end of the isolation insulating film are eliminated, and leakage of current from the impurity region to the semiconductor substrate due to the crystal defects can be prevented.

[0028]

Embodiment (Embodiment 1) Hereinafter, a first embodiment based on the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 1 is a sectional view of a memory cell in this embodiment, and FIG. 2 is a plan view of this embodiment. In addition, FIG.
1 corresponds to a cross section taken along the line X-Y, and FIG. 2 corresponds to a plane viewed along the line Y-Y in FIG.

Here, the cross-sectional structure of the memory cell shown in FIG. 1 has substantially the same structure as the cross-sectional structure of the memory cell shown in FIG. 45 of the prior art, and therefore detailed description is omitted. Only the features of this embodiment will be mentioned.

In the memory cell of this embodiment, a groove 18 communicating with the semiconductor substrate 1 is formed at the end of the isolation oxide film 2 on the side of the second impurity region 6 of the transfer gate transistor 100. A first interlayer oxide film 9 is buried inside.

Thus, by providing groove 18 at a predetermined position at the end of isolation oxide film 2, p-type semiconductor substrate 1 and second impurity region 6 formed of n + impurity region are formed. -N junction is isolated oxide film 2 as in the prior art.
The edge portion having many crystal defects does not touch. Therefore, it is possible to prevent a current from leaking from the storage node 12 to the semiconductor substrate 1 via the second impurity region 6 beforehand.

As a result, the period of the refresh operation of the memory cell can be lengthened, and a high-performance and highly reliable memory cell can be realized.

Next, a method of manufacturing the memory cell will be described with reference to FIGS.

First, referring to FIG. 3, isolation oxide film 2 is formed in a predetermined region on the main surface of p-type semiconductor substrate 1 by using the LOCOS method. Thereafter, referring to FIG. 4, a gate electrode 4 having a predetermined shape made of polysilicon or the like is formed in a predetermined region on semiconductor substrate 1 with a gate oxide film 3 made of SiO ₂ or the like interposed therebetween.

Next, referring to FIG. 5, a resist film 20 exposing a predetermined region between a plurality of gate electrodes 4 arranged in parallel on semiconductor substrate 1 is formed. Then, using this resist film 20 as a mask, n
A type impurity is implanted under the conditions of an implantation amount of about 2.3 × 10 ¹³ cm ² and an implantation energy of about 35 keV to form a low concentration impurity region 5b.

Next, referring to FIG. 6, SiO ₂ is deposited on semiconductor substrate 1 and anisotropic etching is performed to form sidewalls 8 on gate electrode 4. Thereafter, referring to FIG. 7, impurities such as phosphorus are implanted into the main surface of semiconductor substrate 1 under the conditions of implantation energy of 40 keV and implantation amount of 4.0 × 10 ¹³ cm ^{2 using} sidewall 8 as a mask. A high concentration impurity region 5a and a high concentration impurity region 6 are formed. Thereby, the high concentration impurity region 5
a and first impurity region 5 comprising low-concentration impurity region 5b
Then, the second impurity region 6 composed of the high concentration impurity region is completed. Through the above steps, the transfer gate transistor 100 is completed on the semiconductor substrate 1.

Next, referring to FIG. 8, a resist film 21 having an opening exposing an end of isolation oxide film 2 on second impurity region 6 side is formed on semiconductor substrate 1. afterwards,
Using this resist film as a mask, an end of the isolation oxide film is removed by anisotropic etching in a C ₄ F ₈ gas atmosphere to form a groove 18. At this time, a crystal defect generated at the end of the isolation oxide film 2 during the formation of the isolation oxide film 2 is also removed.

Next, referring to FIG. 9, a first interlayer oxide film 9 made of SiO ₂ or the like having a thickness of about 8000 ° is deposited by a CVD method so as to cover semiconductor substrate 1.

Next, referring to FIG. 10, a resist film 22 having an opening above first impurity region 5 is formed on first interlayer oxide film 9. Then, the resist film 22
Is used as a mask to open bit line contact hole 11 by a self-aligned contact method.

Next, referring to FIG.
Is removed, a doped polysilicon film 7a having a thickness of about 1000.degree. And a tungsten silicide film 7 having a thickness of about 1000.degree.
The bit line 7 is formed by depositing b and patterning it into a predetermined shape.

Next, referring to FIG. 12, a second interlayer oxide film 13 made of SiO ₂ or the like and having a thickness of about 10,000 ° is formed on first interlayer oxide film 9. Then, this second
On the interlayer oxide film 13, a resist film 23 having an opening above the second impurity region 6 is formed.
Using storage mask 3 as a mask, a storage node contact hole 10 is opened in first interlayer oxide film 9 and second interlayer oxide film 13 by a self-aligned contact method.

Next, referring to FIG.
Then, polysilicon or the like is deposited in the storage node contact hole to form a storage node 12 having a thickness of about 6000 ° on the second interlayer oxide film 13.

Next, referring to FIG. 14, a dielectric film 14 and a cell plate 15 are deposited on storage node 12. Thus, a stacked type capacitor 200 including the storage node 12, the dielectric film 14, and the cell plate 15 is completed.

Next, referring to FIG.
By depositing a third interlayer oxide film 16 made of SiO ₂ or the like on the substrate 5 and further forming a wiring layer 17 having a predetermined shape on the third interlayer oxide film 16, the third embodiment shown in FIG. The memory cell is completed.

As described above, by using the manufacturing method of the memory cell in this embodiment, the end of the isolation oxide film 2 on the side of the second impurity region 6 is removed, and the crystal defect is removed at the same time when the trench 18 is formed. As a result, the p-type semiconductor substrate 1
And a second impurity region 6 composed of an n.sup. ⁺ Impurity region, a memory cell structure in which crystal defects, which often occur at the end of the isolation oxide film 2, are reduced in a pn junction formed as in the prior art. It can be realized.

(First Embodiment) Next, a first embodiment related to the present invention will be described with reference to FIGS. 16 and 17. FIG. FIG. 16 is a cross-sectional view of a memory cell according to the first embodiment, and FIG. 17 is a plan view of the memory cell according to the first embodiment. In addition, FIG.
17 shows a cross section taken along line XX in FIG. 17, and FIG. 17 shows a plane taken along line YY in FIG.

Here, the cross-sectional structure of the memory cell shown in FIG. 16 has almost the same structure as the cross-sectional structure of the memory cell shown in the first embodiment of FIG. 1, and therefore detailed description is omitted. Only the features of Example 1 will be mentioned.

In the memory cell of the first embodiment, when compared with the structure of the memory cell shown in the first embodiment,
The storage node contact hole 10 in which the storage node 12 is formed is formed so as to include the groove 18. By using this structure, similarly to the first embodiment, the second semiconductor substrate 1 including the p-type semiconductor substrate 1 and the n + impurity region is formed.
The pn junction formed from the impurity region 6 does not cover the edge of the isolation oxide film 2 where there are many crystal defects as in the related art. Therefore, the storage node 12
Leakage of current into the semiconductor substrate 1 via the impurity region 6 can be prevented beforehand.

Therefore, the cycle of the refresh operation of the memory cell can be lengthened, and a high-performance and highly reliable memory cell can be realized. Further, the unit resistance value of the storage node 12 can be reduced.

Next, a method of manufacturing a memory cell according to the first embodiment will be described with reference to FIGS. The steps up to the formation of the high-concentration impurity regions 5a and 6 are the same as the steps shown in FIGS. 3 to 7 described in the first embodiment, and a description thereof will be omitted.

First, referring to FIG. 18, a first interlayer oxide film 9 made of SiO ₂ or the like having a thickness of about 8000 ° is deposited by a CVD method so as to cover semiconductor substrate 1.

Next, referring to FIG. 19, a resist film 22 having an opening above first impurity region 5 is formed on first interlayer oxide film 9. Then, the resist film 22
Is used as a mask to open bit line contact hole 11 by a self-aligned contact method.

Next, referring to FIG.
Is removed, a doped polysilicon film 7a having a thickness of about 1000.degree. And a tungsten silicide film 7 having a thickness of about 1000.degree.
The bit line 7 is formed by depositing b and patterning it into a predetermined shape.

Next, referring to FIG. 21, a second interlayer oxide film 13 made of SiO ₂ or the like and having a thickness of about 10,000 ° is formed on first interlayer oxide film 9. Then, this second
On the interlayer oxide film 13, a resist film 23 having an opening above the second impurity region 6 and above the end of the isolation oxide film 2 is formed, and the resist film 23 is used as a mask to form a self-align contact method. Performs anisotropic etching in a C ₄ F ₈ gas atmosphere to open a storage node contact hole 10 in the first interlayer oxide film 9 and the second interlayer oxide film 13. Is removed to form a groove 18.

Next, referring to FIG.
Is removed, the storage node contact hole 10 is removed.
Polysilicon or the like is deposited inside the second interlayer oxide film 13.
Storage node 12 having a thickness of about 6000 mm on top
To form At this time, a part of the storage node 12 is also formed in the groove 18.

Next, referring to FIG. 23, a dielectric film 14 and a cell plate 15 are deposited on storage node 12. Thus, a stacked type capacitor 200 including the storage node 12, the dielectric film 14, and the cell plate 15 is completed.

Next, referring to FIG.
By forming a third interlayer oxide film 16 made of SiO ₂ or the like on the substrate 5 and further forming a wiring layer 17 having a predetermined shape on the third interlayer oxide film 16, the memory cell shown in FIG. Complete.

As described above, according to the memory cell manufacturing method of the first embodiment, the opening of the storage node contact hole 10 and the formation of the groove 18 are performed in the same step. Thus, the number of manufacturing steps can be reduced as compared with the manufacturing method of the first embodiment, and the cost for the manufacturing steps can be reduced.

Embodiment 2 Hereinafter, a second embodiment according to the present invention will be described with reference to FIG.
5 and FIG. 26 will be described. The memory cell in the first embodiment described above is a case of a buried bit line stack type memory cell, but in the second embodiment, a case of a stack type memory cell will be described. FIG. 25 is a sectional view of a memory cell according to the second embodiment, and FIG. 26 is a plan view of the memory cell according to the second embodiment. Note that FIG. 25 corresponds to a cross section taken along line XX in FIG. 26, and FIG. 26 corresponds to a plane viewed along line YY in FIG.

Referring to both figures, the structure of the memory cell in the second embodiment is different from that of the first embodiment in that:
Except that the bit line 7 is formed above the stacked type capacitor 200, it has the same structure, and the end of the isolation oxide film 2 in contact with the second impurity region 6 is provided in the same manner as in the first embodiment. A groove 18 is formed. The bit line 7 includes a poly pad 7c made of polysilicon or the like, a barrier metal layer 7d made of tungsten or the like, and a metal layer 7e made of aluminum or the like.

As described above, also in the structure of the memory cell in the second embodiment, the groove 18 is provided at the end of the isolation oxide film 2 as in the first embodiment, so that the p-type semiconductor substrate 1 is formed. The pn junction formed by the first impurity region and the second impurity region 6 made of the n @ + impurity region is not applied to the end portion of the isolation oxide film 2 where there are many crystal defects as in the related art.
Therefore, the storage node 12 to the second impurity region 6
Current can be prevented from leaking to the semiconductor substrate 1 through the semiconductor device.

As a result, the period of the refresh operation of the memory cell can be lengthened, and a high-performance and highly reliable memory cell can be realized.

Next, a method of manufacturing the memory cell will be described with reference to FIGS.

The steps up to the formation of the groove 18 are as follows:
Since the process is the same as the process of FIGS. 3 to 8 described in the first embodiment, the description is omitted here.

First, referring to FIG. 27, poly pad 7c made of polysilicon or the like connected to first impurity region 5 is formed on semiconductor substrate 1. Thereafter, referring to FIG. 28, a thickness of about 8000
The first interlayer oxide film 9 made of SiO ₂ or the like
It is deposited by the D method.

Referring to FIG. 29, a resist film 24 having an opening above the second impurity region 6 is formed on the first interlayer oxide film 9, and the resist film 24 is used as a mask. Then, a storage node contact hole 10 is opened in the first interlayer oxide film 9 by a self-aligned contact method.

Next, referring to FIG.
Is removed, the storage node contact hole 10 is removed.
A storage node 12 having a thickness of about 6000 ° on first interlayer oxide film 9.
To form

Next, referring to FIG. 31, a dielectric film 14 and a cell plate 15 are deposited on storage node 12. Thus, a stacked type capacitor 200 including the storage node 12, the dielectric film 14, and the cell plate 15 is completed.

Next, referring to FIG.
5, a second interlayer oxide film 13 made of SiO ₂ or the like and having a thickness of about 10,000 ° is formed. Then, this second
On the interlayer oxide film 13, a resist film 25 having an opening above the first impurity region 5 is formed.
Using bit line 5 as a mask, a bit line contact hole 11 leading to poly pad 7c is opened in first interlayer oxide film 9 and second interlayer oxide film 13 by a self-aligned contact method.

Next, referring to FIG.
Is removed, the storage node contact hole 11 is removed.
A barrier metal layer 7d of tungsten or the like is deposited therein, and a metal layer 7e made of aluminum or the like is further deposited on the barrier metal layer 7d. Thus, the bit line 7 including the poly pad 7c, the barrier metal layer 7d, and the metal layer 7e is completed.

Referring to FIG. 34, a third interlayer oxide film 16 made of SiO ₂ or the like is formed on metal layer 7c. By forming the wiring layer 17, the memory cell shown in FIG. 25 is completed.

As described above, in the method of manufacturing the memory cell according to the second embodiment, similarly to the manufacturing method according to the first embodiment, the end of the isolation oxide film 2 on the second impurity region 6 side is removed. Crystal defects are removed at the same time that the groove portions 18 are formed. As a result, the pn junction formed by the p-type semiconductor substrate 1 and the second impurity region 6 composed of the n ⁺ impurity region is often generated at the end of the isolation oxide film 2 as in the prior art. A memory cell structure with reduced crystal defects can be realized.

(Embodiment 2) Next, Embodiment 2 related to the present invention will be described with reference to FIGS. 35 and 36. FIG. Also in the reference example 2, a case of a stack type memory cell will be described as in the third embodiment. FIG. 35 is a sectional view of a memory cell according to the second embodiment, and FIG. 36 is a plan view of the memory cell according to the second embodiment. Note that FIG.
Shows a cross section taken along line XX in FIG. 36, and FIG.
5 shows a plane viewed from the line YY in FIG. Referring to both figures,
The structure of the memory cell in the reference example 2 is different from that of the third embodiment in that the storage node contact hole 10 in which the storage node 12 is formed includes the groove 18. By using this structure, it is formed from Example 2 Similarly, p-type semiconductor substrate 1 and the n ⁺ second impurity regions 6 that comprise impurity regions p-
The n-junction is no longer applied to the end portion of the isolation oxide film 2 where there are many crystal defects as in the prior art, so that the current is prevented from leaking from the storage node 12 to the semiconductor substrate 1 via the second impurity region 6. It becomes possible. As a result, the period of the refresh operation of the memory cell can be lengthened, and a high-performance and highly reliable memory cell can be realized. Further, the unit resistance value of the storage node 12 can be reduced.

Next, a method of manufacturing the memory cell will be described with reference to FIGS. The steps up to the formation of the high-concentration impurity regions 5a and 6 are the first steps.
3 to 7 described in the first embodiment, the description is omitted here.

First, referring to FIG. 37, poly pad 7c made of polysilicon or the like connected to first impurity region 5 is formed on semiconductor substrate 1. Thereafter, referring to FIG. 38, a thickness of about 8000
The first interlayer oxide film 9 made of SiO ₂ or the like
It is deposited by the D method.

Next, referring to FIG. 39, a resist film 24 having an opening above the second impurity region 6 and the end of isolation oxide film 2 is formed on first interlayer oxide film 9. Thereafter, using the resist film 24 as a mask, the storage node contact hole 10 and the groove 18 are simultaneously formed by performing anisotropic etching in a C4 F8 gas atmosphere by a self-aligned contact method.

Next, referring to FIG. 40, polysilicon or the like is deposited in storage node contact hole 10 to form storage node 12 having a thickness of about 6000 ° on first interlayer oxide film 9. At this time, the trench 18 is also filled with polysilicon.

Next, referring to FIG. 41, a dielectric film 14 and a cell plate 15 are deposited on storage node 12. Thus, a stacked type capacitor 200 including the storage node 12, the dielectric film 14, and the cell plate 15 is completed.

Next, referring to FIG. 42, cell plate 1
A second interlayer oxide film 13 made of SiO ₂ or the like and having a thickness of about 10000 ° is formed on 5. After that, a resist film 25 having an opening above the first impurity region 5 is formed on the second interlayer oxide film 13.
Line contact hole 11 is formed in first interlayer oxide film 9 by a self-aligned contact method using
And an opening in the second interlayer oxide film 13.

Next, referring to FIG.
Is removed, a barrier metal layer 7d made of tungsten or the like is deposited in the bit line contact hole 11, and a wiring layer 7e made of aluminum or the like is formed on the barrier metal layer 7d. Thereby, the poly pad 7c,
The bit line 7 including the barrier metal layer 7d and the metal layer 7e is completed.

Next, referring to FIG. 44, a third interlayer oxide film 16 made of SiO ₂ or the like is formed on metal layer 7e.
Further, by forming a wiring layer 17 having a predetermined shape on third interlayer oxide film 16, the memory cell shown in FIG. 35 is completed.

As described above, in Reference Example 2, Reference Example 1
Similarly to the above, the opening of the storage node contact hole 10 and the formation of the groove 18 are performed in the same step. Thus, the number of manufacturing steps can be reduced as compared with the manufacturing method of the first embodiment, and the cost for the manufacturing steps can be reduced.

In each embodiment and each reference example, the same reference numerals indicate the same or corresponding parts.

[0084]

According to the semiconductor memory device of the present invention, a groove is provided at the end of the isolation insulating film on the side in contact with the impurity region, and the insulating layer is buried in the groove, whereby the isolation insulating film is formed. There is no crystal defect at the end, and leakage of current from the impurity region to the semiconductor substrate due to the crystal defect can be prevented.

As a result, in the semiconductor memory device using this structure, the leak current is reduced, and the operation reliability of the semiconductor memory device can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor memory device according to the first embodiment based on the present invention.

FIG. 3 is a first process chart of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 4 is a second process chart of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 5 is a third process chart of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 6 is a fourth process chart of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 7 is a fifth process chart of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 8 is a sixth process chart of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 9 is a seventh process chart of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 10 is an eighth step diagram of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 11 is a ninth step diagram of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 12 is a tenth process chart of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 13 is an 11th step diagram of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 14 is a twelfth step diagram of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 15 is a thirteenth process chart of the method for manufacturing the semiconductor memory device in the first embodiment based on the present invention;

FIG. 16 is a sectional view of a semiconductor memory device according to a reference example 1 relating to the present invention;

FIG. 17 is a plan view of a semiconductor memory device according to a first embodiment related to the present invention;

FIG. 18 is a sixth process chart of the method for manufacturing the semiconductor memory device in the first embodiment related to the present invention;

FIG. 19 is a seventh process chart of the method for manufacturing the semiconductor memory device in the first embodiment related to the present invention;

FIG. 20 is an eighth step diagram of the method for manufacturing the semiconductor storage device in the first embodiment related to the present invention;

FIG. 21 is a ninth step diagram of the method for manufacturing the semiconductor storage device in the first embodiment related to the present invention;

FIG. 22 is a tenth process chart of the method for manufacturing the semiconductor memory device in the first embodiment related to the present invention;

FIG. 23 is an 11th step diagram of the method for manufacturing the semiconductor memory device in the reference example 1 related to the present invention;

FIG. 24 is a twelfth step diagram of the method for manufacturing the semiconductor memory device in the first embodiment related to the present invention;

FIG. 25 is a sectional view of a semiconductor memory device in a second embodiment based on the present invention.

FIG. 26 is a plan view of a semiconductor memory device in a second embodiment based on the present invention.

FIG. 27 is a seventh process chart of the method for manufacturing the semiconductor memory device in the second embodiment based on the present invention.

FIG. 28 is an eighth step diagram of the method for manufacturing the semiconductor memory device in the second embodiment based on the present invention;

FIG. 29 is a ninth step diagram of the method for manufacturing the semiconductor memory device in the second embodiment based on the present invention.

FIG. 30 is a tenth process chart of the method for manufacturing the semiconductor memory device in the second embodiment based on the present invention;

FIG. 31 is an 11th step diagram of the method for manufacturing the semiconductor memory device in the second embodiment based on the present invention;

FIG. 32 is a diagram showing a twelfth step of the method for manufacturing the semiconductor memory device in the second embodiment based on the present invention;

FIG. 33 is a thirteenth process diagram of the method for manufacturing the semiconductor memory device in the second embodiment based on the present invention.

FIG. 34 is a fourteenth process chart of the method for manufacturing the semiconductor memory device in the second embodiment based on the present invention;

FIG. 35 is a sectional view of a semiconductor memory device according to a reference example 2 relating to the present invention;

FIG. 36 is a plan view of a semiconductor memory device according to a reference example 2 relating to the present invention;

FIG. 37 is a sixth process chart of the method for manufacturing the semiconductor memory device in the reference example 2 related to the present invention;

FIG. 38 is a seventh process chart of the method for manufacturing the semiconductor storage device in the reference example 2 related to the present invention;

FIG. 39 is an eighth step diagram of the method for manufacturing the semiconductor memory device in the reference example 2 related to the present invention;

FIG. 40 is a ninth step diagram of the method for manufacturing the semiconductor storage device in the reference example 2 related to the present invention;

FIG. 41 is a tenth process chart of the method for manufacturing the semiconductor memory device in the reference example 2 related to the present invention;

FIG. 42 is an 11th step diagram of the method for manufacturing the semiconductor memory device in the reference example 2 related to the present invention;

FIG. 43 is a twelfth step diagram of the method for manufacturing the semiconductor storage device in the reference example 2 related to the present invention;

FIG. 44 is a thirteenth process chart of the method for manufacturing the semiconductor memory device in the reference example 2 related to the present invention;

FIG. 45 is a cross-sectional view of a conventional semiconductor memory device.

FIG. 46 is a plan view of a conventional semiconductor memory device.

FIG. 47 is a first step diagram of the method of manufacturing the semiconductor memory device in the related art.

FIG. 48 is a second step diagram of the method of manufacturing the semiconductor memory device in the conventional technique.

FIG. 49 is a third step diagram of the method for manufacturing the semiconductor storage device in the conventional technique.

FIG. 50 is a fourth step diagram of the method for manufacturing the semiconductor memory device in the conventional technique.

FIG. 51 is a fifth process chart of the method of manufacturing the semiconductor memory device in the related art.

FIG. 52 is a sixth process chart of the method of manufacturing the semiconductor memory device in the related art.

FIG. 53 is a seventh process chart of the method of manufacturing the semiconductor memory device in the related art.

FIG. 54 is an eighth step view of the method for manufacturing the semiconductor memory device in the related art.

FIG. 55 is a ninth step diagram of the method for manufacturing the semiconductor storage device in the related art.

FIG. 56 is a tenth step diagram of the method for manufacturing the semiconductor storage device in the related art.

FIG. 57 is an 11th step diagram of the method for manufacturing the semiconductor storage device in the related art.

FIG. 58 is a twelfth step diagram of the method for manufacturing the semiconductor memory device in the related art.

FIG. 59 is a schematic view showing a problem of the semiconductor memory device in the related art.

[Explanation of symbols]

1 semiconductor substrate, 2 isolation oxide film, 3 gate oxide film,
4 gate electrode, 5 first impurity region, 5 a high concentration impurity region, 5 b low concentration impurity region, 6 second impurity region, 7 bit line, 7 a doped polysilicon film, 7
b tungsten silicide film, 8 sidewalls,
9 first interlayer oxide film, 10 storage node contact hole, 11 bit line contact hole, 12 storage node, 13 second interlayer oxide film, 14 dielectric film, 15 cell plate, 16 third interlayer oxide film, 17
Wiring layer, 18 grooves, 100 transfer gate transistor, 200 stacked type capacitor.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor, Toto Yamagata 4-1-1, Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation ULS I Development Laboratory (72) Inventor, Kazuyasu Fujishima, Hyogo 4-1-1 Mizuhara, Itami City, Mitsubishi Electric Corporation, Kita Itami Works (56) References JP-A-60-149160 (JP, A) JP-A-3-22559 (JP, A) JP-A-3-64967 ( JP, A) JP-A-4-97566 (JP, A) JP-A-4-258117 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8242 H01L 21/3065 H01L 21/316 H01L 21/76 H01L 27/108

Claims (1)

(57) [Claims] A semiconductor substrate having a 1. A main surface, a separation insulating film you define the active region of the main surface of said semiconductor substrate, a first conductive layer formed on said main surface, said main A defect formed to a predetermined depth in the active region on the surface
Exposing the impurity region while covering the pure region and the semiconductor substrate
An insulating layer having an opening to be formed, and a second conductive layer connected to the impurity region in the opening.
An electrical layer , provided at an end of the isolation insulating film on the impurity region side,
And a groove communicating with the semiconductor substrate, wherein the insulating layer is embedded in the groove.
To, the semiconductor memory device.