JPS61108163A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the occurrence of software errors due to alpha rays and the like, by electrically connecting the internal electrodes of a groove capacitor, which is formed in a semiconductor substrate, with the diffused layer of an MOSFET through a window of the insulating film of capacitor at the inner surface of the groove. CONSTITUTION:A groove 19 is formed in a p type Si substrate 1. A capacitor insulating film 2 is provided at the inner surface of the groove 19. In the inside of the groove 19, polycrystalline Si 3, in which phosphorus is doped, is embedded. The film 2 is etched, and a window 4 is formed. In this window, polycrystalline Si 22, in which phosphorus is doped, is embedded. A gate insulating film 6 is formed on an oxide film 5, which is provided on the surface of Si 22. Source and drain diffused layers 8 are formed with a gate electrode 7 as a mask. At this time, at the part of the window 4, phosphorus is diffused to the side of substrate from the Si 22, and a diffused layer 9 is formed. Said layer and the layers 8 are connected beneath the film 5. In this constitution, since electrode charges are stored in the groove 19, the device is resistant against software errors due to alpha rays and the like. Since the grooves can be arranged in close proximity, integration density can be made high.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device and manufacturing method for realizing a large-capacity dynamic random access memory.

[Prior art]

A memory unit (cell) consists of one MOS transistor and one
Dynamic random access memory (DRAM), which consists of multiple capacitors, is currently the mainstream of high-density, large-capacity semiconductor memory. 1 per chip
In order to realize a DRAM with a storage capacity of M bits or more, the key is how small the capacitor area in the cell area can be made as viewed from the surface. Drill a groove in the silicon substrate to reduce the area seen from the surface of the capacitor.
A method of forming a capacitor using the surface of this groove has been proposed (1982 International
ElectronDevices Meeting
, Technical Dlgest, PP, 8
06 [Problems to be solved by the invention] However, although the structure proposed in the above paper is effective in reducing the cell area seen from the surface,
When deep grooves are formed by making the distance between adjacent cells close,
Since the charge is stored on the substrate side, there is a problem in that the charge between the grooves is likely to leak due to punch-through. Furthermore, in this proposal, charges are stored along the grooves in the depth direction of the substrate in close proximity to the grooves of adjacent cells, so when an α charge is irradiated, the accumulated charges are removed by the generation of carriers. The problem was that it disappeared easily.

The purpose of the present invention is to eliminate the disadvantages of charge leakage due to bunch drop-through caused by narrow groove spacing and vulnerability to soft errors due to alpha rays, etc., and to provide a 4M cell with a small cell area.
It is an object of the present invention to provide a semiconductor memory device having a structure of a memory cell having an improved trench capacity and a manufacturing method that can be applied to a DRAM of more than one bit.

[Failure to solve the problem]

In the memory pot cell of the semiconductor storage device according to the present invention, a groove is formed on the entire surface of a first conductivity type semiconductor substrate, a capacitive insulating film is formed on the surface of the groove, and a window is opened in a part of the capacitive insulating film. a second conductivity type semiconductor is embedded in the groove via the capacitive insulating film; a MOS transistor having a second conductivity type channel is formed near the groove; Either the source or drain diffusion layer of the transistor is electrically connected to the second conductive type semiconductor through the front and rear windows.

The charges thus stored are accumulated inside the trench capacitor through the transistor. At this time, the other electrode, the substrate side, is biased to a constant potential1.As the charge is stored inside the grooves, even if the groove spacing becomes narrow, there will be no charge leakage due to punch-through. . Furthermore, even if carriers are generated inside the substrate due to irradiation with alpha rays, etc., the substrate is always biased at a constant potential, so it is not affected. Since the bidirectionally accumulated 'charges also exist inside the groove, they are hardly affected by alpha rays, etc.

Note that the method for manufacturing the semiconductor memory device is the first method! Lm
A first coating having etching resistance is formed on one main surface of the semiconductor substrate, a groove is formed in the semiconductor substrate using this coating as a mask, and capacitive insulation is formed on the inner wall and bottom surface of the groove. forming a film, burying a first second conductivity type semiconductor in the groove, and forming a second film having etching resistance on the first second conductivity type semiconductor;
This second groove is opened so that a part of the periphery of the opening of the groove is exposed.
A window is formed in the film, and the first and second conductive type semiconductors and a part of the capacitor insulating film are etched using the first and second films as masks, and a second window is formed in the opening formed by this etching. embedding the second conductivity type semiconductor of the first conductivity type semiconductor;
and forming an insulating film on the surface of a second second conductivity type semiconductor, forming a MOS transistor having a second conductivity type channel on the surface of the semiconductor substrate opposite to the window,
One of the source and drain diffusion layers of the S transistor is electrically connected to the first and second second conductivity type semiconductors inside the first conductivity type semiconductor substrate.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view of a cell structure of an embodiment of a semiconductor memory device according to the present invention. Here, the case of an N-channel MOS transistor will be explained.

In FIG. 1, a reactive film is applied to a P-type silicon substrate 1.
The groove 19 is formed by anisotropic etching such as ion etching.
is being processed. A capacitive insulating film 2 is provided on the inner surface of the trench 19, and polycrystalline silicon 3 doped with phosphorus is buried inside the trench 19. Furthermore, the capacitive insulating film 2
In order to open the window 4, this part of the polycrystalline silicon 3
This window 4 is provided by selectively etching the capacitor insulating film 2 by the depth of the window and then etching the exposed capacitor insulating film 2. Polycrystalline silicon 22 doped with phosphorus is buried here again. The gate insulating film 6 is formed on several thousand^ of oxide films 5 provided on the surface of the polycrystalline silicon 220. The source mid-drain diffusion layer 8 is I) RAM
The word line 25 is formed by ion implantation or the like using the gate electrode 7 as a mask. At this time, in the window 4 portion, phosphorus is diffused from the polycrystalline silicon 22 toward the substrate side to form a diffusion layer 9, but this diffusion layer 9 and the source/drain diffusion layer 8 are connected under the oxide film 5. has been done. Further, the diffusion layer 8 is connected to the bit line 11 through a contact window 23 provided in the interlayer insulating film 10 .

Further, FIG. 2 is a plan view of the present cell structure, and a region 19 shaded by 0 is a groove pattern. The polycrystalline silicon inside the groove and the source/drain diffusion layer are connected at the part indicated by the thick line 9. Contacts to bit lines (not shown) are indicated at 24 and word lines at 25. As is clear from FIG. 2, this cell structure has no waste even in a planar arrangement and is suitable for high integration.

As described above, in the cell structure of the semiconductor memory device of the embodiment, the polycrystalline silicon 3 in the trench and the source/drain diffusion layer 8 are connected via the diffusion layer 9, so that the cell area increases due to the connection. There isn't.

Next, an embodiment of the method for manufacturing the semiconductor memory device of this embodiment will be described with reference to the manufacturing process diagrams of FIGS. 3(a) to 3(g) and FIG. 1.

Engineering@1. (FIG. 3(a)) The P-type nested crystal silicon substrate 1 is, for example, I
The substrate has a boron concentration of about 3. 5 on board 1
Silicon oxide film 17 and silicon nitride film 18 around 00X
to form. Next, after patterning the photoresist film, the empty silicon film, the 18-oxide silicon film 17, and the silicon substrate 1 are etched using the photoresist film as a mask to form a groove 19. In this case, the silicon oxide l]1i17 and the silicon nitride film 18 correspond to the first film in the claims. Next, boron was added to the inner surface of the groove at a surface concentration of 1×10 to 1×10 crIr−.
Diffusion to about 3. This is to prevent formation of an inversion layer on the surface of the substrate. Subsequently, a capacitor insulating film 2 is formed on the inner surface of the capacitor 19. The thickness of this film is preferably 100 to 20 OA W in terms of silicon oxide film. If silicon oxide alone cannot provide a breakdown voltage, a double film of silicon oxide film 17 and silicon nitride film 18 is used.

Step 2 (Fig. 3(b)) Polycrystalline silicon 3 is filled in the trench 19 by vapor phase growth of polycrystalline silicon and etching of unstable parts. This polycrystalline silicon 3 is doped with phosphorus etc. and is sufficiently N-type. O step 3 (FIG. 3(C)) where the resist film 20 needs to be bright is coated and patterned to open a window 21.

Step 4 (FIG. 3(d)) Using the resist film 20 and the silicon nitride film 18 as a mask, a portion of the polycrystalline silicon 3 is etched. Subsequently, a portion of the capacitor insulating film 2 is etched to form a hole 4.

Step 5 (FIG. 3(e)) This hole 4 is filled with polycrystalline silicon 2 which is sufficiently N-doped.
Fill it with 2.

Step 6 (FIG. 3(f)) Using the silicon 9ide film 18 as a mask, polycrystalline silicon 3 and 22 are selectively oxidized to 3,000 to 6, oooX
An oxide film 5 of S degree is formed. At this time, as shown in the figure, N-type impurities are diffused from the polycrystalline silicon toward the substrate side, and an N-type diffusion layer 9 is formed. Alternatively, the N-type diffusion layer 9 is formed sufficiently deep by adding heat treatment.

Step 7 (Figure 3(g)) Silicon nitride film 18. After etching the silicon oxide film 17, a gate oxide film 6 having a thickness of, for example, about 1508 is formed. Next, a gate electrode 7 is formed of polycrystalline silicon, silicide, a double layer film of polycrystalline silicon and silicide, or a high melting point metal. This electrode 7 functions as a word line (X address) in the memory array. Using this gate electrode 7 as a mask, ions of, for example, arsenic are implanted to form an N+ type source/drain diffusion layer 8 with a junction depth of about 0.1 to 0.211 m. This r-diffusion layer 8 must be connected to a diffusion layer 9 formed by diffusion from polycrystalline silicon. As a result, the charges to be stored are introduced into the inner capacitance of the groove capacitor 3 through the transistor.

Step 88 (FIG. 1) Next, after forming an interlayer insulator 10, a contact window 23 reaching the N+ diffusion layer is opened, and a bit line (data line) is formed using, for example, an aluminum wiring 11.

The main point of the manufacturing method according to this embodiment is to connect the N+ diffusion layer and the internal electrode of the groove capacitor through the window 4 provided in the side wall of the groove.

In order to ensure this connection, it is necessary to push the diffusion layer 9 to a sufficient depth in the lateral direction of the substrate. If the impurity diffusion from the polycrystalline silicon 22 is insufficient, the diffusion layer 9 shown in FIG. In e), a sufficiently deep diffusion layer 9 can be formed by performing phosphorus diffusion before or after embedding the polycrystalline silicon 22. In this example, the manufacturing process was explained only for the main part of the cell, so there was no space between the cells. In actual memories, device isolation between cells is essentially important, but in the memory cell of the present invention, deep device isolation is not required, and a conventional shallow ( (about 0.3 to 0.5 μm)
Separation is fine. The steps necessary for this separation can be performed using the LOCO8 method before or at the same time as FIG. 3(f) in this step, or after FIG. 3(f). Therefore, it is possible to perform element isolation that is suitable for the construction method. Particularly in a memory with IM bits or more, the waste separation method is desirable.

Although the embodiment above is for an N-channel MOS transistor, the present invention can also be applied to a P-channel MOS transistor.

Further, the basis of the present invention is to establish an electrical connection between the internal electrode of the trench capacitor and the source/drain diffusion layer of the MOS transistor. Therefore, other parts of the cell structure may be changed in any way.

〔Effect of the invention〕

As explained above, in the present invention, the diffusion layer of the MOS transistor and the electrode of the trench capacitor are connected on the side surface of the trench, so there is no increase in the cell area due to the connection, and the trenches can be placed close to each other. Therefore, the integration density is high, and since charge is stored inside the groove, it has the effect of being resistant to soft errors caused by alpha rays and the like.

The present invention has the effect of reducing the capacity because soft errors occur and separation occurs.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a cell of an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a plan view of a cell of an embodiment of a semiconductor memory device according to the present invention, and FIGS. Figure 1, 2nd
FIG. 2 is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor memory device shown in the figure. 1... Silicon substrate, 2... Capacitive insulating film, 3.2
2...Polycrystalline silicon, 4...Window, 5...Oxide film, 6...Gate oxide film, 8.16...Source
Drain diffusion no, 9... Diffusion layer, 17... Titanium oxide film, 18... Titanium nitride film, 19... Groove, 20... Resist film, 21... Window.

Claims (2)

[Claims] (1) A groove is formed on one main surface of the first conductivity type semiconductor substrate, a capacitive insulating film is formed on the inner surface of the groove, and a window is opened in a part of the capacitive insulating film; A second conductivity type semiconductor is embedded in the groove via a capacitive insulating film, a MOS transistor having a second conductivity type channel is formed near the groove, and a source of the MOS transistor is formed in the vicinity of the groove. Alternatively, a semiconductor memory device characterized in that either one of the drain diffusion layers is electrically connected to the second conductivity type semiconductor through the window. (2) a groove is formed in one main surface of the first conductivity type semiconductor substrate, a capacitive insulating film is formed on the inner surface of the groove, and a window is opened in a part of the capacitive insulating film; A second conductivity type semiconductor is embedded in the groove via a capacitive insulating film, a MOS transistor having a second conductivity type channel is formed near the groove, and a source of the MOS transistor is formed in the vicinity of the groove. Alternatively, in the method for manufacturing a semiconductor memory device, in which either one of the drain diffusion layers is electrically connected to the second conductivity type semiconductor through the window, the semiconductor forming a first coating having etching resistance on the substrate; forming a groove in the semiconductor substrate using the first coating as a mask; and forming a capacitive insulating film on the inner wall and bottom surface of the groove. a step of embedding a first second conductivity type semiconductor in the groove; a step of forming a second coating having etching resistance on the first second conductivity type semiconductor; forming a window in the second coating so that a part of the periphery of the opening is exposed; and using the first and second coatings as masks, the first second conductivity type semiconductor and the capacitive insulation a step of etching a part of the film; a step of embedding a second second conductivity type semiconductor into the opening formed by the etching; and forming an insulating film on the surfaces of the first and second second conductivity type semiconductors. forming a MOS transistor having a second conductivity type channel on the surface of the semiconductor substrate facing the window, and either one of the source or drain diffusion layer of the MOS transistor is connected to the first and second diffusion layers. A method of manufacturing a semiconductor memory device, comprising the step of electrically connecting a second conductive type semiconductor to the inside of the first conductive type semiconductor substrate.