JPH0444428B2 - - Google Patents

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Overview of the disclosure C. Prior art D. Problem to be solved by the invention E. Means for solving the problem F. Example f1 Structure of memory cell f2 Manufacturing process of memory cell f3 Operation of memory cell G. Effect of the invention A. Industrial application field This invention is broadly applicable to dynamic, random,
Regarding an access memory (DRAM) cell, in particular, a storage capacitor of the cell is arranged in a trench formed in a semiconductor substrate.
It concerns DRAM cells. More particularly, the present invention provides at least a portion of the substrate being heavily doped to form the counter electrode of the storage capacitor, and a heavily doped polycrystalline plug disposed in a trench capacitor on the other hand. This relates to DRAM cells that form electrodes.

B. Summary of the Disclosure This DRAM cell includes a field effect transistor (FET) in a well region having a conductivity type opposite to that of the substrate. The well region itself is formed in a lightly doped portion of the substrate;
It can have either n- or p-type conductivity type with other parts having a conductivity type suitable for devices manufactured in a CMOS environment.
A trench capacitor extends through the well region and the lightly doped portion of the substrate from the surface of the well to the heavily doped portion of the substrate. Further, the electrode placed in the trench is connected to the source or drain of the FET for direct access.

C. Prior Art Recent technical literature emphasizes "single device" memory cell configurations in which higher integration densities are pursued. In most cases, high device integration densities are achieved by bringing the access transistors and storage capacitors closer together to reduce cell area while simultaneously increasing the storage capacitor. In the prior art, capacitance is increased by thinning the oxide film, increasing the area of the capacitor, or forming a trench capacitor in the semiconductor substrate.

Now, commonly assigned US patent application Ser. No. 620,667 discloses a DRAM cell in which a trench capacitor extends into a heavily doped substrate which acts as the counter electrode of the capacitor.
In addition, in close proximity to the trench capacitor
A FET access transistor is disposed, and the source or drain of the access transistor is directly connected to the electrode of a capacitor disposed within the trench. In this configuration, an insulating layer electrically isolates the access transistor from other similar cells and the heavily doped substrate. However, the above application discloses a cell in which the access transistor is formed in a well region disposed in a semiconductor region of opposite conductivity type.
It is not concerned with manufacturing DRAM cells in a CMOS environment. That is, considering that the structure of the present invention has such a well region and further includes a trench capacitor extending through the well region to the heavily doped region of the substrate, the present invention has the above-mentioned structure. U.S. Patent Application No. 620667
A line is drawn from the issue.

Proceedings of the 10th Solid State Device Conference held in Tokyo in 1978, Bulletin of the Japan Society of Applied Physics 18-1,
“Novel high-density stacked capacitor MOS” by M. Kobayashi et al., pp. 35-42.
RAM (Novel High Density, Stacked
The paper entitled ``Capacitor MOS RAM'' describes a DRAM cell that uses stacked capacitors on top of the corresponding access transistors. This structure allows the source of the access transistor to connect directly to one electrode of the capacitor. However, this paper does not mention trench capacitors, nor does it suggest the use of trench capacitors in connection with access transistors placed in n-type or p-type well regions. It has not been.

IEEE Electron Device Letters,
Vol. ED6-4, No. 4, April 1983, pages 90-91, "A Corrugated Capacitor Cell (CCC) for Megabit Dynamic MOS Memory" by H. Sunami et al.
A paper titled ``Megabit Dynamic MOS memoies'' has been published, which discloses a one-device memory characterized by a storage capacitor etched in the form of an extended trench in the substrate. Structurally, the storage device is placed alongside the access transistor, and the moat-like region is insulated and filled with polysilicon to form one plate of the capacitor. Furthermore, a depletion region is formed in the semiconductor substrate around the moat-like region, which prevents punch-through when a positive voltage is applied to the polysilicon capacitor electrode. A minimum spacing between trench regions is required, which limits the integration density of the device.Also, the substrate is P ^- to form an inversion region in the substrate that serves as the storage electrode. The paper must be of conductive type, and this is highlighted in the paper by using the substrate as a common counterelectrode, or by using trenches in heavily doped regions to obtain a certain amount of capacitance. This suggests that no consideration has been given to penetrating the well region.On the other hand, in the structure of the present invention, at least one portion of the substrate is provided with a counter electrode for all DRAM cells formed on the chip. Some parts must be heavily doped.
Since the storage electrode is arranged in the trench and insulated from the counter electrode, no short-circuiting of the capacitor occurs. Furthermore, in this conventional structure, there is no direct connection between the source and drain diffusion regions and the polycrystalline material disposed in the trench region, and the access transistor is disposed within the well region. do not have.

IEDM83, December 1983, pages 319-322, K. Minegishi et al.
CMOS megabit level dynamic RAM
Technology (A Submicron CMOS Megabit Level
Dynamic RAM Technology Using Doped
The paper entitled ``Tace Trench Capacitor Cell'' discusses a RAM cell in a CMOS environment, and the walls are heavily doped to form an extended source-drain region for the corresponding access transistor. A polycrystalline electrode is disposed in the trench insulated and separated from the substrate, and this serves as the counter electrode of the capacitor.However, in this structure, a heavily doped substrate is required. The substrate cannot be used as a counter electrode, as this would reduce the performance of the transistor, i.e. in no case should the capacitor penetrate the well region, and between the source of the access device and the electrode in the capacitor trench. There is no direct connection to .

U.S. Pat. No. 4,397,075 discloses a structure in which capacitance is increased by extending a drain diffusion region into a well region etched into a semiconductor substrate. However, the capacitor element is not provided independently, and the increase in capacitance is a direct result of increasing the pn junction area of the drain.

US Pat. No. 4,327,476 discloses a one-device memory cell with a capacitor electrode placed in a groove or trench. The electrodes are formed along the source/drain regions and are insulated and separated from the substrate. However, there is still no connection between the capacitor electrode and the source/drain region in the trench. Also, this document does not suggest the use of wells or trenches penetrating into portions of the heavily doped substrate.

IBM Technical Disclosure Bulletin, Vol.25,
No. 7, July 1982, page 593, CG Gambotkdr's “High Density One Device
Memory Cell (Very Dense One−Device
The paper entitled ``Memory Cell'' describes a one-device memory cell in which a drain diffusion region is formed around a trench, the inside of the trench is covered with an insulating layer, and the remaining recessed area is covered with an insulating layer. Polyimide is polysilicon or
Filled with _SiO2 . Although the trench is formed in the cell, no separate capacitor is formed within it. That is, this fabrication is simply an extension of the drain diffusion region to increase junction capacitance.

From the above, the above-mentioned prior art discloses a memory cell in which an access transistor and a corresponding trench capacitor are formed in a well region disposed in a substrate of opposite conductivity type. It is clear that this is not the case. As a result, in prior art structures incorporating well regions,
The magnitude of the capacitance is limited because it is not considered that the trench penetrates the well region and achieves most of the capacitive effect in the heavily doped counterelectrode portion of the substrate. Thus, in the prior art, a trench capacitor extends from or passes through the well region to the heavily doped substrate, and the source of the access transistor is directly connected to an electrode located inside the trench. The combination of an access transistor and a trench capacitor in the well region as shown is not shown.

D. Problems to be Solved by the Invention The main object of the invention is to solve the problem in the case where an access transistor and a trench capacitor are both formed in a well region in a semiconductor substrate.
Our goal is to provide DRAM cells for devices.

Another object of the present invention is to provide a method in which the depth of the trench capacitor is greater than the depth of the well region in which the corresponding access transistor is formed.
Our goal is to provide DRAM cells.

Yet another object of the invention is to provide a DRAM cell in which the trench capacitor extends from the well region into the heavily doped region, where the majority of the cell's capacitance is obtained. .

Still another object of the present invention is to prevent punch-through between adjacent capacitor trenches.
To provide a DRAM cell that is free from "through" and is less susceptible to soft errors caused by alpha particles inherent in memory cells using relatively high resistivity substrates. It is in.

Still another object of the present invention is to provide a DRAM cell that is less susceptible to soft errors due to injection of fractional carriers from peripheral circuits.

E. Means for Solving the Problems The present invention relates to a DRAM cell that utilizes a FET access transistor and a storage capacitor, both of which are formed in a well region of a semiconductor substrate. The well region is comprised of a material of the opposite conductivity type as the substrate and includes the source and drain of the access transistor and the channel region. Additionally, a trench is provided extending through the well region into the heavily doped substrate region, which serves as the counter electrode of the storage capacitor. The storage capacitor electrode is insulated and spaced apart from the substrate and is made of heavily doped polycrystalline silicon. Its electrode is connected to the source of the access transistor by a bridging region. The basic structure of the DRAM cell is then completed by the polycrystalline gate placed on the channel region. The well region formed in the substrate is of one of p to n ⁻ conductivity types. and when the well region is in one conductivity type, the substrate is in the opposite conductivity type to which it is heavily doped and includes a region of the same conductivity type that is more lightly doped than that for locating the well region. There is. The lightly doped region forms a transition region from the heavily doped region of the substrate to the well region of the opposite conductivity type, thereby reducing breakdown at the junction between the two regions.
Note that the heavily doped region of the substrate not only serves as a counter electrode for the trench capacitor, but also serves to provide the memory cell with properties that reduce the effects of soft errors due to the incidence of alpha particles.

In the cell of the present invention, a constant voltage is applied to the well region, and the polysilicon gate of the access transistor forms part of a word line that contains multiple cells of an array.
DRAM cells are connected. Similarly, the sources and drains of the FET access transistors are connected to bit lines to which the DRAM cells of an array are connected. Binary information can then be read and written to the storage capacitor by applying appropriate word and bit line voltages to the access transistors.

The DRAM cell of the present invention can be implemented using either p-channel or n-channel access transistors. The conductivity types of the source and drain regions govern the conductivity type of the polycrystalline silicon used as the capacitor electrode.

Techniques for manufacturing the DRAM cell structure of the present invention are also disclosed. This manufacturing method is not very different from the processes used to manufacture CMOS devices. However, one difference is that after the formation of the well region in the lightly doped portion of the substrate, reactive ion etching is performed from the surface of the well region through the well region to the heavily doped portion of the substrate. This means forming an extended trench. The trench is then lined with an insulating material and filled with a polycrystalline material. A second layer of polycrystalline silicon is then used to form a bridging region connecting the electrode in the trench to the source region of the access transistor. Portions of the source region are formed when the bridging region diffuses out the dopants during a subsequent anneal step. The resulting structure has good geometry, is not limited by the minimum spacing of traditional trench capacitors, and is less susceptible to soft errors that occur in traditional DRAMs.

F Example f1 Structure of Memory Cell In the drawing, the access transistor 2 is characterized as having a source region and a drain region. For convenience of explanation, it is assumed here that the drain region is a region connected to the bit line of the memory array. In addition, trench
The electrode of the capacitor 3 is the electrode where charge is stored via the access transistor 2,
On the other hand, the counter electrode is the electrode into which the charge is introduced.

FIG. 1 now schematically shows a partial cross-sectional view of a DRAM cell 1 according to the invention, in which an access FET transistor 2 and a trench capacitor 3 are preferably made of silicon. It is formed in the semiconductor substrate 4. The access transistor 2 is formed in an n-type well region 5 and has a source region 6 and a drain region 7, which are heavily doped regions of p ⁺ conductivity type. N-type well region 5
is formed in a lightly doped p ^- conductivity type portion 8 of the substrate 4. Additionally, a perforated oxide (ROX) region 9 serves to separate the memory cell 1 from other memory cells on the substrate 4. In FIG. 1, a trench capacitor 3 is formed from a trench 10. In FIG. A trench 10 extends from the surface of the substrate 4 through the n-well region 5 and the lightly doped portion 8 of the substrate into the heavily doped p ⁺ conductivity type portion 11 of the substrate 4 .
A plug 12 made of heavily doped polycrystalline silicon of p ⁺ conductivity type is placed in the trench 10 and insulated from the substrate 4 by an insulating layer 13 . Insulating layer 13 may be a single silicon dioxide layer, but is preferably a composite layer of silicon dioxide, silicon nitride, and silicon dioxide. The source region 6 and the plug 12 are physically and electrically connected by a bridging region 14 made of heavily doped p ⁺ conductivity type polysilicon. It should be noted that the bridging region 14 may be any conductive material that is available during this process. A gate electrode 15 made of heavily doped n ⁺ conductivity type polysilicon is placed over the channel region between the source region 6 and the drain region 7 so as to be insulated therefrom by a thin gate oxide film 16. ing. Gate electrode 1
5 is connected via a connection 17 to another gate electrode WL1 of the array of DRAM cells.

In FIG. 1, a heavily doped polycrystalline silicon element 18 of n ⁺ conductivity type is disposed on plug 12 and is insulated from plug 12 by an oxide film. The element 18 forms a connection to the gate electrode of the adjacent DRAM cell 1, so that
The area on the trench capacitor 3 can be utilized without any deterioration of the device characteristics, resulting in a significant reduction in the area of the memory cell. Note that the element 18 is connected via the connection 19.
Another gate electrode WL of the array of DRAM cell 1
Connected to 2. Drain region 7 serves as a bit line for all DRAM cells connected to one of the bit lines of an array of DRAM cells 1. In addition, the drain region 7 is connected to the drain of another device via the connection 20.
Connected to BL. Although not specifically shown in FIG. 1, the wire connection 20 is typically made of a metal wire such as aluminum.

In FIG. 1, a power supply 21 is connected to the n-type well region to supply a bias voltage V. On the other hand, as shown in the figure, the board 4 is
2 to ground potential. Further, the connections 17 and 21 are connected to pulse voltage supply sources 23 and 24.
are connected to each other. These power sources 2
3 and 24 have the function of writing binary information into the trench capacitor 3 by controlling the potential level. Note that the specific voltages of the pulse power supplies 23 and 24 will be mentioned when explaining the operation of the DRAM cell 1.

Please note the following. That is,
The trench capacitor 3 has an n-type well region 5,
As a result of passing through the p-n junction with the lightly doped p ^- conductivity type portion 8, there is no limit to the capacitance that can be obtained. On the other hand, conventionally, the capacitance that can be obtained has been limited by the thickness of the epitaxial layer.

Next, FIG. 2 is a plan view of the DRAM cell 1 shown in FIG. 1. In the layout of FIG. 2, the positional relationship of the trench capacitor 3 with respect to the access transistor 2 and the adjacent
The positional relationship of DRAM cell 1 with respect to DRAM cells is shown. Now, in order to keep the area occupied on the substrate small, the trench capacitor 3 is first placed adjacent to the right end of the lower DRAM cell 1 in FIG. Also, the upper
Regarding the DRAM cell 1 as well, a trench capacitor 3 is arranged adjacent to the left end of the cell 1 along the connection line 17. The area above this trench capacitor 3 is then covered with an oxide film. In this way, in Figure 2,
WL1 or connection 17 is connected to the gate electrode 15 of DRAM cell 1 located below and connected to the gate electrode 15 of DRAM cell 1 located below.
It extends over the trench capacitor 3 of the DRAM cell 1. Similarly, WL2 is
The trench capacitor 3 of the lower DRAM cell 1 is connected to the gate electrode 15 of the DRAM cell 1.
extended above. Therefore, as shown in Figure 2,
By repeating the pattern of the set of DRAM cells 1, the area occupied on the substrate can be considerably reduced.

f2 Memory Cell Manufacturing Process Next, referring to FIG. 3, the figure shows a cross-sectional view of the manufacturing process after the n-type well region 5, ROX region 9, and trench capacitor 3 have already been formed. be. Manufacturing of DRAM cell 1 is as follows:
It begins by depositing an epitaxial layer of silicon of p ^- conductivity type with boron-doped silane. This forms a portion 8 of the silicon substrate 4 for forming the access transistor 2 and the trench capacitor 3. The doping level in part 8 is 2
×10 ¹⁵ atoms·cm ⁻³ , while the doping level in portion 11 is 1×10 ¹⁹ atoms·cm ⁻³ .

After deposition of the substrate portion 8, an oxide layer is thermally grown on the top surface of the substrate. A photoresist layer is then deposited over this oxide layer and patterned using known techniques to form an opening for implanting ions to form an n-well region 5. be done. In order to obtain a recessed doping profile in the n-type well region 5, a shallow ion implantation step is performed after the deep ion implantation step. This deep ion implantation step forms a highly conductive region near the bottom of the n-well region 5, which would have occurred if the n-well region 5 had remained highly resistive. However, the noise problem is solved. In this case, arsenic or phosphorus is ion-implanted by known methods to a depth that does not penetrate portion 8 of substrate 4. Next, the substrate 4 is annealed to activate the implanted species. This implanted dopant has a concentration of 10 ¹⁷ atoms/cm ^-3 near the bottom of the implant, while at the surface of the n-well region 5 it has a concentration of 2×10 ¹⁶ atoms/cm
^-3 concentration. After thermally oxidizing the surface, a nitride layer is deposited over the entire surface. A photoresist layer is then deposited and patterned to etch openings in the nitride and oxide layers to expose the portions of the surface of the substrate 4 where the ROX region 9 is to be formed. At this time, an etching agent such as H ₃ PO ₄ is used to etch the nitride layer.
Buffered to etch the oxide layer
An etching agent such as HF is used. By using a thermal oxidation process, a ROX region 9 is formed after the photoresist is removed;
The ROX region 9 serves to separate the DRAM cell 1 from other similar cells on the substrate 4.

Prior to forming trench 10, a photoresist is deposited over the nitride layer and the photoresist is patterned. The substrate 4 is then subjected to a reactive ion etching (RIE) step, which removes the unmasked areas of the substrate 4 to the desired depth. In this step, the trench 10 is
The nitride and oxide layers and portions 8, 11 of the substrate are removed to a depth at which the nitride and oxide layers are formed. Next, a layer 13 is formed on the surface of the trench 10 using alternating layers of oxide layers, nitride layers, and oxide layers. Then, the surface of the thermally grown oxide layer and the ROX
A nitride layer is deposited on the surface of the nitride layer between the regions 9 and on the surface of the ROX region 9 by CVD.
The substrate 4 is then subjected to a thermal oxidation step whereby an oxide layer is thermally grown into the pin holes that may be present on the previously deposited nitride layer. This multilayer process not only eliminates pin holes in the resulting layer, but also serves to prevent dopants from diffusing out of the heavily doped p ⁺ polycrystalline silicon.
This is because the nitride layer is an effective diffusion barrier.

Next, CVD from boron-doped silane
The method deposits heavily doped polycrystalline silicon, thereby forming a layer of p ⁺ conductivity type.
This layer is deposited to a depth sufficient to fill trench 10. Substrate 4 is then subjected to reactive ion etching to remove the polycrystalline silicon layer to the top of trench 10 and planarize the surface of substrate 4. At this time, the nitride layer deposited during the formation of the trench insulation layer 13 and
The nitride layer between the ROX regions 9 serves as an etch stop layer during the reactive ion etch (RIE) planarization process using well known optical end-point detection techniques. At this point, the DRAM
The cell 1 has a structure as shown in the cross-sectional view of FIG.

FIG. 4 shows that a thin heavily doped p ⁺ conductivity type layer is deposited and patterned to form a bridging region 14 on the insulating layer 13 between the source region 6 of the access transistor 2 and the plug 12. FIG. 3 is a cross-sectional view of the structure after

The structure of FIG. 4 is obtained by first adding a nitride layer 25 on top of the oxide and nitride layers formed during the formation of layer 13 on the inside of trench 10. Layers 16, 25 are then coated with a layer of photoresist. The photoresist layer is then patterned and developed using well known methods, thereby exposing a portion of the nitride layer 25. Next, reactive ion etching is used to remove a portion of the nitride layer 25 and the oxide layer 16, thereby removing the portion of the substrate that is to form part of the source region 6, the top surface of the plug 12, and the ROX region 9. is exposed. A thin layer of heavily doped p ⁺ conductivity type polycrystalline silicon is then deposited with boron-doped silane and patterned using well-known photolithographic and etching techniques, thereby forming the insulating layer 13.
A bridge region 14 is formed for connecting the source region 6 and the upper surface of the plug 12 which are separated from each other. By patterning this polycrystalline layer, a part of the surface of the substrate 4 is exposed.
A very shallow poron implant is then performed into the exposed portion of the substrate 4 using well known ion implantation techniques to form a portion of the source region 6. The rest of the source area 6 is
It is formed by diffusing dopants out of bridging region 14 during an annealing step to activate the shallowly implanted boron. still,
The diffused and emitted portion of the source region 6 is located in the insulating layer 1.
3, thereby reducing the area of the cell.

At this point, an oxide layer is thermally grown by using the nitride layer 25 as a mask, which oxide layer covers the exposed parts of the substrate 4 and the remaining exposed parts of the bridging region 14 and the plug 12. Form an insulating layer. At the same time, the ROX region 9 undergoes further growth such that the thickness of the region 9 becomes greater than the thickness formed by the initial ROX growth. In addition, in this process, another ROX
It is recognized that a process equivalent to the growth process may be performed again later. Therefore, the initial ROX growth step is limited to forming a fairly thin ROX region. As a result, reactive ion etching of trench 10 through the ROX region is simplified and ROX "bird's beak" formation is reduced.

After the growth of the oxide layer described above, the nitride layer 25 is removed by wet etching. and,
A heavily doped polycrystalline silicon layer of n ⁺ conductivity type is deposited and patterned using well known photolithographic and etching techniques;
In this way, gate electrode 15 and elements 18 and 19 for connecting to adjacent gate electrodes are formed as shown in FIG. At this point, the substrate 4 is subjected to a boron ion implantation step. Then, a self-aligned drain region 7 is formed in the substrate 4 using the ROX region 9 and the gate electrode 15 as a mask for ion implantation. At this time, the dopant concentrations in the drain region 7 and source region 6 are each 1×10 ²⁰ atoms/cm ^-3
and 1×10 ¹⁹ atoms·cm ⁻³ . After ion implantation into the drain region 7, the gate electrode 1
5. In order to insulate the device 18 from the surface of the substrate 4 into which the drain region 7 is ion-implanted, the substrate 4 is exposed to a thermal oxide layer growth process. The deposited photoresist layer is then exposed, patterned, and developed before the metal connections are deposited. The structure completed through the above steps is as shown in FIG. At this point, although only a single DRAM cell 1 is shown in FIG.
It should be appreciated that a DRAM cell is formed in the n-well region 5 and is simultaneously fabricated by the same method as described above. Furthermore, although what is shown in FIG. 1 is an n-type well region,
It should also be appreciated that type well regions can be used as well. At that time, of course, the conductivity types of the source region 6, drain region 7, and substrate portions 8, 11 are n-
The conductivity type must be changed.

The DRAM cells mentioned above are epitaxial
Compatible with CMOS technology. Also, as mentioned above, by preventing breakthrough current between trenches, high cell integration density can be achieved and soft errors can be reduced. moreover,
In the cell of the present invention, the stored charge is hardly disturbed. The resulting structure also has a relatively planar surface structure.

f3 Operation of memory cell In DRAM cell 1, pulse voltage source 2
4 to the drain 7 of the access transistor 2
A voltage of 0 or 5 volts is applied to. At the same time, 0 volts is applied to the gate electrode 15 to make the access transistor 2 conductive. Thus, since the substrate 4 is kept at ground potential, by applying 5 volts to the drain 7 and 0 volts to the gate electrode 15, thereby charging the plug 12 to 5 volts, the capacitor 3 receives the binary " 1” is written.
Further, both the drain 7 and the gate electrode 15 are
A binary "0" is written into the capacitor 3 by applying a voltage to charge the electrode 12 to a potential equal to the absolute value of the threshold voltage. These binary states are 0 at the gate electrode 15.
It can be read by adding bolts.

As mentioned above, the conductivity type shown in FIG. 1 for the DRAM cell 1 can be changed to the opposite conductivity type without departing from the technical scope of the present invention. That is, when the conductivity type is changed, the threshold voltage of the access transistor 2 is changed from 5 volts by applying 5 volts to both the drain 7 and gate electrode 15 while keeping the substrate 4 at ground potential. A binary "1" is written to the capacitor 3 by charging it to the value obtained by subtracting . Also, binary “0” is
Apply 0 volts to drain 7, gate electrode 15
is written to capacitor 3 by applying 5 volts to charge electrode 12 to approximately 0 volts. These binary states are then read out by applying 5 volts to the gate electrode 15.

G. Effects of the Invention As described above, according to the present invention, in a DRAM cell, a heavily doped substrate is used as one electrode of a capacitor, and a conductive material filled in a vertical trench region formed in the substrate is used as the other electrode. By using this electrode, the area occupied by the cell can be reduced, the integration density can be increased, and the capacitance of the capacitor can be increased. Further, since the structure provides sufficient insulation between cells, punch-through development is prevented.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing the structure of a dynamic RAM cell according to the present invention, and FIG.
3 and 4 are schematic cross-sectional views showing steps in the formation of the structure of FIG. 1. 2... FET transistor for access, 3...
Trench capacitor (charge storage means), 4...
Substrate, 5... well area.

Claims (1)

[Scope of Claims] 1 (a) a substrate of a first conductivity type, the upper portion of which is doped to be less conductive than the lower portion; (b) disposed within the upper portion of the substrate; (c) at least one access transistor disposed in the region; (d) extending from the surface of the region into the region and the upper portion; at least one storage capacitor electrode structure extending through the lower portion of the substrate and electrically isolated from the region, the upper portion of the substrate, and the lower portion of the substrate. cell.