JPH01160047A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the generation of a parasitic MOS transistor between a transfer transistor and storage capacitor, and to thin a dielectric film and lower applied voltage to the dielectric film by forming one conductivity type buried layer between an active region such as a source and a drain in the transfer transistor and a reverse conductivity type buried layer. CONSTITUTION:A MOSDRAM cell is composed of a p-type Si substrate 21, an n<+> buried layer 22, a p-type epitaxial layer 23, a field oxide film 24 isolating and insulating elements, a tranch section 25 to which storage capacitor C1 is shaped, an insulating film 26 such as an SiO2 film demarcating the region of the storage capacitor C1, and a p<+> buried layer formed by implanting B<+> ions, etc., to the p-type epitaxial layer 23 by high acceleration and high energy. The p<+> buried layer 28 is shaped between a drain 33 in a transfer transistor T1 and the n<+> buried layer 22 supplying a counter electrode 29a for the storage capacitor C1 with DC potential. Accordingly, the generation of a capacitance MOS transistor can be prevented.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor memory device and a method for manufacturing the same, in particular a structure of a highly integrated, high-performance M○S dynamic memory having a trench capacitor and a method for forming the same, and relates to a transfer transistor and a storage capacitor. The purpose is to reduce the thickness of the dielectric film and reduce the applied voltage by eliminating the generation of parasitic MOS transistors between the device and the field insulating film. A dynamic memory cell includes an impurity diffusion layer region, a gate electrode, and a storage capacitor, and the pair of impurity diffusion layers are formed in a semiconductor substrate of one conductivity type on a semiconductor substrate of one conductivity type. The storage capacitor is formed in a semiconductor layer of one conductivity type provided with a buried layer, and the storage capacitor selectively penetrates the semiconductor layer of one conductivity type and the buried layer of one conductivity type, and selectively penetrates the semiconductor substrate of one conductivity type. A counter electrode, a dielectric film, and a storage electrode are formed in a groove portion whose bottom is a buried layer of an opposite conductivity type, and one impurity diffusion layer of the transfer transistor and the storage electrode are formed by a conductive layer. The first manufacturing method is a step of selectively forming a buried layer of an opposite conductivity type between a semiconductor substrate of one conductivity type and a semiconductor layer of one conductivity type. selectively oxidizing the semiconductor layer of one conductivity type to form a field insulating film; and selectively trenching the semiconductor layer of one conductivity type to reach the buried layer of the opposite conductivity type. Form the groove, then
forming a first insulating film on the inner wall of the groove; and implanting impurity ions into the semiconductor layer of one conductivity type.
forming a buried layer of one conductivity type; forming a buried layer of opposite conductivity type to the first semiconductor layer of one conductivity type; forming a buried layer of one conductivity type by implanting impurity ions into the entire surface of the first semiconductor layer of one conductivity type; and the buried layer of one conductivity type. forming a second semiconductor layer of one conductivity type on the entire surface of the layer.

[Industrial application field]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a structure of a highly integrated, high-performance MOS dynamic random access memory (MO3DRAM) cell having a trench capacitor and a method of forming the same.

[Conventional technology] FIG. 5.6 is an explanatory diagram of a conventional example.

FIG. 5(a) shows an electric circuit of a MO3DRAM cell.

In the figure, T is Mos+, which transfers data (charge).
A transfer transistor composed of a transistor, etc., C is a storage capacitor (trench capacitor) that stores charge, WL
is a word line, and BL is a bit line. Note that 6 is a storage electrode, 7 is a dielectric film, and 8 is a counter electrode.

FIG. 5B is a cross-sectional view showing the structure of a P-channel MO3DRAM cell. In the figure, 1 is a p-type Si substrate such as a P-type epitaxial layer, 2 is a field oxide film formed by the Locos method, etc., and 3゜4 is an n゛ impurity diffusion layer formed by diffusing As'' ions, etc. This is the source or drain of the transfer transistor T.

5a and 5b are the insulation of the word line WL and the groove part of the storage capacitor C (
It is an insulating film that defines a trench), and is a 5in2 film or Si
3N4 film, etc. Reference numeral 6 denotes an electrode formed by doping a poly-Si film with impurity ions, and is a storage electrode constituting a storage capacitor C.

7 is a dielectric film formed of an insulating film such as a SiO□ film or a 513N4 film. Note that since the potential applied to the dielectric film 7 is the same as that of the P-type Si substrate 1, it is difficult to make the film thin. Reference numeral 8 denotes an electrode formed by doping impurity ions into a poly-Si film, and is a counter electrode constituting the storage capacitor C. A conductive layer 9 electrically connects the storage electrode 6 and the drain 3 of the transfer transistor T, and is formed of a poly-Si film or the like doped with impurity ions.

10 is a PSG film that insulates the conductive layer 9.

BL is a bit line formed of a poly-Si film containing impurity ions, a polycide film, an aluminum film, or the like.

FIG. 6 is a diagram illustrating the problems of the MO3 DRAM cell according to the conventional example. In figure (a), 11 is the counter electrode 8
n buried layer electrically connected to the n. Note that by applying a DC potential to the n'' buried layer, the voltage applied to the dielectric film 7 can be lowered to the potential of the p-type Si substrate 1.

Therefore, the dielectric breakdown voltage of the dielectric film 7 can be reduced, and the dielectric film can be made thinner.

FIG. 2B is an electric circuit diagram relating to the parasitic MOS transistor T0. In the figure, T represents the drain (n'' impurity diffused layer) in Figure (a), the n+ buried layer 11, the gate oxide film formed by the 5i02 film 5b, and the parasitic structure with the counter electrode 8 as the gate electrode. MO3) transistor is shown.The counter electrode 8 and the buried layer 11 are electrically connected.

[Problem that the invention seeks to solve]

By the way, according to the conventional example, as shown in FIG.
is composed of a storage electrode 6, a dielectric film 7, and a counter electrode, and data (charge) is transferred to the dielectric film 7 by a voltage applied between the drain 3 of the transfer transistor T and the P-type Si substrate 1. However, along with the miniaturization and high integration of semiconductor memory devices, the dielectric film 7 is required to be made thinner.Therefore, as shown in FIG. A buried layer 11 is provided which is electrically connected to the counter electrode 8 at the bottom of the
A method has been devised in which the voltage applied to the dielectric film 7 is alleviated by supplying the voltage 2.

However, as shown in the same figure (C), parasitic MO
3) Generates transistor T0, and this parasitic MO3) transistor T. Data (charges) charged (stored) may leak between the drain 3 and the buried layer 11 and be discharged. Further, there is a problem that soft errors and latch-up occur due to the incidence of α rays, and the reliability of the memory characteristics of the MO3 DRAM cell decreases.

The present invention was created in view of the problems of the conventional example, and it solves the parasitic MO between the transfer transistor and the storage capacitor.
It is an object of the present invention to provide a semiconductor memory device and a method for manufacturing the same, which can eliminate the occurrence of S transistors, convert the dielectric film into an 'a' film, and reduce the applied voltage.

[Means for solving problems]

As shown in FIGS. 1 to 4, an embodiment of the semiconductor memory device and the method for manufacturing the same of the present invention is such that the device is provided with a pair of impurity diffusion layers 32 in a region defined by a field insulating film 24 or 46. a transfer transistor T having a .33 or 52.53 region and a gate electrode WL or WF2;
or a dynamic memory cell comprising a storage capacitor C1 or C2, and the pair of impurity diffusion layers 32. ．． 33 or 52° 53 is formed in the semiconductor layer 23 or 45 of one conductivity type provided with the buried layer 28 or 48 of one conductivity type on the semiconductor substrate 21 or 41 of one conductivity type, and is connected to the storage capacitor CI or C2. selectively penetrates the semiconductor layer 23 or 43.45 of one conductivity type and the buried layer 28 or 48 of one conductivity type, and is selectively provided in the semiconductor substrate 21 or 41 of one conductivity type. A counter electrode 29a or 49a, a dielectric film 30a or 50a, and
storage electrode 31a or 51a, and one impurity diffusion layer 33 or 53 of the transfer transistor T1 or T2 and the storage electrode 31a or 51a are electrically connected by a conductive layer 36 or 56. The first manufacturing method includes a step of selectively forming a buried layer 22 of an opposite conductivity type between a semiconductor substrate 21 of one conductivity type and a semiconductor layer 23 of one conductivity type, and the semiconductor layer of one conductivity type. a step of selectively oxidizing 23 to form a field insulating film 24;
Selectively trenching the semiconductor layer 23 of one conductivity type to form a groove 25 that reaches the buried layer 22 of the opposite conductivity type, and then forming a first insulating film on the inner wall of the groove 25. and a step of implanting impurity ions into the semiconductor layer 23 of one conductivity type to form a buried layer 28 of −i conductivity type. y) forming a layer 42 of an opposite conductivity type between the semiconductor substrate 41 and the first semiconductor layer 43 of one conductivity type; a step of implanting impurity ions into the entire surface to form a buried layer 44 of one conductivity type; and a step of forming a second semiconductor layer 45 of one conductivity type over the entire surface of the buried layer 44 of one conductivity type. The above object is achieved.

[Function] According to the semiconductor memory device of the present invention, the active regions such as the source and drain of the transfer transistor formed in the semiconductor layer of one conductivity type, the semiconductor substrate of one conductivity type, and the semiconductor layer of the one conductivity type. A pressing layer of one conductivity type is provided between the pressing layer of the opposite conductivity type and a pressing layer of an opposite conductivity type that supplies a DC voltage to a counter electrode of a storage capacitor selectively provided therebetween.

This makes it possible to eliminate the generation of parasitic MOS transistors due to the drain (impurity diffusion layer) of the transfer transistor and the buried layer of opposite conductivity type that supplies a DC potential to the opposing electrode of the storage capacitor.

Further, according to the manufacturing method of the present invention, a buried layer of an opposite conductivity type is formed between a semiconductor substrate of a −i conductivity type and a semiconductor layer of one conductivity type, and then a buried layer of one conductivity type is formed. .

This makes it possible to form the active region of the transfer transistor in a region in which a buried layer of one conductivity type is interposed between a buried layer of opposite conduction type that supplies a DC potential to the opposite electrode of the storage capacitor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 to 4 are explanatory diagrams of a semiconductor memory device and its manufacturing method according to an embodiment of the present invention, and FIG. 1 shows a structural diagram of a MO3DRAM cell according to a first embodiment of the present invention. .

FIG. 3(a) is a cross-sectional view of the MO3DRAM cell, and FIG. 2(b) is a plan view thereof. Note that FIG. 11A shows a cross-sectional view taken along the line AA' in FIG. In the figure, 21 is a p-type Si substrate, and 22 is an n1 buried layer.

Note that the n+ buried layer 22 is a conductive layer to which a DC potential is applied from the outside.

23 is a p-type epitaxial layer, 24 is a field oxide film for isolating and insulating elements, and 25 is a trench in which a storage capacitor C1 is provided.

Reference numeral 26 denotes an insulating film such as a 5in2 film that defines the region of the storage capacitor NC9. Reference numeral 28 denotes a p-buried layer formed by implanting B-ion ions into the p-type eviaxial layer 23 with high acceleration and high energy.

Furthermore, since the p' buried layer 28 is provided between the drain 33 of the transfer transistor T1 and the n' buried layer 22 that supplies a DC potential to the counter electrode 29a of the storage capacitor CI, the parasitic MO3 I-transistor can eliminate the occurrence of

Note that 29a is a counter electrode, 30a is a dielectric film, and 31a is a storage electrode, and the electrodes 29a, 31a and the dielectric film 30
a constitutes a storage capacity C, (+- wrench capacitor).

32.33.34 is poly-Si doped with impurity ions
This is an impurity diffusion layer formed of a film, and is the source 32 and drain 33 of the transfer transistor T.

WL is the gate electrode of the transfer transistor T1, and MO
This is a word line in a 3DRAM cell.

35 is a SiO□ film that insulates the word line WL.

These constitute the transfer transistor T1.

Note that 36 is a conductive layer that electrically connects the drain 33 of the transfer transistor T1 and the storage capacitor C5;
is a PSG film that insulates the conductive layer 37.

BL is a bit line formed of a poly-Si film doped with impurity ions, a polycide film, AN cotton, or the like.

These constitute a MO3DRAM cell.

In this way, active regions such as the source 32 and drain 33 of the transfer transistor T formed in the p-type epitaxial layer 23 and between the p-type Si substrate 21 and the P-type epitaxial layer 23 are selectively provided. A P' buried layer 28 is provided between the N' buried layers 22 that supply a DC potential to the counter electrode 29a of the storage capacitor C0.

As a result, the drain 33 (n
It is possible to eliminate the generation of parasitic MO3) transistors as in the prior art due to the impurity diffusion layer) and the buried layer 22 that supplies a DC potential to the counter electrode 29a of the storage capacitor C1.

FIG. 2 is a structural diagram of a MO3 DRAM cell according to a second embodiment of the present invention, and although there are differences in the formation process compared to the first embodiment, the structure is completely the same.

Therefore, to briefly explain the structure, T2 is the source 52
, a drain 53, and a gate electrode WL2;
Counter electrode 49a, dielectric film 50a, storage electrode 51a
This is a storage capacitor (trench capacitor) composed of

Note that 44 is a p-buried layer provided between the p-type epitaxial layer 45 and 43, and in comparison with the first embodiment, the depth of embedding must be controlled more reliably in the second embodiment. Can be done. Also, 56 is transfer 1 to transistor T2
A conductive layer 57 electrically connects the storage capacitor C2 and the storage capacitor C2.
The SG film and BL2 are bit lines.

These constitute a MO3DRAM cell.

In this way, since the P buried layer 44 is provided between the p type epitaxial layers 43 and 45 on the P type Si substrate 41, the generation of parasitic MO3+- transistors is eliminated as in the first embodiment. It becomes possible.

FIG. 3 shows an n-channel MO according to the first embodiment of the present invention.
It is a formation process diagram of a 3DRAM cell, and the same figure (a) - (
i) shows the forming process according to the sectional view taken along the line AA' in FIG. 1(b).

In the figure, impurity ions such as As+ ions are first implanted into a region where a storage capacitor (trench capacitor) is to be formed in a p-type Si substrate 21 using a resist film (not shown) as a mask. Thereafter, the oxide film on the P-type Si substrate 11 is removed, and a p-type epitaxial layer 23 is further formed. Note that P-type Si
By heat-treating the substrate 21 and activating it, an n-buried layer 22 is formed. In addition, the n" buried layer 22 becomes a conductive layer that supplies a direct current potential from the outside. The oxide film generated during the heat treatment is removed to expose the surface of the p-type epitaxial layer 23 (FIG. 2(a)). .

Next, the P-type Si substrate 21 is heat-treated by the Locos method, etc.
A field oxide film 24 is formed, and a transfer transistor T1 is formed.
(b)
).

Next, using a resist film (not shown) as a mask, the storage capacitor C1 is
A trench 25 is formed to reach the buried layer 24. Note that the groove portion 25 is formed by anisotropic etching such as RIE method. Further, as the enching gas, CCP410□ or the like is used. After that, a 5in2 film 2 with a film thickness of about 300 demarcates the area of storage capacity C1.
6 is formed by a CVD oxidation method or the like ((C) in the same figure).

Next, the entire surface of the p-type Si substrate 21 is anisotropically etched by RIE or the like to remove the SiO□ film 26 at the bottom of the trench 25 and expose the n+ buried layer 22.

Furthermore, highly accelerated, high-energy B1 ions 27 and the like are implanted into the entire surface of the p-type Si substrate 21 by ion implantation, and then the p-type Si substrate 11 is heat-treated to activate and p°
A buried layer 28 is formed. Note that the buried layer 28 has a function of preventing the generation of parasitic MO3I transistors (FIG. 2(d)).

Incidentally, the forming steps after the step shown in FIG. 2(d) are carried out as in the conventional example. That is, the entire surface of the p-type Si substrate 11 is coated with a film thickness of 100 mm.
A poly-Si film 29 doped with about 0 impurity ions is formed by low pressure CVD or the like. Note that the poly-Si film 29
becomes the counter electrode 29a that constitutes the storage capacitor MC1 ((e) in the same figure).

Next, using a resist film (not shown) as a mask, the poly-Si film 29 is
The poly-Si film 29 is over-etched using the tE method or the like to leave the poly-Si film 29 in the groove 25, and then the p-type Si substrate 1 is
1 is heat-treated to form a SiO□ film or a Si3N4 film 30. Note that the SiO□ film 30 and the like become the dielectric film 30a in the storage capacitor C1. Furthermore, a poly-Si film 31 doped with impurity ions is buried in the trench 25, the poly-Si film 31 grown in the formation region of the transfer transistor T1 is removed, and the upper part of the storage capacitor C1 is flattened (FIG. 3(f)). )
.

Next, the gate electrode WI is formed by patterning the poly-Si film. Furthermore, using the gate electrode WL as a mask, As+ ions are implanted into the epitaxial layer 23 by an ion implantation method or the like, and the n° impurity diffusion layer 32.3 is
3.34 is formed.

Note that the n' impurity diffusion layers 32 and 33 become the source and drain of the transfer transistor T1 ((g) in the same figure).
).

Next, as an insulating film for insulating the gate electrode WL, a 5in2
A film 35 is formed by a CVD oxidation method or the like ((h) in the same figure).
.

Furthermore, the SiO□ film 35 is selectively removed in order to bond the transfer transistor T1 and the storage capacitor C1, and then,
A poly-Si film doped with impurity ions is selectively formed to form a conductive layer 36. Next, a PSG film 37 etc. that insulates the conductive layer 36 is formed, and then a contact pole 38 of the bit line is formed (FIG. 1(i)).

After the step (+) in the figure, a poly-Si film doped with impurity ions, a polycide film, aluminum wiring, etc. are formed as the bit line BL, and MO3 as shown in Fig. 1 (a) is formed.
DRAM cells can be manufactured.

In this way, after the n+ buried layer 22 is selectively formed between the P type Si substrate 21 and the P type epitaxial layer 23, the p+ buried layer 28 is formed. This results in
Supplying a DC potential to the counter electrode 29a of the storage capacitor CI
Active regions such as the source 32 and drain 33 of the transfer transistor T1 can be formed in the p-type epitaxial layer 23 with the p-buried layer 28 interposed in the buried layer 22.

FIG. 4 shows the p channel M according to the embodiment of FIG. 2 of the present invention.
It is a formation process diagram of an O3DRAM cell, and the figure (a) to (
Similarly to the first embodiment, k) shows a forming process according to the cross section taken along the line AA' in FIG. 2(b).

In the figure, first, an n-buried layer 42 and a p-type epitaxial layer I'i 43 are formed on a P-type Si substrate 41 in the same way as in the first embodiment (FIG. 2(a)).

Next, impurity ions such as B+ ions are implanted into the entire surface of the p-type epitaxial layer 43 by an ion implantation method or the like.
+ An impurity diffusion layer (p'' buried layer) 44 is formed (FIG. 4(b)).

Furthermore, a p-type epitaxial layer 45 is formed on the entire surface of the p' impurity diffusion layer 44 (FIG. 4(C)).

Next, the p-type Si substrate 41 is heat-treated by the Locos method or the like to form a field oxide film 46, and a transfer transistor T is formed.
2 and storage capacitor C2 are defined ((d) in the same figure).
.

Next, using a resist film (not shown) as a mask, the storage capacitor C2 is
A trench 47 reaching the n° buried layer 42 is formed by R⊙E method or the like. Thereafter, a SiO□ film 48 is formed in the groove portion 47 by a CVD method or the like to define an area for the storage capacitor C2 (FIG. 8(e)).

Next, the entire surface of the p-type S1 substrate 41 is anisotropically etched by RIE or the like to expose the SiO□ film 48 at the bottom of the groove 47 and the n-buried layer 42 (FIG. 4(f)). .

Note that the steps after the formation shown in FIG. 2(f) are similar to FIGS.
), so we will briefly explain it.

That is, in the same figure (g), the p-type S
The entire surface of the i-substrate 41 is made of poly-Si doped with impurity ions.
A film 49 is formed, and further, in FIG. 4(h), a 5in2 film or a Si, N4 film 50 is formed as a dielectric film 50a, and then a poly-Si film 51 doped with impurities is formed.
The storage electrode 51a is formed by planarization.

Furthermore, in FIG. 5(i), the word line WL of the transfer transistor T2, the source 52. A drain 53 and an impurity diffusion layer 54 are formed, and in FIG. ! ! A 5in2 film 55 is formed around the edge. After that, in FIG. 5K, a conductive layer 56 is formed to connect the storage capacitor C2 and the drain 53 of the transfer transistor T2, a PSG film 57 is formed to insulate the conductive layer 56, and then a bit line contact ball 58 is formed. Form.

Note that by forming the bit line BL2 after the step shown in FIG. 2(k), it is possible to manufacture a MO3 DRAM cell as shown in FIG. 2(b).

In this way, similar to the second embodiment, the P-type Si substrate 4
1 and the p-type epitaxial layer 43, the p-type epitaxial layer 43 is selectively formed.
．． A p+ buried layer 48 is formed between the layers 44 and 44.

As a result, active regions such as the source 52 and the drain 53 of the transfer transistor T2 are formed in the P-type epitaxial layer 45 with the P buried layer 48 interposed in the N° buried layer 42 that supplies a DC potential to the counter electrode 49a of the storage capacitor C2. It becomes possible to form.

Furthermore, compared to the first embodiment, in the second embodiment, the p+ buried layer 4B is not dependent on the implantation control of ion implantation, so that it is possible to perform accurate positioning.

[Effects of the Invention] As described above, according to the present invention, generation of a parasitic MO81-transistor can be prevented.

Therefore, it becomes possible to form a high-performance DRAM cell without leakage current and to reduce the voltage applied to the dielectric film.

This makes it possible to manufacture ultra-fine, highly integrated, and high-performance semiconductor memory devices.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram of a MO3DRAM cell according to a first embodiment of the present invention. FIG. 2 is a structural diagram of a MO3DRAM cell according to a second embodiment of the present invention. FIG. FIG. 4 is a diagram of the formation process of the MO3DRAM cell according to the second embodiment of the present invention. FIG. 5 is an explanatory diagram of the MO3DRAM cell according to the conventional example. FIG. 2 is a diagram illustrating problems of a MO3DRAM cell according to a conventional example. (Explanation of symbols) T, T,, T2...transfer transistor, C, C,, C
,...storage capacitance, 1.21.41...p-type Si substrate (semiconductor substrate of one conductivity type), 2.24.46...field oxide film (field insulating film), 3.33.53 ...Drain (impurity diffusion layer), 4.
32.52... Source (impurity diffusion layer), 5a, 5b
, 26, 35, 48.55-3in□ film (insulating film), 6.31a, 51a...Storage electrode, 7.30a, 50a...Dielectric film, 8.29a, 49a...Counter electrode , 9.36.56... Conductive layer (Ho'J Si ll), 10.37.57... PSG film (insulating film), 11
．． 22.42...n-buried layer (buried layer of opposite conductivity type), 23.43.45...p-type epitaxial layer (semiconductor layer of one conductivity type), 25.47...groove (1 - wrench), 27...B4
ion (impurity ion), 28.44...p buried layer (buried layer of one conductivity type), 29.31.49.51... poly-Si film (conductive film),
30.50...5in2 film or St3Nm film, 34.
54...n゛ impurity diffusion layer, 38.58... Bit line contact ball, WL, W
L, , WL2...word line (gate electrode), BL, B
L,, BL2...Bisito line, To...parasitic MO3I
Ranjista. Fall Maishi Lω
Is it the history of C'J-tsu A Ku?

Claims (3)

[Claims] (1) A pair of impurity diffusion layer (32, 33 or 52, 53) regions and a gate electrode (WL_1 or WL_
2) A transfer transistor (T_1 or T_2) having
and a storage capacitor (C_1 or C_2), the pair of impurity diffusion layers (3
2, 33 or 52, 53) is a semiconductor substrate of one conductivity type (
21 or 41) on one conductivity type buried layer (28 or 48)
) is formed in a semiconductor layer (23 or 45) of one conductivity type, and the storage capacitor (C_1 or C_2) is formed in a semiconductor layer (23 or 43, 45) of one conductivity type and a buried layer of one conductivity type. (
28 or 48) and whose bottom is a buried layer (22) of an opposite conductivity type selectively provided in a semiconductor substrate (21 or 41) of one conductivity type; A counter electrode (29a or 49a) and a dielectric film (30a
or 50a) and a storage electrode (31a or 51a), one impurity diffusion layer (33 or 53) of the transfer transistor (T_1 or T_2) and a storage electrode (31a or 51a).
1a) are electrically connected to each other by a conductor layer (36 or 56). (2) A buried layer of the opposite conductivity type (
22), selectively oxidizing the semiconductor layer (23) of one conductivity type to form a field insulating film (24), and selectively trenching the semiconductor layer (23) of one conductivity type. forming a trench (25) reaching the buried layer (22) of the opposite conductivity type, and then forming a first insulating film on the inner wall of the trench (25); A method for manufacturing a semiconductor memory device, comprising the step of implanting impurity ions into a semiconductor layer (23) to form a buried layer (28) of one conductivity type. (3) selectively forming a buried layer (42) of an opposite conductivity type between the semiconductor substrate (41) of one conductivity type and the first semiconductor layer (43) of one conductivity type; a step of implanting impurity ions into the entire surface of the semiconductor layer (43) of one conductivity type to form a buried layer (44) of one conductivity type; A method for manufacturing a semiconductor memory device, comprising the step of forming a semiconductor layer (45) of one conductivity type.