JPH11284137A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the substrate potential of a memory cell array part independently without using triple well structure, and reduce the off leakage current of an access transistor, in a DRAM cell. SOLUTION: A memory cell array part A and a peripheral circuit part B are separated and isolated by a buried oxide film layer 7 within a trench 4, using an SOI substrate which has a p-type silicon single crystalline layer on a buried polysilicon layer 2b caught above and below between oxide film layers 2a and 2b. The separation between the elements at the memory cell array part A is performed by the field shield element isolating structure by a field electrode thereby avoiding the substrate floating effect peculiar to SOI structure. The buried polysilicon layer 2b is put at the same substrate bias potential as the p-type silicon single crystalline layer on it, and the access transistor is made double gate structure so as to reduce the off leak current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynami
(c) Random Access Memory) and a method of manufacturing the same.

[0002]

2. Description of the Related Art For example, in a conventional DRAM of 64M or later, the peripheral circuit speed is improved, and an electrostatic discharge (ESD:
For the purpose of improving reliability against o-Static Discharge), latch-up and the like, a triple well method is employed.

[0003]

However, in order to form multiple wells in a substrate as in the triple well method, an ion implantation step is inevitably increased, and a mask step for the same is required. Was also complicated.

[0004] Furthermore, as a result of ion implantation with impurities of different conductivity type being superimposed on the substrate, there has been a problem that the substrate concentration is increased and the substrate bias effect is deteriorated and the retention characteristics are deteriorated.

Accordingly, an object of the present invention is to provide a low-voltage, high-speed peripheral circuit and a stable substrate potential in a memory cell array section, even if the triple well method is not employed. Accordingly, it is an object of the present invention to provide a semiconductor memory device and a method of manufacturing the same, which can be achieved respectively, and as a result, deterioration of the substrate bias effect and deterioration of the holding characteristics can be avoided.

[0006]

A semiconductor memory device according to the present invention for solving the above-mentioned problems includes a first insulating layer provided on a semiconductor substrate, and a polycrystal provided on the first insulating layer. A semiconductor layer and a second layer provided on the polycrystalline semiconductor layer.
And a single crystal semiconductor layer provided on the second insulating layer, wherein each element of a memory cell array region and a peripheral circuit region is formed in the single crystal semiconductor layer, and in the memory cell array region The elements are separated by the field shield element separation method, and the elements are separated by the insulator separation method in the peripheral circuit region.

In one embodiment of the present invention, a third insulating layer is provided in a trench formed so as to surround the memory cell array region and penetrate the single crystal semiconductor layer. The third insulating layer electrically isolates the single crystal semiconductor layer in the memory cell array region from the single crystal semiconductor layer in the peripheral circuit region.

In one aspect of the present invention, isolation between elements in the peripheral circuit region is performed by a LOCOS method.

In one embodiment of the present invention, at least the polycrystalline semiconductor layer in the memory cell array region is fixed at substantially the same potential as the single crystal semiconductor layer in the memory cell array region.

In one embodiment of the present invention, at least the polycrystalline semiconductor layer in the memory cell array region and the single crystal semiconductor layer in the memory cell array region are both fixed at a back bias potential.

In one embodiment of the present invention, a one-transistor-one-capacitor type memory cell is formed in the memory cell array region.

In one embodiment of the present invention, a capacitor structure of each memory cell is formed in a trench provided in the substrate in the memory cell array region.

In one embodiment of the present invention, the capacitor structure of each of the memory cells includes a cell plate provided on an inner surface of the trench in the memory cell array region via an insulating film, and a capacitor provided on the cell plate. It comprises an insulating film and a storage node provided on the capacitor insulating film.

In one embodiment of the present invention, a field shield electrode of a field shield element isolation structure in the memory cell array region is formed continuously with the cell plate.

In one aspect of the present invention, the capacitor structure of each of the memory cells is configured in a stack type.

In one embodiment of the present invention, the cell plate having the capacitor structure is electrically connected to a field shield electrode having a field shield element isolation structure in the memory cell array region.

Further, according to the method of manufacturing a semiconductor memory device of the present invention, a first single crystal semiconductor substrate having a polycrystalline semiconductor layer formed on a main surface with a first insulating film interposed therebetween, After bonding the second single-crystal semiconductor substrate on which the insulating film is formed to each other with the main surfaces thereof facing each other, processing the thickness of the second single-crystal semiconductor substrate to obtain the first single-crystal semiconductor substrate Forming a single crystal semiconductor layer over the semiconductor substrate with the first insulating film, the polycrystalline semiconductor layer, and the second insulating film interposed therebetween; and forming a single crystal semiconductor layer in a portion to be a peripheral circuit region of the single crystal semiconductor layer. Forming a device isolation structure, and at least the second semiconductor layer between the portion to be the peripheral circuit region and the portion to be the memory cell array region of the single crystal semiconductor layer so as to surround the portion to be the memory cell array region. Of the depth that reaches the insulating film To form a 1 of the trench,
Forming a second trench for forming a memory cell capacitor at a predetermined position of the single crystal semiconductor layer in a portion to be the memory cell array region, and filling the entire surface so as to fill the first and second trenches Forming a third insulating film, and removing the third insulating film outside the first and second trenches, and then removing the third insulating film in the second trench. Forming a fourth insulating film over the entire surface of the memory cell array region including the inner surface of the second trench; and forming a first conductive film on the fourth insulating film Patterning the first conductive film to leave the first conductive film in a region serving as an element isolation region in the memory cell array region and a region including the second trench continuous with the region. First Forming a fifth insulating film on the conductive film; and forming a second conductive film on the fifth insulating film, and then forming the second conductive film on a storage node pattern of the memory capacitor. Processing, forming MOSFETs in predetermined portions of the portion to be the peripheral circuit region and the portion to be the memory cell array region, and forming the MOSFET in the portion to be the memory cell array region.
Electrically connecting one of the diffusion layers of the FET and the second conductive film.

In one embodiment of the present invention, LOCOS is used as the element isolation structure in a portion to be the peripheral circuit region.
An oxide film is formed, and the LOCOS oxide film is polished and processed to be flush with the main surface of the single crystal semiconductor layer.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising: a first single-crystal semiconductor substrate having a polycrystalline semiconductor layer formed on a main surface with a first insulating film interposed therebetween; After bonding a second single crystal semiconductor substrate having a second insulating film formed on a surface thereof to each other with the main surfaces thereof facing each other, processing the thickness of the second single crystal semiconductor substrate to obtain the second single crystal semiconductor substrate. Forming a single crystal semiconductor layer on the single crystal semiconductor substrate via the first insulating film, the polycrystalline semiconductor layer, and the second insulating film; and a peripheral circuit region of the single crystal semiconductor layer. Forming an element isolation structure in a portion to be
A trench having a depth reaching at least the second insulating film between the portion to be the peripheral circuit region and the portion to be the memory cell array region of the single crystal semiconductor layer so as to surround the portion to be the memory cell array region; Forming a third insulating film so as to fill the trench, forming a field shield element isolation structure in a portion to be the peripheral circuit region, and forming a portion to be the peripheral circuit region A step of forming MOSFETs at predetermined portions of a portion to be the memory cell array region, and a memory having a storage node electrically connected to one diffusion layer of the MOSFET at the portion of the memory cell array region Forming a capacitor.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described according to preferred embodiments.

FIG. 1 shows a first embodiment of the present invention applied to a reverse wrench capacitor type DRAM.
2 is a schematic sectional view of the embodiment, FIG. 2 is a plan view of a memory cell array portion, and FIG. 3 is a schematic diagram of the entire DRAM. FIG. 1 corresponds to a cross section taken along line II of FIG.

As shown in FIG. 1, the DRA of this embodiment
M has a thickness of, for example, 0.2 to 0.2 μm on a p-type single-crystal silicon semiconductor substrate 1 via a buried polysilicon layer 2 b sandwiched between silicon oxide film layers 2 a and 2 c on the upper and lower sides.
About 0.3 μm and a substrate surface concentration of 1 × 10 ¹⁶ / c
A kind of SOI (Silicon On Insulator or Semic) provided with ap type single crystal silicon semiconductor layer ^{3 of} about m ³ or more.
(Onductor On Insulator) structure.

As shown in FIG. 3, the DRAM includes a memory cell array section A in which a large number of memory cells are formed, and a peripheral circuit section B including a sense amplifier and the like. It is separated by a trench 4 of about 5 to 10 μm. In FIG. 3, reference numeral 5 denotes a trench in which a memory capacitor is formed in the memory cell array section A, and 100 denotes various MOS transistors provided in the peripheral circuit section B.

As shown in FIG. 1, the memory cell array section A
The trench 4 that separates the semiconductor device from the peripheral circuit portion B is formed to a depth penetrating the lower oxide film layer 2a, and the inside thereof is filled with a silicon oxide film layer 6. The trench 4 does not necessarily need to be formed to a greater depth as long as it is formed to a depth reaching the upper oxide film layer 2c.

By the oxide film layer 6 and the oxide film layer 2c in the trench 4, the silicon semiconductor layer 3 which is the substrate part of the memory cell array part A and the silicon semiconductor layer 3 which is the substrate part of the peripheral circuit part B are mutually connected. It is electrically insulated and exhibits the same effect as the conventional triple well structure.

The buried polysilicon layer 2b of the memory cell array portion A and the buried polysilicon layer 2b of the peripheral circuit portion B are electrically insulated from each other by the oxide film layer 6 and the oxide film layer 2a in the trench 4. ing.

On the other hand, in the example shown, the trench 5 in which the memory capacitor is formed in the memory cell array portion A is also formed to a depth penetrating the oxide film layer 2a, but this trench 5 is required as a memory capacitor. As long as the capacity is obtained, the depth is not particularly limited.

In trench 5, an n-type polysilicon film 8, which is a cell plate of a memory capacitor, is formed on the inner surface thereof via a silicon oxide film 7. On this n-type polysilicon film 8, For example, an n-type polysilicon film 10, which is a storage node of a memory capacitor, is stacked via a capacitor dielectric film 9 made of an ONO film.

At this time, in this embodiment, as shown in FIG.
An n-type polysilicon film 8 serving as a cell plate of the above-mentioned memory capacitor is formed to extend to an element isolation region,
In the element isolation region, the field shield electrode 8
It is configured to function as a (see FIG. 2).

In the memory cell array section A, an access transistor of each memory cell is formed by an n-type polysilicon gate (word line) 11 and a pair of n ⁺ diffusion layers 12 and 13.

In the example shown, two memory cells sharing one n ⁺ diffusion layer 13 of the access transistor are formed in one element region.

[0032] Each n ⁺ diffusion layers 12 and 13 of the access transistor, n-type polysilicon film 14 is contacted people each, one of the n ⁺ diffusion that is not shared with other memory cells as a diffusion layer lead electrode The n-type polysilicon film 14 in contact with the layer 12 is connected to the storage node 10 of each memory capacitor.
a (see FIG. 2). Also, the other n ⁺ diffusion layer 1 shared by the two memory cells
The n-type polysilicon film 14 in contact with 3 is a metal wiring as a bit line via a tungsten (W) plug 17 in a contact hole (bit contact) 16 (see FIG. 2) provided in the interlayer insulating film 15. 18 is electrically connected.

As shown in FIG. 1, _Vcc / _Vcc / is applied to the polysilicon films 8 and 8a, which are the cell plate of each memory capacitor and the field shield electrode, via the tungsten (W) plug 42. 2
(V _cc : power supply potential).

In the substrate portion of the memory cell array portion A,
P-type silicon semiconductor layer 3 ⁺The diffusion layer 20
Through the tact tungsten (W) plug 21, gold
Substrate bias potential V_bbIs given
You.

Further, the substrate bias potential _Vbb is also applied to the buried polysilicon layer 2b of the memory cell array section A through a contact (not shown).

On the other hand, as shown in FIG. 1, for example, an n-type polysilicon gate 23 and a pair of n-type
^- a diffusion layer 24 and a pair of n ⁺ diffusion layer 25. LD
An n-channel MOS transistor having a D (Lightly Doped Drain) structure, a p-channel MOS transistor and the like are formed in an n-well provided in a p-type silicon semiconductor layer 3 (not shown).

Reference numeral 27 denotes the n-channel MOS transistor described above.
N, the source / drain of the transistor ⁺Tan for the diffusion layer 25
Metal contact through Gusten (W) plug 26
Wiring.

In the example shown in the figure, the LOCOS oxide film 28 is used to separate the elements in the peripheral circuit section B.

The operation of the first embodiment configured as described above will be described.

The substrate bias potential V _bb (for example, -0.5 V _cc ) is applied to the p-type silicon semiconductor layer 3 of the memory cell array portion A, which is insulated and separated by the oxide film layers 2c, 6, and the oxide film layers 2a, 6 To the buried polysilicon layer 2b of the memory cell array portion A, which is insulated and separated by the above, by applying substantially the same substrate bias potential V _bb (for example, -0.5 V _cc ) as the p-type silicon semiconductor layer 3 thereon. The buried polysilicon layer 2b has the function of the back gate electrode of the access transistor in each memory cell. On the other hand, as described above, the voltage at which a parasitic channel occurs on the substrate surface in the field region (sometimes referred to as “field threshold voltage” in this specification) has a substrate surface concentration of 1 × 10 ^16. / Cm ³ or more, the voltage is about 2.0 V or more. Therefore, V _cc / 2 is set to 1.00 V, for example, on the field shield electrode 8a.
By fixing the potential of the substrate surface by applying about 1.25 V or 1.65 V, it is possible to prevent the conductivity type of the substrate surface from being inverted in the field region. That is, the polysilicon film 8 can be used not only as a cell plate of a memory capacitor but also as a field shield electrode 8a.

Also, by using such a field shield element separation method, the LOCOS method or the STI (Sh
Unlike the case where an insulator isolation method such as an allow Trench Isoration (shallow trench isolation) method is used, the potential of the p-type silicon semiconductor layer 3 in the memory cell array portion A is fixed by local electric field control, and a substrate unique to the SOI structure is used. Floating effects can be avoided.

On the other hand, in the peripheral circuit section B, by using the above-described insulator isolation method for element isolation, for example,
Isolation between elements in a CMOS structure can be easily performed.

As described above, the p-type silicon semiconductor layer 3 of the memory cell array portion A is formed by the oxide film layers 2c and 6, and the buried polysilicon layer 2b of the memory cell array portion A is formed by the oxide film layers 2a and 6. By electrically insulating and separating from the substrate portion of the peripheral circuit portion B so that the substrate can be independently biased, the same effect as the conventional triple well structure can be obtained.

Next, a method for manufacturing the structure of the first embodiment will be described with reference to FIGS.

The manufacturing method shown in FIGS. 4 to 7 is slightly different from the structure shown in FIG. 1 in which the element isolation in the peripheral circuit portion is performed by the STI method in the LOCOS method. .

First, as shown in FIG.
The single-crystal silicon semiconductor substrates 1 and 3 are prepared, and the main surface of one of the substrates 3 is coated with a thickness of, for example, 10 mm by thermal oxidation.
Forming a silicon oxide film 2c of about 20 nm to about 20 nm;
A depth of about 0.2 to 0.3 μm from the main surface (E in the figure)
Indicated by ) With hydrogen (H), for example, 2 × 10 ¹⁶ to 2
Ion implantation is performed at a dose of about × 10 ¹⁷ / cm ² . After forming a thermal oxide film 2a having a thickness of about 20 to 30 nm on the main surface of the other substrate 1, an n-type polysilicon layer 2b having a thickness of about 200 nm is formed thereon by CVD. Keep it.

Next, the main surfaces of the two substrates 1 and 3 are respectively subjected to, for example, RCA cleaning, and then bonded to each other with their main surfaces facing each other.

Thereafter, for example, when a heat treatment at about 400 to 600 ° C. is performed, the substrate 3 is peeled off at a portion E into which hydrogen (H) has been implanted, and as shown in FIG. A buried polysilicon layer 2b sandwiched between upper and lower silicon oxide film layers 2a and 2c on a single crystal silicon semiconductor substrate 1.
Through this, an SOI substrate on which the p-type single-crystal silicon semiconductor layer 3 having a thickness of about 0.2 to 0.3 μm is obtained (generally referred to as a smart-cut method).

Next, as shown in the figure, the silicon oxide film 28 is formed only in the element isolation (field) region of the region to be the peripheral circuit portion B of the silicon semiconductor layer 3 by the LOCOS method.
It is formed to a depth reaching the silicon oxide film layer 2c but not penetrating the buried polysilicon layer 2b, for example, a depth of about 0.3 μm.

Next, as shown in FIG. 4C, a trench 4 for separating the memory cell array portion A from the peripheral circuit portion B by photolithography and anisotropic dry etching, and a memory cell array portion A , Trenches 5 for forming memory capacitors are formed, for example, to a depth of about 5 to 10 μm, respectively.

Next, thermal oxidation is performed on the entire surface including the inner surfaces of the trenches 4 and 5 at about 1000 ° C., and then a silicon oxide film 6 is deposited by the CVD method. Embed with Then, CMP (Chem
The silicon oxide film 6 outside the trenches 4 and 5 is removed by an ical mechanical polishing (chemical mechanical polishing) method.
At this time, the LOC protruding from the main surface of the silicon semiconductor layer 3
The portion of the OS oxide film 28 is also polished at the same time, as shown in FIG.
The upper surface of LOCOS oxide film 28 is substantially flush with the main surface of silicon semiconductor layer 3.

Next, as shown in FIG. 5A, the portions other than the memory cell array portion A are covered with a photoresist 31, and only the silicon oxide film 6 in the trench 5 of the memory cell array portion A is once removed.

Next, as shown in FIG. 5B, after removing the photoresist 31, thermal oxidation is performed to form a relatively thin silicon oxide film 7 on the entire surface including the inner surface of the trench 5, and further, On the silicon oxide film 7, a thickness of 100 nm
N-type polysilicon film 8 having a thickness of about 5
Capacitor dielectric film 9 made of ONO film of about 6 nm
Are sequentially formed, and these capacitor dielectric films 9 and 9 are formed by photolithography and anisotropic dry etching.
The n-type polysilicon film 8 and the silicon oxide film 7 are respectively patterned, and are left only in the trench 5, its peripheral region and the element isolation region.

Next, as shown in FIG. 5C, an n-type polysilicon film 10 having a thickness of about 100 to 150 nm is formed on the entire surface so as to fill the trench 5 by the CVD method. The n-type polysilicon film 10 is patterned by photolithography and anisotropic dry etching to be processed into the shape of the storage node of each memory capacitor.

Thereafter, the peripheral circuit portion B is formed by a thermal oxidation method.
And the surface of each element formation region of the memory cell array portion A,
In addition, a silicon oxide film 32 to be a gate oxide film later is formed on the surface of the polysilicon film 10.

The portion of the capacitor dielectric film 9 exposed from the polysilicon film 10 due to the thermal oxidation at this time is:
The whole turns into an oxide film.

Next, as shown in FIG.
After forming a mold polysilicon film and a cap silicon oxide film 33 thereon, these are patterned by photolithography and anisotropic dry etching. In the memory cell array portion A, polysilicon serving as a word line is formed. In the gate 11, the cap silicon oxide film 33 thereon, and the peripheral circuit section B, the polysilicon gate 23 of various MOS transistors and the cap silicon oxide film 33 thereon are formed, respectively.

Next, a portion of the memory cell array portion A which will be a substrate contact portion later is covered with a photoresist 34,
Further, in a state where the side surfaces of the polysilicon gates 11 and 23 are covered with the thermal oxide film 35, an n-type impurity 36 such as phosphorus (P) is applied to the entire surface, for example, at an energy of about 20 to 40 KeV.
Ion implantation is performed under the conditions of a dose of about 1 × 10 ^{13 to} 3 × 10 ¹³ / cm ² , and the n ⁻ diffusion layer 12a and the p-type silicon semiconductor layer 3 on both sides of the polysilicon gates 11 and 23 are self-aligned. 13a and 24 are formed respectively.

Next, as shown in FIG.
The silicon oxide film formed by the VD method is anisotropically dry-etched to form side surfaces of the polysilicon gates 11 and 23,
And sidewall silicon oxide films 3 on the side surfaces of the n-type polysilicon film 10 as storage nodes of the memory capacitors.
7 is formed.

At this time, due to the anisotropic dry etching, the surface of the p-type silicon semiconductor layer 3 other than the portion covered with the sidewall silicon oxide film 37 and the surface of the n-type polysilicon film 10 which is the storage node of the memory capacitor (FIG. During,
The relatively thin silicon oxide films (portions indicated by C) are removed respectively, and those portions are exposed. Therefore, in order to cover portions other than the n ⁻ diffusion layers 12 a and 13 a of the memory cell array portion A and portions other than the surface of the n-type polysilicon film 10, a silicon oxide film is formed on a portion other than the element region of the memory cell array portion A by the CVD method. 38 are formed.

Thereafter, a non-doped polysilicon film 14 is formed on the entire surface, and the polysilicon film 14 is patterned by photolithography and anisotropic dry etching to form the n ⁻ diffusion layer 12 of the memory cell array portion A.
The electrodes are processed into the shapes of the extraction electrodes a and 13a. At this time, the polysilicon film 14 serving as an extraction electrode of the n ⁻ diffusion layer 12a is connected to the n-type polysilicon film 10 via the exposed portion of the surface of the n-type polysilicon film 10 which is the storage node of the memory capacitor. Contact is made (the portion indicated by C in the figure).

Next, as shown in FIG. 7A, a portion of the memory cell array portion A which will be a substrate contact portion later is covered with a photoresist 40, and the entire surface of the memory cell array portion A is made of n such as arsenic (As).
Type impurity 41, for example, energy of about 60 KeV,
Ion implantation is performed under the conditions of a dose of about 5 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² . As a result, the polysilicon film 14 becomes n
The n ⁺ diffusion layers 12b and 13b are self-aligned with the side wall silicon oxide film 37 provided on the polysilicon gate 11 and the like of the memory cell array portion A by diffusion of the n-type impurity from the polysilicon film 14. Are formed, and the polysilicon gate 23 of the peripheral circuit portion B is formed.
N in a self-alignment manner with the side wall silicon oxide film 37
^{+ A} diffusion layer 25 is formed.

[0063] At this time, as shown, each n ⁺ diffusion layer 12
The bottom surfaces of b, 13b and 25 are respectively in contact with oxide film layer 2c.

Next, as shown in FIG. 7B, after removing the photoresist 40, ap ⁺ diffusion layer 20 is formed at a portion where the substrate contact is made, and thereafter, for example, a BPSG film is formed on the entire surface. Is formed by a normal pressure CVD method. Then, contact holes are opened at predetermined positions of the interlayer insulating film 15 and these contact holes are formed by tungsten (W) plugs 17, 21, 26, 4
Embed each with 2.

Thereafter, although not shown in detail, metal wirings 18, 19, 22, and 27 are formed on the interlayer insulating film 15, respectively, and a structure substantially similar to that of FIG. 1 is formed.

In the first embodiment described above, as shown in FIG. 1, the p-type silicon semiconductor layer 3 of the memory cell array section A is formed on the substrate of the peripheral circuit section B by the buried oxide film layers 2c and 6. The p-type silicon semiconductor layer 3 of the memory cell array section A can be independently substrate-biased because it is electrically insulated and separated from the section. Therefore, the same effect as the conventional triple well structure can be obtained without employing the triple well structure.

Further, a buried polysilicon layer 2b is provided below the p-type silicon semiconductor layer 3 in the memory cell array section A via an oxide film layer 2c, and the potential of the buried polysilicon layer 2b is set to a substrate bias potential. By functioning as a back gate electrode of the access transistor of each transistor, the off-leak current of the access transistor is reduced, and its cut-off characteristics are improved.
As a result, the refresh characteristics of the DRAM are improved.

Further, the device isolation in the memory cell array section A is performed by the field shield device isolation method,
Unlike the case where the insulator isolation method such as the LOCOS method or the STI method is used, the potential of the p-type silicon semiconductor layer 3 of the memory cell array portion A is fixed by local electric field control,
The substrate floating effect peculiar to the OI structure can be avoided.

Further, the memory capacitor is formed as a reverse wrench capacitor, and the cell plate of the memory capacitor is formed integrally with the field shield electrode, so that the contact structure and the manufacturing process thereof can be simplified. .

On the other hand, in the peripheral circuit section B, the above-described LOC
By using an insulator isolation method such as an OS method or an STI method for element isolation, for example, element isolation in a CMOS structure can be easily performed.

[Second Embodiment] Next, a second embodiment of the present invention will be described.
An embodiment will be described.

FIG. 8 shows the DR according to the second embodiment.
FIG. 9 is a schematic cross-sectional view of the AM, FIG. 9 is a plan layout view of the memory cell array portion, and FIG. 10 is an overall schematic configuration diagram of the DRAM. FIG. 8 corresponds to a cross section taken along line VIII-VIII in FIG.

In the second embodiment, the memory capacitors are configured in a stack type, and the field shield element isolation structure of the memory cell array is formed independently of the memory capacitors. Although not specifically illustrated, isolation between elements in the peripheral circuit portion B is performed by the STI method using a trench similar to the trench 4 for separating the memory cell array portion A and the peripheral circuit portion B. . Other configurations are substantially the same as those of the above-described first embodiment. Therefore, portions corresponding to those in the above-described first embodiment are denoted by the same reference numerals as those in the above-described first embodiment.

As shown in FIG. 8, in the second embodiment, the silicon oxide film layers 2 are formed on the p-type single-crystal silicon semiconductor substrate 1 in the same manner as in the first embodiment.
through a buried polysilicon layer 2b sandwiched between a and 2c, a DRA is formed on a kind of SOI substrate provided with a p-type single crystal silicon semiconductor layer 3 having a thickness of about 0.2 to 0.3 μm.
M is formed.

As shown, in the second embodiment, the trench 4 separating the memory cell array portion A and the peripheral circuit portion B reaches the oxide film layer 2c but has a depth not penetrating the oxide film layer 2c. It is formed in a so-called STI structure. The oxide film layer 6 and the oxide film layer 2c in the trench 4 form the silicon semiconductor layer 3 which is the substrate part of the memory cell array part A and the silicon semiconductor layer 3a which is the substrate part of the peripheral circuit part B (shown in FIG. Are electrically insulated from each other, and the same effect as in the conventional triple well structure is obtained.

In the second embodiment, isolation between elements in the memory cell array section A is achieved by the field shield electrode 50 made of an n-type polysilicon film. On the other hand, although not shown, the peripheral circuit unit B
Is performed by an STI element isolation method using a trench similar to the trench 4.

The access transistor of each memory cell is
n ^- diffusion layers 12a and 13a and n ⁺ diffusion layers 12a and 13a
The storage node 10 of the memory capacitor is connected to one of the n ⁺ diffusion layers 12a.

The memory capacitor is a stack type in which a cell plate 8 made of an n-type polysilicon film is stacked on a storage node 10 made of an n-type polysilicon film via a capacitor dielectric film 9 made of an ONO film. Is configured. Then, the cell plate 8 of the memory capacitor is in contact with the field shield electrode 50 as shown.

An extraction electrode 14 made of an n-type polysilicon film is provided on the other n ⁺ diffusion layer 13a of the access transistor, and a bit line 18 made of a polycide wiring is connected through the extraction electrode 14. .

The p ⁺ diffusion layer 20 for substrate contact
Is also provided with an extraction electrode 14 made of an n-type polysilicon film, and the extraction electrode 14 and tungsten (W)
The substrate bias potential V _bb is applied from the metal wiring 22 via the plug 21.

The buried polysilicon layer 2b also has a substrate bias potential V due to a contact structure (not shown).
Fixed to _bb .

In the second embodiment, in the illustrated example, the substrate portion of the peripheral circuit portion B is formed as an n-well 3a, in which an n-type polysilicon gate 23 and a pair of p-type
^- p-channel MOS transistor of LDD structure consisting of the diffusion layer 51 and the p ⁺ diffusion layer 52 is formed.

In FIG. 8, reference numeral 26 denotes tungsten (W).
The plugs 27 and 53 are metal wirings. In FIG. 9, reference numeral 10a denotes a storage contact, and 16 denotes a bit contact.

Next, a method of manufacturing the structure of the second embodiment will be described with reference to FIGS.

First, as shown in FIG. 11A, the upper and lower portions are sandwiched between silicon oxide film layers 2a and 2c on a p-type single crystal silicon semiconductor substrate 1 as in the first embodiment. An SOI substrate on which a p-type single-crystal silicon semiconductor layer 3 having a thickness of about 0.2 to 0.3 μm is formed via a buried polysilicon layer 2b. In the second embodiment, the region between the memory cell array portion A and the peripheral circuit portion B of the silicon semiconductor layer 3 reaches the silicon oxide film layer 2 by photolithography and anisotropic dry etching. Is the silicon oxide film layer 2
Is formed to a depth that does not penetrate through the trenches, for example, a depth of about 0.5 μm. At this time, a trench for element isolation in the peripheral circuit portion B is also formed at this time.

Next, after thermal oxidation of about 1000 ° C. is performed on the entire surface, a silicon oxide film 6 is deposited by the CVD method to fill the trench 4. Thereafter, the silicon oxide film 6 outside the trench 4 is removed by the CMP method.

Next, as shown in FIG. 11B, after the n-well 3a of the peripheral circuit section B is formed by, for example, a thermal diffusion method or a high-acceleration ion implantation method, the memory cell array section A
Only, a field shield element isolation structure including a field shield electrode 50 made of an n-type polysilicon film is formed.

Thereafter, the silicon semiconductor substrate 3 in the element formation region defined by the field shield element isolation structure is formed.
A silicon oxide film 32 to be a gate oxide film later is formed on the surface by a thermal oxidation method.

Next, as shown in FIG. 11C, an n-type polysilicon film is formed on the entire surface, and a cap silicon oxide film is formed thereon, and then, by photolithography and anisotropic dry etching. By patterning them, in the memory cell array portion, the polysilicon gate 11 serving as a word line and the cap silicon oxide film thereon are formed. In the peripheral circuit portion, the polysilicon gate 23 of various MOS transistors and the cap silicon oxide film thereon are formed. Form each.

Next, a portion of the memory cell array portion, which will be a substrate contact portion later, and a region of the n-well 3a of the peripheral circuit portion B are covered with a photoresist (not shown). The n-type impurity is, for example, energy of about 20 to 40 KeV and a dose of 1 × 10 ^{13 to} 3 × 10
Ion implantation is performed under conditions of about ¹³ / cm ² , and n ⁻ diffusion layers 12 a and 13 a are formed in the p-type silicon semiconductor layer 3 on both sides of the polysilicon gate 11 in a self-aligned manner.

Next, the entire memory cell array portion A and the portion other than the n-well 3a of the peripheral circuit portion B are covered with a photoresist (not shown), and a p-type impurity such as boron (B) is ion-implanted over the entire surface. Then, ap ⁻ diffusion layer 51 is formed in the n well 3 a on both sides of the polysilicon gate 23 in a self-aligned manner.

Next, the silicon oxide film formed on the entire surface by the CVD method is anisotropically dry-etched to form side wall silicon oxide films on the side surfaces of the polysilicon gates 11 and 23, respectively.

Next, the portion of the memory cell array portion A, which will be a substrate contact portion later, and the region of the n-well 3a of the peripheral circuit portion B are covered with a photoresist (not shown). Is implanted, for example, at an energy of about 60 KeV and a dose of 5 × 10 ¹⁵ to 1 × 10 ¹⁶ / c.
ions are implanted in m ² about conditions, the polysilicon gate 1
N ^{+ in a} self-aligned manner with respect to the side wall silicon oxide film provided in FIG ^.
The diffusion layers 12b and 13b are formed.

At this time, the n ⁺ diffusion layers 12b and 13b are formed to a depth at which the bottom surface contacts the oxide film layer 2c.

Next, the element region of the memory cell array portion A is covered with a photoresist (not shown), and a p-type impurity such as boron (B) is ion-implanted over the entire surface, and a substrate contact is formed after the memory cell array portion A. A p ⁺ diffusion layer 20 is formed in a portion serving as a portion, and ap ⁺ diffusion layer 52 is formed in a self-alignment manner with a side wall silicon oxide film provided on a polysilicon gate 23 in an n well 3 a of a peripheral circuit portion B. I do.

Next, as shown in FIG. 12A, after forming an n-type polysilicon film on the entire surface, the n-type polysilicon film is patterned by photolithography and anisotropic dry etching. And forming the storage node 10 of the memory capacitor as shown in FIG.
The respective lead electrodes 14 for the ⁺ diffusion layer 13b and the p ⁺ diffusion layer 20 are formed.

Next, a capacitor dielectric film 9 made of an ONO film is formed on the entire surface, and a contact hole (D in FIG. 2) for the field shield electrode 50 is formed at a predetermined position by photolithography and anisotropic dry etching.
Indicated by ) Is formed.

Next, as shown in FIG. 12B, after forming an n-type polysilicon film on the entire surface, the n-type polysilicon film is patterned by photolithography and anisotropic dry etching. The cell plate 8 of the memory capacitor is formed as shown in FIG. The portion of the capacitor dielectric film 9 not covered by the cell plate 8 is
Is removed.

Next, as shown in FIG. 12C, an interlayer insulating film 15a made of, for example, a BPSG film is formed on the entire surface by normal pressure CVD. Then, the interlayer insulating film 1
A contact hole is formed at a predetermined position of 5a, and a bit line 18 made of a polycide wiring is formed through the contact hole to contact the extraction electrode 14 of the n ⁺ diffusion layer 13b.

Thereafter, although not shown in detail, for example, after an interlayer insulating film made of a BPSG film is further formed on the entire surface, contact holes are formed in predetermined portions of the interlayer insulating film, and the contact holes are formed. Buried with tungsten (W) plugs 21 and 26, respectively. And
Metal wirings 22, 27, and 53 are formed on the interlayer insulating film, respectively, to obtain a structure shown in FIG.

In the second embodiment as well, the first
As in the first embodiment, the p-type silicon semiconductor layer 3 of the memory cell array section A is
Since the p-type silicon semiconductor layer 3 of the memory cell array section A can be independently substrate-biased since it is electrically insulated and separated from the silicon semiconductor layer 3a of the peripheral circuit section B, a triple well structure is particularly adopted. Without this, the same effect as the conventional triple well structure can be obtained.

A buried polysilicon layer 2b is provided below the p-type silicon semiconductor layer 3 in the memory cell array section A via an oxide film layer 2c, and the potential of the buried polysilicon layer 2b is fixed at the substrate bias potential. By making the access transistor of each transistor have a double gate structure, the off-leak current of the access transistor is reduced, the cut-off characteristic is improved, and the refresh characteristic of the DRAM is improved.

Further, by performing the element isolation in the memory cell array section A by the field shield element isolation method,
Unlike the case where the insulator isolation method such as the LOCOS method or the STI method is used, the potential of the p-type silicon semiconductor layer 3 of the memory cell array portion A is fixed by local electric field control,
The substrate floating effect peculiar to the OI structure can be avoided.

On the other hand, in the peripheral circuit section B, the STI
By using an insulator isolation method such as a method for element isolation, for example, element isolation in a CMOS structure can be easily performed.

[0105]

According to the present invention, the substrate portion of the memory cell array region is electrically insulated and separated from other substrate portions by the buried insulating layer having the SOI structure and the trench isolation structure. Of the substrate portion can be independently controlled, and in particular, the same effect as the conventional triple well structure can be obtained without employing the triple well structure.

Therefore, since the triple well structure is not adopted, the substrate concentration can be kept relatively low, and the problems of deterioration of the substrate bias effect and deterioration of the holding characteristics of the memory cell capacitor can be avoided.

A buried polycrystalline semiconductor layer is provided below the substrate in the memory cell array region via an insulating layer.
By fixing the potential of the buried polycrystalline semiconductor layer to, for example, the substrate bias potential and making the access transistor of the DRAM memory cell have a double gate structure, for example, the off-leak current (standby current) of the access transistor is reduced. The cutoff characteristics are improved, and the refresh characteristics of the DRAM are improved.

Further, by performing element isolation in the memory cell array region by a field shield element isolation method,
Unlike the case where the insulator isolation method such as the LOCOS method or the STI method is used, the potential of the substrate in the memory cell array region is fixed by local electric field control, thereby avoiding the substrate floating effect peculiar to the SOI structure. Can be.

At this time, if the memory capacitor is constituted by, for example, a reverse wrench capacitor and the cell plate of the memory capacitor is constituted integrally with the field shield electrode, the contact structure to them and the manufacturing process can be simplified. Can be.

On the other hand, in the peripheral circuit area, for example, LOC
By using an insulator isolation method such as the OS method or the STI method for element isolation, element isolation in a CMOS structure or the like can be easily performed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a plan layout view of a memory cell array portion of the DRAM according to the first embodiment of the present invention.

FIG. 3 is an overall schematic configuration diagram of the DRAM according to the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a method of manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 5 is a schematic cross-sectional view showing a method for manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 6 is a schematic cross-sectional view showing a method for manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 7 is a schematic cross-sectional view showing a method of manufacturing the DRAM according to the first embodiment of the present invention in the order of steps.

FIG. 8 is a schematic sectional view of a DRAM according to a second embodiment of the present invention.

FIG. 9 is a plan layout view of a memory cell array portion of a DRAM according to a second embodiment of the present invention.

FIG. 10 is an overall schematic configuration diagram of a DRAM according to a second embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps.

FIG. 12 is a schematic cross-sectional view showing a method for manufacturing the DRAM according to the second embodiment of the present invention in the order of steps.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type single crystal silicon semiconductor substrate 2a, 2c ... buried oxide film layer 2b ... buried polysilicon layer 3 ... p-type single crystal silicon semiconductor layer 3a ... n-well 4, 5, 30 ... trench 6 ... silicon oxide film layer 8 ... n-type polysilicon film (cell plate) 8a, 50 ... field shield electrode 9 ... capacitor dielectric film 10 ... n-type polysilicon film (storage node) 10a ... storage contact 11 ... n-type polysilicon gate (word line) 12 , 12b, 13, 13b, 25... N ⁺ diffusion layers 12a, 13a, 24... N ⁻ diffusion layers 14... N-type polysilicon film (lead electrode) 15... Interlayer insulating film 16. ... Tungsten (W) plug 18 ... Metal wiring (bit line) 19 ... Metal wiring ( _Vcc / 2) 20, 52 ... p ⁺ Diffusion layer 22: metal wiring (V _bb ) 23: n-type polysilicon gate 27, 53: metal wiring 28: LOCOS oxide film 51: p ^- diffusion layer A: memory cell array part B: peripheral circuit part

Claims (14)

[Claims] 1. A first insulating layer provided on a semiconductor substrate, a polycrystalline semiconductor layer provided on the first insulating layer, and a second insulating layer provided on the polycrystalline semiconductor layer. And a single crystal semiconductor layer provided on the second insulating layer, wherein each element of a memory cell array region and a peripheral circuit region is formed on the single crystal semiconductor layer. A semiconductor memory device, wherein isolation between elements is performed by a shield element isolation method, and isolation between elements is performed in the peripheral circuit region by an insulator isolation method. 2. A third insulating layer is provided in a trench formed so as to surround the memory cell array region and penetrate the single crystal semiconductor layer, and a third insulating layer is formed by the second and third insulating layers. 2. The semiconductor memory device according to claim 1, wherein said single crystal semiconductor layer in said memory cell array region is electrically insulated and separated from said single crystal semiconductor layer in said peripheral circuit region. 3. The semiconductor memory device according to claim 2, wherein isolation between elements in said peripheral circuit region is performed by a LOCOS method. 4. The semiconductor device according to claim 1, wherein at least the polycrystalline semiconductor layer in the memory cell array region is fixed at substantially the same potential as the single crystal semiconductor layer in the memory cell array region. The semiconductor memory device according to claim 1. 5. The semiconductor device according to claim 4, wherein at least the polycrystalline semiconductor layer in the memory cell array region and the single crystal semiconductor layer in the memory cell array region are both fixed at a back bias potential. Semiconductor storage device. 6. The semiconductor memory device according to claim 1, wherein one-transistor / one-capacitor type memory cells are formed in said memory cell array region. 7. The semiconductor memory device according to claim 6, wherein a capacitor structure of each memory cell is formed in a trench provided in said substrate portion of said memory cell array region. 8. The capacitor structure of each of the memory cells,
The memory cell array region includes a cell plate provided on the inner surface of the trench via an insulating film, a capacitor insulating film provided on the cell plate, and a storage node provided on the capacitor insulating film. 8. The semiconductor memory device according to claim 7, wherein 9. The semiconductor memory device according to claim 8, wherein a field shield electrode of a field shield element isolation structure in said memory cell array region is formed continuously with said cell plate. 10. The semiconductor memory device according to claim 6, wherein the capacitor structure of each memory cell is configured in a stack type. 11. The semiconductor memory device according to claim 10, wherein the cell plate having the capacitor structure is electrically connected to a field shield electrode having a field shield element isolation structure in the memory cell array region. 12. A first single crystal semiconductor substrate having a polycrystalline semiconductor layer formed on a main surface thereof with a first insulating film interposed therebetween, and a second single crystal having a second insulating film formed on a main surface thereof. After bonding the semiconductor substrate to each other with the main surfaces thereof facing each other, processing the thickness of the second single crystal semiconductor substrate to form the first insulating film on the first single crystal semiconductor substrate. Forming a single crystal semiconductor layer via the polycrystalline semiconductor layer and the second insulating film; forming an element isolation structure in a portion of the single crystal semiconductor layer that becomes a peripheral circuit region; A first portion of a depth reaching at least the second insulating film is provided between the portion to be the peripheral circuit region and the portion to be the memory cell array region of the crystalline semiconductor layer so as to surround the portion to be the memory cell array region. Forming a trench, and Forming a second trench for forming a memory cell capacitor at a predetermined position of the single crystal semiconductor layer in a portion to be a memory cell array region; and forming an entire surface so as to fill the first and second trenches. Forming a third insulating film; removing the third insulating film outside the first and second trenches; and then removing the third insulating film in the second trench. Forming a fourth insulating film over the entire surface of the portion to be the memory cell array region including the inner surface of the second trench; and forming a first conductive film on the fourth insulating film. Patterning the first conductive film so as to leave the first conductive film in a region serving as an element isolation region in the memory cell array region and a region including the second trench continuous therewith; One Forming a fifth insulating film on the conductive film; and forming a second conductive film on the fifth insulating film, and then forming the second conductive film on a storage node pattern of the memory capacitor. Processing; forming MOSFETs at predetermined portions of the portion to be the peripheral circuit region and the portion to be the memory cell array region; and forming the MOSFET in the portion to be the memory cell array region.
Electrically connecting one of the diffusion layers of the OSFET to the second conductive film. 13. A LOCOS oxide film is formed as the element isolation structure in a portion to be the peripheral circuit region,
13. The method of manufacturing a semiconductor memory device according to claim 12, wherein the LOCOS oxide film is polished and processed to be flush with a main surface of the single crystal semiconductor layer. 14. A first single crystal semiconductor substrate having a polycrystalline semiconductor layer formed on a main surface thereof with a first insulating film interposed therebetween, and a second single crystal having a second insulating film formed on a main surface thereof. After bonding the semiconductor substrate to each other with the main surfaces thereof facing each other, processing the thickness of the second single crystal semiconductor substrate to form the first insulating film on the first single crystal semiconductor substrate. Forming a single crystal semiconductor layer via the polycrystalline semiconductor layer and the second insulating film; forming an element isolation structure in a portion of the single crystal semiconductor layer that becomes a peripheral circuit region; A trench having a depth at least reaching the second insulating film is formed between the portion serving as the peripheral circuit region and the portion serving as the memory cell array region of the crystalline semiconductor layer so as to surround the portion serving as the memory cell array region. And the trench Forming a third insulating film so as to fill the inside, forming a field shield element isolation structure in the portion to be the peripheral circuit region, and forming a portion to be the peripheral circuit region and the portion to be the memory cell array region Forming a MOSFET at a predetermined location, and forming a memory capacitor having a storage node electrically connected to one of the diffusion layers of the MOSFET in the portion of the memory cell array region. A method for manufacturing a semiconductor memory device, comprising: