EP1213757A3 - Integrated circuits having and adjacent p-type doped regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same - Google Patents

Integrated circuits having and adjacent p-type doped regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same Download PDF

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Publication number
EP1213757A3
EP1213757A3 EP01128854A EP01128854A EP1213757A3 EP 1213757 A3 EP1213757 A3 EP 1213757A3 EP 01128854 A EP01128854 A EP 01128854A EP 01128854 A EP01128854 A EP 01128854A EP 1213757 A3 EP1213757 A3 EP 1213757A3
Authority
EP
European Patent Office
Prior art keywords
adjacent
type doped
doped regions
therebetween
methods
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP01128854A
Other languages
German (de)
French (fr)
Other versions
EP1213757B1 (en
EP1213757A2 (en
Inventor
Yong-Chul Oh
Gyo-Young Jin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority to EP04020046A priority Critical patent/EP1487011B1/en
Publication of EP1213757A2 publication Critical patent/EP1213757A2/en
Publication of EP1213757A3 publication Critical patent/EP1213757A3/en
Application granted granted Critical
Publication of EP1213757B1 publication Critical patent/EP1213757B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer that reduces a stress between the integrated circuit substrate and the insulator layer.
EP01128854A 2000-12-09 2001-12-04 Integrated circuits having adjacent p-type doped regions having shallow trench isolation structures without liner layers therebetween and methods of forming same Expired - Lifetime EP1213757B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04020046A EP1487011B1 (en) 2000-12-09 2001-12-04 Integrated circuits having adjacent regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR2000074915 2000-12-09
KR10-2000-0074915A KR100382728B1 (en) 2000-12-09 2000-12-09 Semiconductor device having shallow trench isolation structure and method for manufacturing the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
EP04020046A Division EP1487011B1 (en) 2000-12-09 2001-12-04 Integrated circuits having adjacent regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same

Publications (3)

Publication Number Publication Date
EP1213757A2 EP1213757A2 (en) 2002-06-12
EP1213757A3 true EP1213757A3 (en) 2003-09-03
EP1213757B1 EP1213757B1 (en) 2007-04-11

Family

ID=19702879

Family Applications (2)

Application Number Title Priority Date Filing Date
EP01128854A Expired - Lifetime EP1213757B1 (en) 2000-12-09 2001-12-04 Integrated circuits having adjacent p-type doped regions having shallow trench isolation structures without liner layers therebetween and methods of forming same
EP04020046A Expired - Lifetime EP1487011B1 (en) 2000-12-09 2001-12-04 Integrated circuits having adjacent regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP04020046A Expired - Lifetime EP1487011B1 (en) 2000-12-09 2001-12-04 Integrated circuits having adjacent regions having shallow trench isolation structures without liner layers therein therebetween and methods of forming same

Country Status (7)

Country Link
US (2) US6642125B2 (en)
EP (2) EP1213757B1 (en)
JP (1) JP2002231805A (en)
KR (1) KR100382728B1 (en)
CN (1) CN1277300C (en)
DE (2) DE60127799T2 (en)
TW (1) TWI247377B (en)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6906793B2 (en) * 2000-12-11 2005-06-14 Canesta, Inc. Methods and devices for charge management for three-dimensional sensing
KR100413830B1 (en) * 2001-04-30 2003-12-31 삼성전자주식회사 Semiconductor device having trench isolation structure and method of fabricating the same
JP4173658B2 (en) * 2001-11-26 2008-10-29 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
KR100400254B1 (en) * 2001-12-18 2003-10-01 주식회사 하이닉스반도체 Method for forming the semiconductor device
JP2003273206A (en) * 2002-03-18 2003-09-26 Fujitsu Ltd Semiconductor and its manufacturing method
JP2004047599A (en) * 2002-07-10 2004-02-12 Renesas Technology Corp Semiconductor device and its manufacture
KR100443126B1 (en) * 2002-08-19 2004-08-04 삼성전자주식회사 trench structure and method of forming thereof
US7081395B2 (en) * 2003-05-23 2006-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials
US6887798B2 (en) * 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
KR100971432B1 (en) * 2003-06-30 2010-07-21 주식회사 하이닉스반도체 Method of forming isolation layer for semiconductor device
KR100839528B1 (en) * 2003-06-30 2008-06-19 주식회사 하이닉스반도체 Semiconductor device with trench type isolation and method for making the same
US7244680B2 (en) * 2003-11-14 2007-07-17 Macronix International Co., Ltd. Method of simultaneously fabricating isolation structures having rounded and unrounded corners
KR100602085B1 (en) * 2003-12-31 2006-07-14 동부일렉트로닉스 주식회사 Semiconductor device and manufacturing method thereof
US20050158897A1 (en) * 2004-01-21 2005-07-21 Jhy-Jyi Sze Image sensor device and method of fabricating the same
KR100546161B1 (en) * 2004-07-13 2006-01-24 주식회사 하이닉스반도체 Device Separation Method of Semiconductor Device
JP4515951B2 (en) * 2005-03-31 2010-08-04 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
JP2006286788A (en) * 2005-03-31 2006-10-19 Fujitsu Ltd Semiconductor apparatus and its manufacturing method
KR100695868B1 (en) * 2005-06-23 2007-03-19 삼성전자주식회사 Isolation Layer and Method of manufacturing using the same, apparatus for a Semiconductor device having the Isolation Layer and Method of manufacturing using the same
US7396728B2 (en) * 2005-06-29 2008-07-08 Texas Instruments Incorporated Methods of improving drive currents by employing strain inducing STI liners
US7384861B2 (en) * 2005-07-18 2008-06-10 Texas Instruments Incorporated Strain modulation employing process techniques for CMOS technologies
US7514309B2 (en) * 2005-07-19 2009-04-07 Texas Instruments Incorporated Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process
US20070200196A1 (en) * 2006-02-24 2007-08-30 Lattice Semiconductor Corporation Shallow trench isolation (STI) devices and processes
US7691722B2 (en) 2006-03-14 2010-04-06 Micron Technology, Inc. Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability
US20070267715A1 (en) * 2006-05-18 2007-11-22 Sunil Mehta Shallow trench isolation (STI) with trench liner of increased thickness
US7892931B2 (en) * 2006-12-20 2011-02-22 Texas Instruments Incorporated Use of a single mask during the formation of a transistor's drain extension and recessed strained epi regions
US20080205023A1 (en) * 2007-02-27 2008-08-28 International Business Machines Corporation Electronic components on trenched substrates and method of forming same
KR100891534B1 (en) * 2007-10-26 2009-04-03 주식회사 하이닉스반도체 Method of manufacturing semiconductor device
US20090191688A1 (en) * 2008-01-28 2009-07-30 Texas Instruments Incorporated Shallow Trench Isolation Process Using Two Liners
KR101446331B1 (en) * 2008-02-13 2014-10-02 삼성전자주식회사 Method of manufacturing semiconductor device
US8003482B2 (en) 2009-11-19 2011-08-23 Micron Technology, Inc. Methods of processing semiconductor substrates in forming scribe line alignment marks
CN102693932B (en) * 2011-03-23 2014-06-11 中芯国际集成电路制造(上海)有限公司 Manufacturing method of shallow trench isolation structure
DK177321B1 (en) * 2011-05-10 2013-01-02 Skandinavisk HTP ApS Paper for transfer pattern printing
CN102412184B (en) * 2011-05-23 2014-03-12 上海华力微电子有限公司 Manufacture method of shallow trench isolation structure for adjusting stress of isolation oxide by ion implantation
US8927387B2 (en) * 2012-04-09 2015-01-06 International Business Machines Corporation Robust isolation for thin-box ETSOI MOSFETS
KR20150052065A (en) 2012-09-04 2015-05-13 피에스4 뤽스코 에스.에이.알.엘. Semiconductor device and method for producing same
US9006080B2 (en) * 2013-03-12 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Varied STI liners for isolation structures in image sensing devices
CN104240762B (en) * 2013-06-09 2018-06-01 中芯国际集成电路制造(上海)有限公司 Anti-fuse structures and programmed method
CN105826191B (en) * 2015-01-07 2019-09-17 中芯国际集成电路制造(上海)有限公司 The preparation method of fleet plough groove isolation structure
CN106711213B (en) * 2015-07-20 2021-02-26 联华电子股份有限公司 Semiconductor element and manufacturing method thereof
US9812548B2 (en) * 2015-09-08 2017-11-07 Maxpower Semiconductor, Inc. Power device having a polysilicon-filled trench with a tapered oxide thickness
US11335770B2 (en) 2020-05-28 2022-05-17 Winbond Electronics Corp. Semiconductor isolation structures having different configurations in different device regions and method of forming the same
CN116344623B (en) * 2023-05-30 2023-08-22 粤芯半导体技术股份有限公司 High-voltage MOS device and preparation method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07176606A (en) * 1993-12-21 1995-07-14 Toshiba Corp Semiconductor device and fabrication thereof
JPH11220017A (en) * 1998-01-30 1999-08-10 Mitsubishi Electric Corp Semiconductor device and its manufacture
US5940717A (en) * 1997-12-30 1999-08-17 Siemens Aktiengesellschaft Recessed shallow trench isolation structure nitride liner and method for making same
JPH11284137A (en) * 1998-03-30 1999-10-15 Nippon Steel Corp Semiconductor storage device and its manufacture
US5990002A (en) * 1997-04-18 1999-11-23 Micron Technology, Inc Method of making an antireflective structure
EP0967636A2 (en) * 1998-06-16 1999-12-29 Siemens Aktiengesellschaft Electrically isolated semiconductor devices
JP2000124303A (en) * 1998-10-09 2000-04-28 Samsung Electronics Co Ltd Manufacturing trench isolation
US6064105A (en) * 1997-10-09 2000-05-16 Vantis Corporation Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848936A (en) * 1981-09-10 1983-03-23 Fujitsu Ltd Preparation of semiconductor device
JPH02273956A (en) * 1989-04-15 1990-11-08 Fujitsu Ltd Semiconductor device
US5981341A (en) * 1997-12-05 1999-11-09 Advanced Micro Devices Sidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned flash memory core
CN1219328C (en) * 1998-02-19 2005-09-14 国际商业机器公司 Field effect transistors with improved implants and method for making such transistors
KR20000009808A (en) * 1998-07-28 2000-02-15 윤종용 Method of fabricating trench isolation
US6468849B1 (en) * 1999-06-11 2002-10-22 Texas Instruments Incorporated Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07176606A (en) * 1993-12-21 1995-07-14 Toshiba Corp Semiconductor device and fabrication thereof
US5990002A (en) * 1997-04-18 1999-11-23 Micron Technology, Inc Method of making an antireflective structure
US6064105A (en) * 1997-10-09 2000-05-16 Vantis Corporation Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide
US5940717A (en) * 1997-12-30 1999-08-17 Siemens Aktiengesellschaft Recessed shallow trench isolation structure nitride liner and method for making same
JPH11220017A (en) * 1998-01-30 1999-08-10 Mitsubishi Electric Corp Semiconductor device and its manufacture
US6245641B1 (en) * 1998-01-30 2001-06-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device comprising trench isolation insulator film and method of fabricating the same
JPH11284137A (en) * 1998-03-30 1999-10-15 Nippon Steel Corp Semiconductor storage device and its manufacture
EP0967636A2 (en) * 1998-06-16 1999-12-29 Siemens Aktiengesellschaft Electrically isolated semiconductor devices
JP2000124303A (en) * 1998-10-09 2000-04-28 Samsung Electronics Co Ltd Manufacturing trench isolation
US6251746B1 (en) * 1998-10-09 2001-06-26 Samsung Electronics Co., Ltd. Methods of forming trench isolation regions having stress-reducing nitride layers therein

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 10 30 November 1995 (1995-11-30) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 13 30 November 1999 (1999-11-30) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 01 31 January 2000 (2000-01-31) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 07 29 September 2000 (2000-09-29) *

Also Published As

Publication number Publication date
EP1487011A1 (en) 2004-12-15
US6642125B2 (en) 2003-11-04
EP1213757B1 (en) 2007-04-11
DE60127799D1 (en) 2007-05-24
EP1213757A2 (en) 2002-06-12
CN1277300C (en) 2006-09-27
US20020070420A1 (en) 2002-06-13
TWI247377B (en) 2006-01-11
EP1487011B1 (en) 2010-02-03
CN1359145A (en) 2002-07-17
DE60127799T2 (en) 2007-12-27
JP2002231805A (en) 2002-08-16
KR20020045656A (en) 2002-06-20
KR100382728B1 (en) 2003-05-09
US20040021197A1 (en) 2004-02-05
DE60141256D1 (en) 2010-03-25

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