US20070267715A1

US20070267715A1 - Shallow trench isolation (STI) with trench liner of increased thickness

Info

Publication number: US20070267715A1
Application number: US11/436,503
Authority: US
Inventors: Sunil Mehta; Stewart Logie; Steve Fong
Original assignee: Lattice Semiconductor Corp
Current assignee: Lattice Semiconductor Corp
Priority date: 2006-05-18
Filing date: 2006-05-18
Publication date: 2007-11-22
Also published as: US7989911B1; US7985656B1

Abstract

Improved shallow trench isolation (STI) techniques are provided for semiconductor devices. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a substrate, a first trench in the substrate, and a second trench in the substrate. A first silicon dioxide liner substantially lines the first trench. A second silicon dioxide liner substantially lines the second trench, wherein the second silicon dioxide liner has a thickness greater than a thickness of the first silicon dioxide liner. A silicon nitride liner is on the first silicon dioxide liner in the first trench but not on the second silicon dioxide liner in the second trench. A dielectric material fills the first and second trenches.

Description

TECHNICAL FIELD

The present invention relates generally to integrated circuits and, more particularly, to the isolation of integrated circuit components.

BACKGROUND

Integrated circuits having transistors in close proximity to each other can often exhibit unintended current leakage between adjacent transistors. As a result, various isolation techniques have been developed to reduce such leakage currents.
Shallow trench isolation (STI) is one conventional approach frequently used to reduce leakage currents for integrated circuits having nominal feature sizes approximately equal to or less than 90 nm. STI entails the creation of a trench between adjacent transistors which is then filled with a dielectric material. The dielectric material (for example, silicon dioxide) provides a barrier which impedes the flow of leakage current between the transistors on opposite sides of the trench.
Unfortunately, the introduction of STI trenches can cause unintended stress on the channels of adjacent transistors. Such STI stress is difficult to model and complicates circuit design. For example, STI stress can depend on the channel type, doping level, width, and length of adjacent transistors, as well as the spacing between the channel and the trench and the spacing between additional trenches.
This stress is generally most pronounced in low voltage transistors (e.g., transistors having an operating voltage in the range of approximately 1.2 volts to 3.3 volts). In such low voltage transistors, STI stress can cause reduced electron mobility and increased hole mobility, resulting in slightly enhanced PMOS performance and significantly degraded NMOS performance. The net effect of such changes is slower performance of integrated circuits (for example, CMOS circuits).
For low voltage transistors, such stress effects can be reduced by lining the STI trench with silicon nitride. Unfortunately, such configurations are generally only suitable for low voltage applications. The introduction of the silicon nitride liner can reduce the performance of high voltage transistors, such as flash memory cells and circuitry that supports flash operation or transistors used at input/output pins, and/or having an operating voltage in the range of approximately 5 volts and higher.
For example, the introduction of a silicon nitride liner can interfere with data retention of adjacent flash memory cells. Because silicon nitride tends to absorb hydrogen, it can interfere with the injection and retention of hot electrons with respect to the floating gates of flash memory cells. The silicon nitride layer can also interfere with the growth of additional silicon dioxide in the corners of STI trenches which may be desired to further round the corners in order to provide more uniform electric field distribution.
As a result, conventional STI techniques are generally unsatisfactory for applications where low voltage and high voltage transistors are embedded within a single integrated circuit. Integrated circuits used in programmable logic devices (PLDs) may include high voltage flash memory cells embedded with low voltage transistors in a single integrated circuit. Accordingly, the use of STI trenches in such devices without a silicon nitride liner can increase stress effects on low voltage transistors, but the use of an additional silicon nitride liner can reduce performance of high voltage transistors. Moreover, the creation of a separate high voltage trench after the creation of a low voltage trench on the same substrate can unduly increase manufacturing and design costs.
As a result, there is a need for an improved STI implementation that reduces the disadvantages described above when applied to integrated circuits that include both high voltage and low voltage transistors.

SUMMARY

In accordance with one embodiment of the present invention, an integrated circuit includes a substrate; a first trench in the substrate; a second trench in the substrate; a first silicon dioxide liner substantially lining the first trench; a second silicon dioxide liner substantially lining the second trench, wherein the second silicon dioxide liner has a thickness greater than a thickness of the first silicon dioxide liner; a silicon nitride liner on the first silicon dioxide liner in the first trench but not on the second silicon dioxide liner in the second trench; and a dielectric material filling the first and second trenches.
In accordance with another embodiment of the present invention, an integrated circuit includes a substrate; a trench in the substrate; a silicon dioxide liner substantially lining the trench, the liner having a first portion and a second portion, wherein the first portion of the silicon dioxide liner is thinner than the second portion of the silicon dioxide liner; a silicon nitride liner on the first portion of the silicon dioxide liner but not on the second portion; a dielectric material filling the trench; a first transistor region in the substrate and adjacent to a first side of the trench; and a second transistor region in the substrate and adjacent to a second side of the trench, wherein the trench is adapted to isolate the first transistor region from the second transistor region.
In accordance with another embodiment of the present invention, a method of manufacturing an integrated circuit includes etching first and second trenches adjacent to high and low voltage transistor regions of a substrate, respectively; oxidizing a silicon dioxide layer substantially lining the first and second trenches; depositing a silicon nitride layer on the silicon dioxide layer in the first and second trenches; etching the silicon nitride layer from the first trench but not the second trench; increasing a thickness of the silicon dioxide layer in the first trench; and filling the first and second trenches with a dielectric material.
The scope of the invention is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a process of manufacturing a semiconductor device providing shallow trench isolation (STI) in accordance with the present invention.

FIGS. 2A-E illustrate cross-sectional side views of a first semiconductor device undergoing the process of FIG. 1 in accordance with an embodiment of the present invention.

FIGS. 3A-E illustrate cross-sectional side views of a second semiconductor device undergoing the process of FIG. 1 in accordance with an embodiment of the present invention.

Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.

DETAILED DESCRIPTION

The various techniques disclosed herein are applicable to a wide variety of integrated circuits and applications. Several exemplary implementations will be utilized to illustrate the techniques in accordance with one or more embodiments of the present invention. However, it should be understood that this is not limiting and that the techniques disclosed herein may be implemented as desired, in accordance with one or more embodiments of the present invention, in various types of integrated circuits.
FIG. 1 illustrates a process of manufacturing a semiconductor device providing shallow trench isolation (STI) in accordance with the present invention. In one embodiment, the process of FIG. 1 can be applied to the manufacture of integrated circuits having a nominal feature size approximately equal to 90 nm or less.
As further described herein, the process of FIG. 1 can be performed to create STI regions suitable for use in integrated circuits including both low voltage transistors (e.g., having an operating voltage in the range of approximately 1.2 volts to 2.5 volts) and high voltage transistors (e.g., flash memory cells, transistors used at input/output pins, and/or having an operating voltage in the range of approximately 3.3 volts and higher). It will be appreciated, however, that transistors having an operating voltage of approximately 3.3 volts may be considered low voltage transistors or high voltage transistors in particular applications. Accordingly, transistors having an operating voltage of approximately 3.3 volts may be implemented in appropriate transistor regions adapted to support either high voltage transistors or low voltage transistors as may be desired in particular applications.
FIGS. 2A-E and 3A-E illustrate cross-sectional side views of first and second semiconductor devices 200 and 300, respectively, undergoing the process of FIG. 1 in accordance with various embodiments of the present invention. Semiconductor devices 200 and 300 may be implemented in any desired type of integrated circuit including both high voltage and low voltage transistors. For example, in one embodiment, each of semiconductor devices 200 and 300 may be a programmable logic device (PLD) such as a complex programmable logic device (CPLD) or a field programmable gate array (FPGA).
FIGS. 2A and 3A illustrate semiconductor devices 200 and 300 having undergone steps 110 through 135 of the process of FIG. 1 as further described herein. As illustrated, semiconductor devices 200 and 300 include substrates 205 and 305 (for example, p-type substrates) having a plurality of trenches 220/230 and 320/330/380 separating a plurality of transistor regions 210A-D and 310A-B, respectively. It will be appreciated that transistors may be manufactured in transistor regions 210A-D and 310A-B following the process of FIG. 1. It will also be appreciated that, for purposes of clarity, a portion of semiconductor device 200 between trenches 220 and 230 is not shown in FIGS. 2A-E. As such, it will be understood that transistor regions 210B and 210C may extend into the portion of semiconductor device 200 not shown. For example, transistor regions 210B and 210C may form a transistor region adjacent to and between trenches 230 and 220.
Turning now to the particular steps of FIG. 1, in step 110, pad oxide layers 260 and 360 are oxidized (i.e., grown) on substrates 205 and 305, respectively. In step 115, hard masks 290 and 390 (i.e., isolation masks) are provided on pad oxide layers 260 and 360, respectively, to isolate transistor regions 210A-D and 310A-B.
A dry etch (step 120) and wet etch (step 125) may then be performed on substrates 205 and 305 to create trenches 220/230 and 320/330/380, respectively. Wet etch step 125 can improve the cleaning and rounding of inside corners of trenches 220/230 and 320/330/380 prior to the performance of further steps in the process of FIG. 1.
At step 130, exposed surfaces (i.e., unmasked portions) of substrates 205 and 305 are oxidized to form silicon dioxide layers 240 and 340 which form silicon dioxide liners in each of trenches 220/230 and 320/330/380. In one embodiment, silicon dioxide layers 240 and 340 may be approximately 3 nm thick.
Silicon nitride layers 250 and 350 are then deposited on top of silicon dioxide layers 240 and 340, respectively (step 135), resulting in the structures illustrated in FIGS. 2A and 3A. In one embodiment, each of silicon nitride layers 250 and 350 may exhibit a thickness in the range of approximately 6 nm to approximately 10 nm.
At step 140, an etch mask is provided, which is followed by step 145 in which portions of silicon nitride layers 250 and 350 are etched. FIGS. 2B and 3B illustrate semiconductor devices 200 and 300, respectively, following etching step 145. In the embodiment of FIG. 2B, all portions of silicon nitride layer 250 in trench 220 and above transistor regions 210C-D have been etched away. Conversely, the remaining portions of silicon nitride layer 250 in trench 230 and above transistor regions 210A-B have not been etched in step 145. As a result, the remaining portions of silicon nitride layer 250 effectively provide trench 230 with a silicon nitride liner.
In the embodiment of FIG. 3B, silicon nitride layer 350 has been selectively etched away during step 145. As illustrated, silicon nitride layer 350 has been removed from trench 320 and portion 380A of trench 380. In contrast, portions of silicon nitride layer 350 remain in trench 330 and portion 380B of trench 380. As a result, the remaining portions of silicon nitride layer 350 effectively provide trench 330 with a silicon nitride liner, and also provide portion 380B of trench 380 with a silicon nitride liner. Although trench portions 380A and 380B are shown as substantially equal in width, it will be appreciated that the relative widths of the portions can vary to some degree without affecting the efficacy of the structure.
In step 150, additional silicon dioxide is oxidized on exposed portions of silicon dioxide layers 240 and 340. In one embodiment, step 150 may be performed using a high temperature (for example, in excess of approximately 1000 degrees C.) oxide growth process. FIGS. 2C and 3C illustrate embodiments of semiconductor devices 200 and 300, respectively, following the performance of step 150.
In FIG. 2C, the thickness of a portion of silicon dioxide layer 240 has increased to create a thicker silicon dioxide layer 245 (i.e., a thicker silicon dioxide liner) in trench 220. Similarly in FIG. 3C, the thickness of a portion of silicon dioxide layer 340 has increased to create a thicker silicon dioxide layer 345 (i.e., a thicker silicon dioxide liner) in trench 320 and in portion 380A of trench 380.
Advantageously, the performance of step 150 has the effect of causing a plurality of corners 247 and 347 of thicker silicon dioxide layers 245 and 345 to become rounded. In this regard, the rounding of corners 247 and 347 can improve the charge-to-breakdown (QBD) in high voltage transistors manufactured in transistor regions 210C-D and 310A. In particular, the rounding of corners 247 and 347 can aid in the prevention of gate oxide thinning and more evenly distribute electric fields (e.g., less current will be concentrated in trench corners 247 and 347) for high voltage transistors manufactured in transistor regions 210C-D and 310A. It will be appreciated that because thicker silicon dioxide layers 245 and 345 can reduce the effective width of transistors in transistor regions 210C-D and 310A, high voltage transistors are preferred over low voltage transistors in such regions. In one embodiment, thicker silicon dioxide layers 245 and 345 may each exhibit a thickness of approximately 10 nm, approximately 20 nm, approximately 30 nm, or a thickness in the range of approximately 10 nm to approximately 30 nm.
At step 155, trenches 220/230 and 320/330/380 are filled with dielectric material 225/235 and 325/335/385 (for example, silicon dioxide), respectively. Any excess portions of dielectric material 225/235 and 325/335/385 can then be removed through planarization (for example, chemical-mechanical planarization or polishing) of the top surfaces of semiconductor devices 200 and 300, respectively (step 160).
FIGS. 2D and 3D illustrate semiconductor devices 200 and 300, respectively, following step 160. As illustrated in FIG. 2D, transistor regions 210C and 210D are isolated from each other by trench 220 having dielectric material 225 and a silicon dioxide liner in trench 220 provided by thicker silicon dioxide layer 245. In addition, transistor regions 210A and 210B are isolated from each other by trench 230 having dielectric material 235, a silicon dioxide liner in trench 230 provided by silicon dioxide layer 240, and a silicon nitride liner in trench 230 provided by silicon nitride layer 250 (i.e., a dual liner configuration).
As illustrated in FIG. 3D, transistor regions 310A and 310B are isolated from each other by trench 380 having dielectric material 385, a silicon dioxide liner in portion 380A of the trench provided by thicker silicon dioxide layer 345, and liners in portion 380B of the trench provided by silicon dioxide layer 340 and silicon nitride layer 350 (i.e., a dual liner configuration).
Following step 160, an optional oxide recess etch operation (step 165) and a nitride strip operation (step 170) may be performed to remove remaining portions of dielectric material 225/235 and 325/335/385, silicon nitride layers 250/350, hard masks 290/390, and pad oxide layers 260/360 above substrates 205/305. FIGS. 2E and 3E illustrate semiconductor devices 200 and 300, respectively, following step 170. It will be appreciated that additional conventional processing operations may also be performed (for example, a high density plasma densification operation) to further prepare semiconductor devices 200 and 300 for further processing, such as the manufacture of transistors in transistor regions 210A-D and 310A-B.
In view of FIGS. 2E and 3E, it will be appreciated that the structure of semiconductor devices 200 and 300 can provide isolation for both low and high voltage transistors embedded within the same device. For example, in semiconductor device 200, high voltage transistors may be provided in transistor regions 210C-D and remain isolated from each other by trench 220. Because the previously-deposited silicon nitride layer 250 has been removed from trench 220, high voltage transistors manufactured in transistor regions 210C-D need not experience degraded performance (for example, reduced data retention tendencies in flash memory cells) resulting from silicon nitride in close proximity. In addition, the presence of thicker silicon dioxide layer 245 and the rounding exhibited by its corners 247 can improve the QBD of high voltage transistors manufactured in transistor regions 210C-D. As a result, the performance of hot carrier injection for flash memory cells manufactured in such regions can also be improved.
Also in semiconductor device 200, low voltage transistors may be provided in transistor regions 210A-B and remain isolated from each other by trench 230. Because trench 230 includes silicon nitride layer 250, STI stress effects on low voltage transistors manufactured in transistor regions 210A-B can be reduced.
In semiconductor device 300, high voltage transistors may be provided in transistor region 310A, and low voltage transistors may be provided in transistor region 310B. In this regard, low voltage and high voltage transistors can remain isolated from each other by a single trench 380. Because the previously-deposited silicon nitride layer 350 has been removed from portion 380A of trench 380, high voltage transistors manufactured in transistor region 310A need not experience degraded performance resulting from close proximity of silicon nitride. High voltage transistors in transistor region 310A can also exhibit improved QBD as previously discussed in relation to semiconductor device 200 due to the presence of thicker silicon dioxide layer 345 and the rounding exhibited by its corners 347.
Because portion 380B of trench 380 includes silicon nitride layer 350, STI stress effects on low voltage transistors manufactured in transistor region 310B can be reduced. It will be appreciated that trenches 320 and 330 can further isolate transistors provided in transistor regions 310A and 310B, respectively.
In view of the present disclosure, it will be appreciated that the various trenches of each of semiconductor devices 200 and 300 can advantageously be manufactured simultaneously in accordance with the process of FIG. 1. As a result, STI features can be provided for low voltage and high voltage transistors on the same substrate without incurring excessive additional processing costs and time.
Embodiments described herein illustrate but do not limit the invention. It should also be understood that numerous modifications and variations are possible in accordance with the principles of the present invention. Accordingly, the scope of the invention is defined only by the claims.

Claims

1. An integrated circuit comprising:

a substrate;

a first trench in the substrate;

a second trench in the substrate;

a first silicon dioxide liner substantially lining the first trench;

a second silicon dioxide liner substantially lining the second trench, wherein the second silicon dioxide liner has a thickness greater than a thickness of the first silicon dioxide liner;

a silicon nitride liner on the first silicon dioxide liner in the first trench but not on the second silicon dioxide liner in the second trench; and

a dielectric material filling the first and second trenches.

2. The integrated circuit of claim 1, wherein the second silicon dioxide liner comprises a plurality of rounded corners.

3. The integrated circuit of claim 1, wherein the silicon nitride layer is on substantially the entire first silicon dioxide liner in the first trench.

4. The integrated circuit of claim 1, wherein the silicon nitride layer is on substantially only half the first silicon dioxide liner in the first trench.

5. The integrated circuit of claim 1, wherein the substrate further comprises a transistor region adjacent to the first trench, wherein the transistor region is adapted to receive a low voltage transistor.

6. The integrated circuit of claim 1, wherein the substrate further comprises a transistor region adjacent to the second trench, wherein the transistor region is adapted to receive a high voltage transistor.

7. The integrated circuit of claim 1, wherein the substrate comprises a transistor region adjacent to the second trench, wherein the transistor region is adapted to receive a flash memory cell.

8. The integrated circuit of claim 1, wherein the integrated circuit is a programmable logic device (PLD).

9. An integrated circuit comprising:

a substrate;

a trench in the substrate;

a silicon dioxide liner substantially lining the trench, the liner having a first portion and a second portion, wherein the first portion of the silicon dioxide liner is thinner than the second portion of the silicon dioxide liner;

a silicon nitride liner on the first portion of the silicon dioxide liner but not on the second portion;

a dielectric material filling the trench;

a first transistor region in the substrate and adjacent to a first side of the trench; and

a second transistor region in the substrate and adjacent to a second side of the trench, wherein the trench is adapted to isolate the first transistor region from the second transistor region.

10. The integrated circuit of claim 9, wherein the first and second portions of the silicon dioxide liner are substantially equal in width.

11. The integrated circuit of claim 9, wherein the dielectric material is silicon dioxide.

12. The integrated circuit of claim 9, wherein the first transistor region is adapted to receive a low voltage transistor.

13. The integrated circuit of claim 9, wherein the second transistor region is adapted to receive a high voltage transistor.

14. The integrated circuit of claim 9, wherein the second transistor region is adapted to receive a flash memory cell.

15. The integrated circuit of claim 9, wherein the integrated circuit is a programmable logic device (PLD).

16. A method of manufacturing an integrated circuit, the method comprising:

etching first and second trenches adjacent to high and low voltage transistor regions of a substrate, respectively;

oxidizing a silicon dioxide layer substantially lining the first and second trenches;

depositing a silicon nitride layer on the silicon dioxide layer in the first and second trenches;

etching the silicon nitride layer from the first trench but not the second trench;

increasing a thickness of the silicon dioxide layer in the first trench; and

filling the first and second trenches with a dielectric material.

17. The method of claim 16, wherein the increasing further comprises rounding a plurality of corners of a silicon dioxide liner in the first trench formed by the silicon dioxide layer.

18. The method of claim 16, further comprising providing a low voltage transistor in the low voltage transistor region.

19. The method of claim 16, further comprising providing a high voltage transistor in the high voltage transistor region.

20. The method of claim 16 including concurrently with the prior steps:

etching a third trench, the third trench separated from the first trench by the high voltage transistor region and separated from the second trench by the low voltage transistor region;

oxidizing a silicon dioxide layer substantially lining the third trench;

depositing a silicon nitride layer on the silicon dioxide layer in the third trench;

etching the silicon nitride layer only from a first portion of the third trench adjacent to the high voltage transistor region;

increasing a thickness of the silicon dioxide layer only in the first portion of the third trench; and

filling the third trench with the dielectric material.