CN116344623B - High-voltage MOS device and preparation method thereof - Google Patents

High-voltage MOS device and preparation method thereof Download PDF

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Publication number
CN116344623B
CN116344623B CN202310620579.0A CN202310620579A CN116344623B CN 116344623 B CN116344623 B CN 116344623B CN 202310620579 A CN202310620579 A CN 202310620579A CN 116344623 B CN116344623 B CN 116344623B
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layer
gate
mos device
voltage mos
grid
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CN116344623A (en
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刘翔
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Yuexin Semiconductor Technology Co ltd
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Yuexin Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The application provides a high-voltage MOS device and a preparation method thereof. The high-voltage MOS device comprises a substrate, a grid electrode, a source electrode, a drain electrode, a drift region and a plurality of isolation trenches; the grid electrode is positioned in the substrate or on the upper surface of the substrate; the plurality of drift regions are positioned in the substrate and on two sides of the grid, the source electrode and the drain electrode are respectively positioned in the drift regions on two sides of the grid, a plurality of isolation trenches are arranged between the source electrode and the grid and between the drain electrode and the grid at intervals in the substrate, and a first inversion layer is arranged on the surface of the substrate between every two adjacent isolation trenches. According to the improved structural design, the plurality of grooves are arranged in the drift region between the source electrode and the drain electrode and the grid electrode at intervals, and the inversion layer is formed on the surface of the drift region between the isolation grooves, so that the electric field distribution of the device is improved, local field intensity peaks are avoided, the breakdown voltage of the device can be improved while the on-resistance of the device is not increased, and the further optimization of the performance of the device is facilitated.

Description

High-voltage MOS device and preparation method thereof
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device, and especially relates to a high-voltage MOS device and a preparation method thereof.
Background
A high voltage (MOS) device is a commonly used power device. The working principle is that when a control voltage is applied to the grid electrode, an electric field formed between the grid electrode and the source electrode can change the resistance value between the drain electrode and the source electrode. When the control voltage increases, the resistance between the drain and the source gradually decreases, thereby increasing the current. Conversely, when the control voltage decreases, the resistance between the drain and the source gradually increases, and the current decreases. The device has the advantages of high reliability, small volume, low power consumption, high response speed and the like, so that the device is widely applied to the fields of power electronics, communication, automobile electronics, aerospace and the like.
The main indicators of the high-voltage MOS device include (Breakdown Voltage, abbreviated as BV) in the off-state and the on-state on-resistance (Rdson) in the on-state. It is generally desirable that the breakdown voltage is as high as possible and the on-resistance is as low as possible. The breakdown voltage and on-resistance are determined mainly by the Drift region (Drift) length and concentration. In the prior art, the breakdown voltage is generally increased by increasing the length of the drift region and reducing the doping concentration of the drift region, but this increases the chip area and on-resistance, affecting the device performance and further miniaturization.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a high-voltage MOS device and a method for manufacturing the same, which are used for solving the problems of increasing the chip area and on-resistance, affecting the device performance and further miniaturization in the prior art by increasing the length of the drift region and reducing the doping concentration of the drift region to increase the breakdown voltage.
To achieve the above and other related objects, the present application provides a high voltage MOS device including a substrate, a gate, a source, a drain, a drift region, and a plurality of isolation trenches; the grid electrode is positioned in the substrate or on the upper surface of the substrate; the plurality of drift regions are positioned in the substrate and on two sides of the grid, the source electrode and the drain electrode are respectively positioned in the drift regions on two sides of the grid, a plurality of isolation trenches are arranged between the source electrode and the grid and between the drain electrode and the grid at intervals in the substrate, and a first inversion layer is arranged on the surface of the substrate between every two adjacent isolation trenches.
In an alternative scheme, the grid electrode is a planar grid structure, and the high-voltage MOS device is further provided with a side wall structure, wherein the side wall structure extends from the side surface of the grid electrode to the surface of the isolation groove adjacent to the grid electrode.
More optionally, the sidewall structure includes more than 3 insulating layers attached to each other in a lateral direction, and the dielectric constants of the insulating layers are increased in sequence along a direction away from the gate.
In another alternative, the gate is a trench gate, and includes a gate oxide layer and a gate conductive layer filled inside the gate oxide layer, where the thickness of the gate oxide layer at the bottom of the trench gate is greater than the thickness of the gate oxide layer on the sidewall.
More optionally, a highly doped electric field shielding structure is arranged at the bottom of the trench gate.
Optionally, the isolation trench includes a first insulating material layer located on a surface of the trench, a metal layer located inside the first insulating material layer, and a second insulating layer covering the metal layer.
Optionally, the doping concentration of the first inversion layer is not lower than the doping concentration of the drift region.
More optionally, the doping concentration of the first inversion layer is 1E12/cm 3 -1E13/cm 3 。
Optionally, a second inversion layer is arranged in the drift region below the source electrode and/or the drain electrode at intervals.
The application also provides a preparation method of the high-voltage MOS device, which is used for preparing the high-voltage MOS device according to any scheme; in the preparation process, the mask plate used for forming the isolation groove and the mask plate used for forming the source electrode and the drain electrode are the same mask plate.
As described above, the high-voltage MOS device and the method for manufacturing the same of the present application have the following beneficial effects: according to the improved structural design, the plurality of grooves are arranged in the drift region between the source electrode and the drain electrode and the grid electrode at intervals, and the inversion layer is formed on the surface of the drift region between the isolation grooves, so that the electric field distribution of the device is improved, local field intensity peaks are avoided, the breakdown voltage of the device can be improved while the on-resistance of the device is not increased, and the further optimization of the performance of the device is facilitated.
Drawings
Fig. 1 is a schematic cross-sectional view of a high-voltage MOS device according to an embodiment of the present application.
Fig. 2 is a schematic cross-sectional structure of a high-voltage MOS device according to another embodiment of the present application.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. As described in detail in the embodiments of the present application, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. In order to make the illustration as concise as possible, not all structures are labeled in the drawings.
Example 1
As shown in fig. 1, the present embodiment provides a high-voltage MOS device including a substrate 11, a gate electrode, a source electrode 13, a drain electrode 14, a drift region 15, and a plurality of isolation trenches 16. The gate is located on the upper surface of the substrate 11, i.e. the gate is a planar gate structure. The drift regions 15 are located in the substrate 11 and on two sides of the gate, the source electrode 13 and the drain electrode 14 are located in the drift regions 15 on two sides of the gate, a plurality of isolation trenches 16 (more than two isolation trenches 16 are located on two sides of the gate) are arranged in the substrate 11 between the source electrode 13 and the gate and between the drain electrode 14 and the gate at intervals, and a first inversion layer 20 is arranged on the surface of the substrate 11 between adjacent isolation trenches 16.
According to the improved structural design, the plurality of grooves are arranged in the drift region between the source electrode and the drain electrode and the grid electrode at intervals, and the inversion layer is formed on the surface of the drift region between the isolation grooves, so that the electric field distribution of the device is improved, local field intensity peaks are avoided, the breakdown voltage of the device can be improved while the on-resistance of the device is not increased, and the further optimization of the performance of the device is facilitated.
The substrate 11 includes, but is not limited to, wafers of various semiconductor materials such as silicon wafers, germanium wafers, silicon-on-insulator wafers, silicon carbide wafers, and the like. The wafer may be a bare wafer or a wafer with a functional film layer or a transistor or other device structure formed on the surface. For example, in some examples, the substrate 11 includes a silicon wafer and an epitaxial layer formed on the silicon wafer, the epitaxial layer having the same conductivity type as the silicon wafer, e.g., both N-type, but having a lower doping concentration than the substrate 11. If the substrate 11 is a composite structure with an epitaxial layer formed on the surface, the following drift region 15 and isolation trench 16 structures will be formed in the epitaxial layer. The arrangement of the epitaxial layer can adjust the resistivity of the epitaxial layer according to the requirement, and is beneficial to further optimizing the performance of the prepared device, such as improving the breakdown resistance of the device. In a further example, in the case where the epitaxial layer is formed, a buffer layer of the same conductivity type may also be formed between the epitaxial layer and the wafer, the doping concentration of the buffer layer being intermediate between the wafer and the epitaxial layer. The buffer layer is arranged, so that ions of the epitaxial layer can be prevented from diffusing into the wafer, and the electrical performance of the device is ensured.
In the case of a planar gate structure, the gate may extend outwardly to the surface of the drift region 15 until it abuts the isolation trench 16, as shown in fig. 1. The gate electrode includes a gate oxide layer 121, a gate conductive layer 122 and a gate dielectric layer 123 sequentially formed on the surface of the substrate 11. The gate oxide layer 121 is, for example, a silicon oxide layer, which is preferably formed on the surface of the substrate 11 by a thermal oxidation process. The thickness is, for example, 50 angstroms to 200 angstroms. The gate conductive layer 122 may be a polysilicon layer or a gate metal layer, which may be formed by a chemical vapor deposition process. Gate dielectric layer 123 may be a silicon nitride layer or other high K dielectric material layer such as hafnium oxide, zirconium oxide, etc.
In a further example, the high voltage MOS device is further provided with a sidewall structure 19, which sidewall structure 19 extends from the gate side to the surface of the isolation trench 16 adjacent to the gate, and may cover part or all of the surface of the single isolation trench 16.
The sidewall structure 19 may be a single-layer or multi-layer structure, such as a single silicon nitride layer, or include a silicon oxide layer on the side of the gate and a silicon nitride layer on the surface of the silicon oxide layer facing away from the gate. In a preferred example, the sidewall structure 19 includes more than 3 insulating layers sequentially attached along a lateral direction, and the dielectric constants of the insulating layers sequentially increase along a direction away from the gate. The lateral dimensions of the sidewall structures 19 gradually increase from top to bottom. For example, the insulating layer attached to the gate electrode is a silicon oxide layer, and the other two insulating layers are selected from one of the material layers such as a silicon nitride layer, a silicon oxynitride layer, a hafnium oxide layer, an aluminum oxide layer, and a zirconium oxide layer. The sidewall structure 19 formed by the plurality of material layers helps to improve the mechanical strength of the sidewall itself and the isolation performance thereof.
As an example, the number of isolation trenches 16 in each drift region 15 is 2 or more. When the number of isolation trenches 16 is 3 or more, it is preferable that the surfaces of the drift regions 15 of adjacent isolation trenches 16 are each formed with the first inversion layer 20. The dimensions of the drift regions 15 and the dimensions of the isolation trenches 16 may be the same or different. However, in the symmetrical MOS device, the dimensions of each drift region 15 and isolation trench 16 are preferably the same, and accordingly the dimensions and doping concentrations of source 13 and drain 14 are also kept the same, so that source 13 and drain 14 may be used interchangeably. The specific size and number of the isolation trenches 16 are not limited, and the number thereof may be appropriately increased in case of satisfying process permission and device size.
The isolation trench 16 is preferably a narrow top and wide bottom structure. This aids in material filling. The depth of the isolation trench 16 is preferably smaller than the depth of the drift region 15, i.e. the bottom of the isolation trench 16 is spaced from the bottom of the drift region 15. The sides of the isolation trenches 16 are preferably at a distance from the sides of the drift region 15. The isolation trenches 16 of the prior art are filled with an insulating material. For example, the isolation trenches 16 may be filled with a single insulating material such as silicon oxide. In a preferred example provided by the present application, the isolation trench 16 includes a first layer of insulating material on the trench surface, a metal layer on the inside of the first layer of insulating material, and a second insulating layer covering the metal layer. The first insulating material layer is, for example, a silicon oxide layer, which may be formed on the inner surfaces of the trenches by a thermal oxidation process. The inner surface of the silicon oxide layer may further be formed with a silicon nitride layer to enhance its isolation effect, and the metal layer is formed on the inner side of the silicon nitride layer. The metal layer may be the same material layer as the conductive metal layer of the source and drain electrodes 14, for example, an aluminum layer. The second insulating layer may be a metal oxide layer formed by oxidizing or ion-implanting a metal layer, or may be an insulating material layer such as a silicon nitride layer formed by chemical vapor deposition or physical vapor deposition. In other examples, the metal oxide layer formed by oxidizing or ion implanting the metal layer and the silicon nitride layer formed on the surface of the metal oxide layer may be included at the same time, which helps to enhance the adhesion between different film layers and further helps to improve the isolation performance of the isolation trench 16. And filling portions of the metal layer in the isolation trenches 16 helps to adjust the stress distribution of the device, which in subsequent processes such as high temperature annealing and chemical mechanical polishing helps to improve process uniformity and device performance.
The first inversion layer 20 is preferably formed by a doping process having a doping type opposite to that of the drift region 15, e.g., the drift region 15 is P-doped and the first inversion layer 20 isAnd N-type doping. Preferably, the doping concentration of the first inversion layer 20 is not lower than the doping concentration of the drift region 15. In a further example, the doping concentration of the first inversion layer 20 is 1E12/cm 3 -1E13/cm 3 The doping depth of which is smaller than the doping depth of the drift region 15 and preferably smaller than the doping depth and concentration of the source 13 and drain 14.
In a preferred example, the second inversion layer 22 is disposed in the drift region 15 under the source electrode 13 and/or the drain electrode 14 at intervals. That is, the second inversion layer 22 may be provided in the drift region 15 under the source electrode 13, the second inversion layer 22 may be provided in the drift region 15 under the drain electrode 14, or both regions may be provided. The second inversion layer 22 has a pitch in the longitudinal direction with respect to the source 13 and the drain 14. The second inversion layer 22 is spaced from the bottom of the drift region 15 and preferably has a width less than the width of the source 13 and drain 14. The doping concentration of the second inversion layer 22 and the doping concentration of the first inversion layer 20 may be the same or different. The formation of the second inversion layer 22 helps to further improve the electric field distribution of the device and helps to further improve the voltage withstand and reliability of the device.
The high voltage MOS device typically further comprises an extraction electrode 17 for electrically extracting the source 13, the drain 14 and the gate. The extraction electrode 17 may be a metal electrode such as a copper electrode, an aluminum electrode, or a nickel electrode, or may be a nonmetal electrode. To reduce the interfacial contact resistance, the surfaces of the source electrode 13, the drain electrode 14, and the gate electrode may be formed with a metal silicide layer 18, and the metal silicide layer 18 may be formed by high-temperature annealing after depositing the corresponding metal material layers.
The high voltage MOS device is also formed with other structures depending on the type of device that is ultimately fabricated. For example, if a superjunction device, a superjunction structure will also be formed in the substrate 11. The back side of the substrate 11 may also form a drain metal layer. The specific type of the high-voltage MOS device is not limited in this embodiment, and specific structures of different high-voltage MOS devices are well known to those skilled in the art, and the same is not developed.
The high-voltage MOS device provided in this embodiment may be manufactured by a conventional method, for example, a gate is formed on the upper surface of the substrate 11 through processes such as thin film deposition and etching, then an isolation trench 16 is formed in the substrate 11, and then a source-drain structure is formed according to processes such as ion implantation and high-temperature push-well for the gate. Alternatively, the isolation trench 16 and the source/drain structure may be formed first and then the gate may be formed, which is not limited thereto.
Example two
As shown in fig. 2, the present embodiment provides a high-voltage MOS device of another structure. The main difference between the high-voltage MOS device of the present embodiment and the first embodiment is that the high-voltage MOS device of the first embodiment has a planar gate structure, i.e., the gate thereof is formed on the upper surface of the substrate 11. The gate of the high-voltage MOS device of this embodiment is a trench gate, that is, the gate is formed in the substrate 11. This contributes to further reduction in on-resistance of the device and further miniaturization of the device.
Specifically, the trench gate includes a trench, a gate oxide layer 121 formed on the surface of the trench, a gate conductive layer 122 filled inside the gate oxide layer 121 to completely fill the trench, and a gate dielectric layer 123 covering the gate oxide layer 121 and the surface of the gate conductive layer 122. The gate oxide layer 121 is, for example, a silicon oxide layer, and the gate conductive layer 122 is, for example, a polysilicon layer or other gate metal layer. The trench gate is preferably a U-shaped gate. And in a preferred example, the thickness of the gate oxide 121 at the bottom of the trench gate is greater than the thickness of the gate oxide 121 at the sidewalls. For example, in the process of preparing the trench gate, the trench of the trench gate is formed through an etching process, then the trench gate is subjected to bottom filling to form a silicon oxide layer at the bottom, and then the trench is subjected to thermal oxidation to form a silicon oxide layer at the side wall. The trench gate with the structure is beneficial to further improving the pressure resistance of the device.
In a preferred example, the bottom of the trench gate is also provided with a highly doped electric field shielding structure 21. The lateral dimension of the electric field shielding structure 21 is preferably smaller than the lateral dimension of the trench gate, and the depth thereof is preferably smaller than 2 μm, for example, 0.5 μm to 1 μm. The electric field shielding structure 21 is, for example, an aluminum doped region. The formation of the electric field shielding structure 21 helps to further improve the breakdown resistance of the device.
Other structures of the high-voltage MOS device of this embodiment are the same as those of the first embodiment except for the above differences. For example, each of the plurality of drift regions 15 formed on both sides of the gate electrode, the source electrode 13, the drain electrode 14, and the plurality of isolation trenches 16 located in each of the drift regions 15, the first inversion layer 20 formed on the surface of the drift region 15 between adjacent isolation trenches 16, and the like. A second inversion layer 22 may also be formed in the drift region 15 under the source 13 and/or drain 14. For more details, please refer to the foregoing, and the description is omitted for brevity.
The application also provides a preparation method of the high-voltage MOS device, which is used for preparing the high-voltage MOS device in any scheme. The preparation method of the embodiment is characterized in that in the preparation process of the MOS device, the mask plate used in the process of forming the isolation groove and the mask plate used in the process of forming the source electrode and the drain electrode are the same mask plate. The formation of the inversion layer does not add extra mask cost. Besides, the preparation method of other structures is not different from the prior art, for example, a thin film deposition and photoetching process is adopted to form a grid electrode, then isolation grooves are formed on two sides of the grid electrode through the etching and thin film deposition processes, and then a source electrode, a drain electrode, a drift region and a first inversion layer are formed through processes such as ion implantation, high-temperature annealing and the like, or other structures can be formed first and then the grid electrode can be formed. If a trench gate is formed, the isolation trench and the trench of the trench gate may be formed in the same step. The present embodiment is not particularly limited.
In summary, the application provides a high-voltage MOS device and a preparation method thereof. The high-voltage MOS device comprises a substrate, a grid electrode, a source electrode, a drain electrode, a drift region and a plurality of isolation trenches; the grid electrode is positioned in the substrate or on the upper surface of the substrate; the plurality of drift regions are positioned in the substrate and on two sides of the grid, the source electrode and the drain electrode are respectively positioned in the drift regions on two sides of the grid, a plurality of isolation trenches are arranged between the source electrode and the grid and between the drain electrode and the grid at intervals in the substrate, and a first inversion layer is arranged on the surface of the substrate between every two adjacent isolation trenches. According to the improved structural design, the plurality of grooves are arranged in the drift region between the source electrode and the drain electrode and the grid electrode at intervals, and the inversion layer is formed on the surface of the drift region between the isolation grooves, so that the electric field distribution of the device is improved, local field intensity peaks are avoided, the breakdown voltage of the device can be improved while the on-resistance of the device is not increased, and the further optimization of the performance of the device is facilitated. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (9)

1. The high-voltage MOS device is characterized by comprising a substrate, a grid electrode, a source electrode, a drain electrode, a drift region and a plurality of isolation trenches; the grid electrode is positioned in the substrate or on the upper surface of the substrate; the plurality of drift regions are positioned in the substrate and are positioned at two sides of the grid, the source electrode and the drain electrode are respectively positioned in the drift regions at two sides of the grid, a plurality of isolation grooves are arranged between the source electrode and the grid and between the drain electrode and the grid at intervals in the drift regions, a first inversion layer is arranged on the surface of the substrate between adjacent isolation grooves in the same drift region, and the doping type of the first inversion layer is opposite to that of the drift region; the isolation trench comprises a first insulating material layer positioned on the surface of the trench, a metal layer positioned on the inner side of the first insulating material layer and a second insulating layer covering the metal layer, wherein the first insulating material layer comprises a silicon oxide layer and a silicon nitride layer positioned on the inner surface of the silicon oxide layer, the metal layer is formed on the inner side of the silicon nitride layer, and the second insulating layer comprises a metal oxide layer formed by oxidizing or ion implanting the metal layer and a silicon nitride layer formed on the surface of the metal oxide layer.
2. The high voltage MOS device of claim 1, wherein the gate is a planar gate structure, the high voltage MOS device further provided with a sidewall structure extending from a gate side to an isolation trench surface adjacent to the gate.
3. The high-voltage MOS device of claim 2 wherein the sidewall structure comprises more than 3 insulating layers that are sequentially attached in a lateral direction, and wherein the dielectric constants of the insulating layers sequentially increase in a direction away from the gate.
4. The high-voltage MOS device of claim 1 wherein the gate is a trench gate comprising a gate oxide and a gate conductive layer filled inside the gate oxide, wherein the gate oxide at the bottom of the trench gate has a thickness greater than the gate oxide at the sidewalls.
5. The high voltage MOS device of claim 4, wherein a bottom of the trench gate is provided with a highly doped electric field shielding structure.
6. The high voltage MOS device of claim 1, wherein a doping concentration of the first inversion layer is not lower than a doping concentration of the drift region.
7. The high voltage MOS device of claim 6, wherein the doping concentration of the first inversion layer is 1E12/cm 3 -1E13/cm 3 。
8. The high voltage MOS device of claim 1, wherein a second inversion layer is provided in the drift region under the source and/or drain at intervals.
9. A method for manufacturing a high-voltage MOS device, characterized in that the method is used for manufacturing a high-voltage MOS device according to any one of claims 1 to 8; in the preparation process, the mask plate used for forming the isolation groove and the mask plate used for forming the source electrode and the drain electrode are the same mask plate.
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