JPH11238860A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DRAM or a system LSI on which a DRAM is mounted together, which has both stability and rapidity of memory operation. SOLUTION: On the same semiconductor board 1, a selective MISFETQm of a memory cell array region B1 of a DRAM is formed on a main surface of the semiconductor board 1 which is a bulk silicon board and a circuit expecting a memory cell, that is, a MISFET (an n-channel MISFETQn and a p-channel MISFETQp) of a peripheral circuit region B2 of a DRAM or a general circuit region A in which a general circuit such as a logic circuit is formed is formed on an SOI layer 3, which is a single crystalline silicon layer provided on an insulation film 2 on the semiconductor board 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a DRAM (Dynami
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device in which a logic circuit such as a cRandom Access Memory) and a logic control circuit or a logic operation circuit are mounted on a single semiconductor substrate.

[0002]

2. Description of the Related Art A memory cell of a DRAM comprises one cell selection MISFET and one capacitor connected in series to the cell selection MISFET. Therefore, it is relatively easy to increase the degree of integration of the DRAM, and a large-capacity memory element can be configured at low cost. Therefore, DRAM
Are widely used, including the main memory of various computers. In addition, as the miniaturization of elements has progressed and large-scale integration has become possible, a general-purpose circuit such as a logic circuit and a DRAM are integrated on the same semiconductor chip to achieve a higher system performance. (Larg
Demand for e-scale integration is increasing.

Such a highly integrated and high performance DRAM or system LSI is generally formed on the surface of a bulk silicon substrate (single crystal silicon wafer). However, MISFET formed on the surface of bulk silicon substrate
In a bulk MISFET (hereinafter, referred to as a bulk MISFET), a parasitic junction capacitance or the like existing between the source / drain diffusion layer and the substrate becomes a hindrance factor for increasing the operation speed of the bulk MISFET. Further, the effective channel length of the bulk MISFET is set to about 0.
If the size is reduced to 1 μm or less, there are problems such as difficulty in obtaining a bulk MISFET having a high current driving capability.

On the other hand, for example, November 30, 1984
Published by Ohm Co., Ltd., "LSI Handbook",
As described on page 387, the MISFET is
2. Description of the Related Art A technique for forming an I (Silicon On Insulator) substrate is known. A MISFET (hereinafter referred to as a SOIMISFET) formed on an SOI substrate is effective in reducing the parasitic junction capacitance described above, and can increase the speed of the element. Further, a thin SOI layer (a single crystal silicon layer on an insulating layer) is said to be suitable for miniaturization, and is considered promising for realizing high performance of a device.

[0005] The DRAM uses a capacitor for storing charges as an information storage element, and if left as it is, the stored charges leak over time. For this reason, it is well known that a so-called refresh operation for periodically reproducing the stored contents is necessary in order to keep and keep the information. In order to stabilize the refresh operation, it is necessary to improve the retention characteristics of the stored charge, and it is effective to reduce the leakage current between channels of the MISFET for selecting a memory cell. Therefore, the memory cell selection MISFE connected in series to the capacitor
The threshold voltage of T is about 1V and MISFET of peripheral circuit
It is set much higher. This prevents the stored charge from leaking through the memory cell selection MISFET, and enhances the storage retention characteristics.

[0006]

However, in the above-described conventional DRAM and system LSI in which the MISFET is formed on the surface of the bulk silicon substrate, the existence of the parasitic junction capacitance and the like adversely affects the high speed as described above. On the other hand, when a MISFET is formed on an SOI substrate to produce a DRAM or a system LSI, the following problems occur, although the speed is excellent.

In a SOIMISFET, if the channel length is reduced to at least 0.5 μm or less, the thickness of the single-crystal silicon layer formed on the insulating layer must be 0.1 μm or less in order to sufficiently bring out the performance. It is desirable to make the following. Usually, in a SOIMISFET formed on such a thin-film single-crystal silicon layer, the substrate potential, that is, the potential of the single-crystal silicon layer is not fixed.
SOIMISFET with so-called floating substrate
Operates, so that the margin of the SOIMISFET for noise is reduced. In the operation of the DRAM, it is necessary to detect a weak signal from the memory cell and amplify the weak signal.
When an IMISFET is used, it is difficult to secure a stable memory operation.

In the case where polycrystalline silicon, polycide in which a silicide layer is formed on polycrystalline silicon, or polymetal in which a metal layer is formed on polycrystalline silicon is used for a SOIMISFET as a material of a gate electrode,
In general, the conductivity type of polycrystalline silicon is p-type polycrystalline silicon for a p-channel MISFET and n-type polycrystalline silicon for an n-channel MISFET because of the ease of the manufacturing process. However, the work function of the gate electrode is determined by the work function of polycrystalline silicon. The work function of polycrystalline silicon is about 4.15 eV when it is n-type and about 5.15 eV when it is p-type.
15 eV. The difference between the work function of the gate electrode and the work function of the silicon layer constituting the active region is determined by the MISFET.
It is well known that the threshold voltage fluctuates when n-type polycrystalline silicon is used for the gate electrode in the n-channel MISFET and when the p-channel MISFE
When p-type polycrystalline silicon is used for T as the gate electrode, the threshold voltage of the MISFET becomes low, and it becomes difficult to obtain an enhancement mode MISFET.
Vt is selected as the MISFET for selecting the memory cell of the DRAM.
h is about 1 V (select MISFET is n-channel MISFE
The setting of the enhancement mode (in the case of T) is as described in the related art, and the configuration of the gate electrode described above is not preferable as a selection MISFET of a DRAM. On the other hand, a memory cell selection MISFET of a DRAM
Can be considered to increase the concentration of impurities introduced into the channel region of the substrate in order to increase the threshold voltage of the substrate. However, such a measure increases the electric field strength near the storage node and increases the junction leakage. This causes the refresh characteristic to deteriorate.

Further, when the single-crystal silicon layer on the insulating layer is thin, the sheet resistance of the source / drain layers increases,
On the whole, there is a possibility that the high-speed operation of the MISFET is impaired.

An object of the present invention is to provide a technique in a semiconductor integrated circuit device having a DRAM, which is characterized by the high speed of a MISFET on an SOI substrate and is capable of performing a stable memory operation.

Another object of the present invention is to provide a semiconductor integrated circuit device having a DRAM in an SOI device used therein.
An object of the present invention is to provide a technique for improving controllability of a threshold voltage of an IMISFET.

Another object of the present invention is to provide a semiconductor integrated circuit device having a DRAM in which an M
It is an object of the present invention to provide a technique capable of increasing the threshold voltage of an ISFET without increasing the impurity concentration of the substrate.

Another object of the present invention is to provide a technique capable of improving refresh characteristics in a semiconductor integrated circuit device having a DRAM.

Another object of the present invention is to provide a semiconductor integrated circuit device having a DRAM in which
An object of the present invention is to provide a technique for reducing the diffusion layer resistance of an IMISFET.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) The semiconductor integrated circuit device of the present invention
A first MISFET for selecting a memory cell of the RAM;
A semiconductor integrated circuit device including a memory cell array region in which memory cells are arranged in an array and including a second MISFET included in a peripheral circuit of the DRAM, or a logic circuit in addition to the first and second MISFETs A semiconductor integrated circuit device having a third MISFET included in an arithmetic circuit and other logic circuits, comprising: a first MISFET
Are formed on the main surface of the semiconductor substrate, and the second and third M
An ISFET is formed on a single-crystal silicon layer formed on a main surface of an insulating film of a semiconductor substrate so as to be electrically insulated from the semiconductor substrate.

According to such a semiconductor integrated circuit device,
By forming a selection MISFET (first MISFET) constituting a memory cell of a DRAM on the surface of a semiconductor substrate, that is, a bulk silicon substrate, a margin for noise is high, and a stable memory operation can be performed. MISFET (second and third MISFETs)
FET) is formed over a silicon single crystal (SOI) layer provided over an insulating layer over a silicon substrate, whereby a high-speed semiconductor integrated circuit device can be obtained.

(2) In the semiconductor integrated circuit device according to the present invention, the gate electrode of the first MISFET is a polycrystalline silicon film,
A polycrystalline silicon film and a metal silicide film formed on the upper surface thereof, or a polycrystalline silicon film and a metal film formed on the upper surface thereof. Impurities having a conductivity type opposite to the conductivity type of the impurity semiconductor regions forming the source / drain regions of the first MISFET can be introduced into this polycrystalline silicon film at a high concentration. Also,
The gate electrode of the first MISFET may be a metal film having a work function substantially equal to that of intrinsic silicon, for example, tungsten or molybdenum.

As described above, the source of the first MISFET is
Impurities having a conductivity type opposite to the conductivity type of the impurity semiconductor region forming the drain region are introduced into polycrystalline silicon at a high concentration, or the gate electrode of the first MISFET is made substantially equivalent to intrinsic silicon. By using a metal film having a work function, for example, tungsten or molybdenum, the threshold voltage of the first MISFET can be increased toward the enhancement side without increasing the impurity concentration of the channel region.
The refresh characteristics of the DRAM can be improved by reducing the leakage current of the SFET, ie, the MISFET for selecting the DRAM. That is, the first MISFET is an n-channel MI
In the case of an SFET, the gate electrode is made of p-type polysilicon, or the gate electrode is made of a metal film having a work function almost equivalent to that of intrinsic silicon, so that the gate electrode is made of n-type polysilicon. The threshold voltage can be increased to the positive voltage side as compared with the case of crystalline silicon. On the other hand, the first MISFET is a p-channel MI
In the case of an SFET, the gate electrode is made of an n-type polycrystalline silicon or a metal film having a work function substantially equivalent to that of intrinsic silicon, so that the gate electrode is made of a p-type polycrystalline silicon. The threshold voltage can be increased to the negative voltage side as compared with the case of crystalline silicon.

(3) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (1) or (2), wherein the gate electrodes of the second and third MISFETs are made of a polycrystalline silicon film. A polycrystalline silicon film and a metal silicide film formed on the upper surface thereof, or a polycrystalline silicon film and a metal film formed on the upper surface thereof. This polycrystalline silicon film has a second or third M
An impurity having the same conductivity type as that of the impurity semiconductor region forming the source / drain region of the ISFET may be introduced at a high concentration. Also, the second and third MISF
The gate electrode of the ET may be a metal film having a work function substantially equal to that of intrinsic silicon, for example, tungsten or molybdenum. In such a semiconductor integrated circuit device, the gate electrodes of the second and third MISFETs are made of a metal film having a work function substantially equal to that of intrinsic silicon, for example, tungsten or molybdenum, so that the threshold value can be controlled. And the performance of the semiconductor integrated circuit device can be improved. Further, the conductivity type of the impurity introduced into the polycrystalline silicon film is made the same as the conductivity type of the impurity semiconductor region forming the source / drain regions, thereby facilitating the manufacturing process. An MISFET corresponding to driving can be formed. Thereby, the characteristics and reliability of the semiconductor integrated circuit device can be improved. By using a metal (tungsten, molybdenum, or the like) having a work function substantially equal to that of intrinsic silicon for the gate electrodes of the second and third MISFETs, the threshold voltage of the MISFET can be easily set to the enhancement mode. it can.

In the semiconductor integrated circuit device described in the above (1) to (3), the peripheral circuit or the logic circuit
N-channel MISFET and p-channel MISFET
And a circuit mainly composed of a complementary MISFET circuit composed of Also, the second and third MISFETs
May have a selectively formed metal layer or metal silicide layer on the impurity semiconductor region. According to such a semiconductor integrated circuit device, a complementary MISFET
To improve the performance of the semiconductor integrated circuit device, and
By forming a metal layer or a metal silicide layer selectively grown on the impurity semiconductor regions of the second and third MISFETs, it is possible to suppress an increase in the resistance value of the impurity semiconductor regions of the MISFET due to the thin SOI film. . Thereby, the performance of the semiconductor integrated circuit device can be improved comprehensively.

(4) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a first MIS for selecting a memory cell of a DRAM is provided.
A semiconductor integrated circuit device having an FET and a second MISFET arranged around a memory cell array region in which memory cells are arranged in an array and included in a peripheral circuit of a DRAM, or a first and a second MISFET. In addition, the third MIS included in the logical operation circuit and other logical circuits
1. A method of manufacturing a semiconductor integrated circuit device having an FET, comprising: (a) forming an insulating layer on a main surface of a semiconductor substrate, and forming a single-crystal silicon layer electrically insulated from the semiconductor substrate on the insulating layer; (B) removing the single crystal silicon layer and the insulating layer in the memory cell array region and exposing the main surface of the semiconductor substrate; (c) separating the element into the exposed main surface of the semiconductor substrate and the single crystal silicon layer Forming a region,
(D) forming a first MISFET on a main surface of a semiconductor substrate and forming a second and third MISFET on a single crystal silicon layer;
And (e) a step of forming an information storage capacitive element above the first MISFET.
In the step (c), the element isolation region is formed in the single crystal silicon layer by forming a groove reaching the insulating layer in the single crystal silicon layer, depositing an insulating film filling the groove, and forming the groove on the single crystal silicon layer. The method can be performed by any of a method of removing an insulating film and a method of using a selective oxidation (LOCOS) method. According to such a method of manufacturing a semiconductor integrated circuit device, the semiconductor integrated circuit device according to the above (1) can be manufactured.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a sectional view showing an example of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG.
1 is a plan view showing an entire chip of a semiconductor integrated circuit device according to the present embodiment.

As shown in FIG. 2, in the semiconductor integrated circuit device of the present embodiment, a region A where a general circuit such as a logic circuit is formed and a DRAM are formed on the surface of a single semiconductor substrate 1. And a region B. The area B in which the DRAM is formed includes a memory cell array area B1 in which memory cells are formed in an array and a peripheral circuit area B2 in which peripheral circuits of the DRAM are formed. Further, the semiconductor substrate 1 has
It has a plurality of bonding pads P.

In FIG. 1, the left side of the figure shows a cross section of the memory cell array area B1 in which the memory cells of the DRAM are formed, and the right side of the figure shows the peripheral circuit area B2 of the DRAM or a general circuit area A such as a logic circuit. The memory cell array region B1 has a memory cell selection MISFET of a DRAM.
Qm is formed, and n-channel MISFET Qn and p-channel MISFET Qp are formed in peripheral circuit region B2 or general circuit region A. n-channel MISFE
TQn and p-channel MISFET Qp have complementary M
Construct an IS circuit.

Also, as shown in FIG.
m is formed on the main surface of the semiconductor substrate 1 which is a bulk silicon substrate. On the other hand, n-channel MISFET Qn and p-channel MISFET Qp are single-crystal silicon layers formed on insulating film 2 on the main surface of semiconductor substrate 1.
It is formed on the OI layer 3. Thus, the selected MISF
Since the ETQm is formed on the main surface of the semiconductor substrate 1 which is a bulk silicon substrate, the noise resistance of the selected MISFET Qm can be improved, its operation can be stabilized, and the performance of the semiconductor integrated circuit device can be maintained. On the other hand, n-channel MISFET
Since the Qn and p-channel MISFETs Qp are formed on the SOI layer 3, the operation speed of these MISFETs can be improved, and the operation speed of peripheral circuits or general circuits can be improved. As a result, the high-speed response performance of the semiconductor integrated circuit device can be improved and the performance of the semiconductor integrated circuit device can be improved while maintaining the read / write noise resistance performance of the DRAM.

In FIG. 1, a semiconductor substrate 1 is a single crystal silicon substrate doped with an impurity having a p-type conductivity. In the memory cell array region B1 of the semiconductor substrate 1,
p-type well or p-type well and n surrounding it
A mold deep well may be formed. Further, a threshold voltage adjusting layer may be formed in the p-type well.

Peripheral circuit area B2 or general circuit area A
An insulating film 2 is formed on the main surface of the semiconductor substrate 1, and an SOI layer 3 is formed on the insulating film 2. SOI layer 3
Are separated from each other by a separation region 4. That is, the SOI layer 3 is separated and insulated from the semiconductor substrate 1 and the other SOI layers 3 by the insulating film 2 and the separation region 4. Since the SOI layer 3 is thus isolated and in a floating state, the n-channel MISFET Qn and the p-channel MISFET Qp formed on the SOI layer 3
, The speed of the n-channel MISFET Qn and the p-channel MISFET Qp can be increased, and the performance of the semiconductor integrated circuit device can be improved. An isolation region 5 is formed on the main surface of the semiconductor substrate 1 in the memory cell array region B1. The insulating film 2 and the isolation regions 4 and 5 can be, for example, silicon oxide films. The SOI layer 3 is a single-crystal silicon layer as described above. The SOI layer 3 is doped with an impurity corresponding to the channel conductivity type of the MISFET.

The selection MISFET Qm includes a gate electrode 7 formed on the main surface of the semiconductor substrate 1 with a gate insulating film 6 interposed therebetween, and an impurity semiconductor region 8 formed on the main surface of the semiconductor substrate 1 on both sides of the gate electrode 7. Consists of Gate insulating film 6
Is formed of a silicon oxide film having a thickness of, for example, 7 to 8 nm and formed by thermal oxidation. Gate electrode 7 can be, for example, a stacked film of polycrystalline silicon film 7a and tungsten silicide film 7b doped with p-type impurities at a high concentration. Further, an n-type impurity, for example, arsenic or phosphorus is introduced into impurity semiconductor region 8. As described above, the select MISFET Qm is an n-channel type MISFET, and since the gate electrode 7 is formed of the p-type polycrystalline silicon film 7a, the select MISFET Qm
The threshold voltage of the selected MISFET Qm can be increased without increasing the concentration of the impurity introduced into the channel region of m. Thus, the DRAM can be used without increasing the concentration of the channel impurity, that is, without increasing the electric field strength between impurity semiconductor region 8 and the channel.
Refresh characteristics can be improved.

A cap insulating film 9 made of a silicon nitride film is formed on the upper layer of the gate electrode 7 of the selective MISFET Qm, and the upper layer is covered with a silicon nitride film 10. The silicon nitride film 10 is also formed on the side wall of the gate electrode 7, and is used for self-alignment processing when forming a connection hole described later. The gate electrode 7 of the selection MISFET Qm functions as a word line of the DRAM, and a word line WL is formed on the upper surface of the isolation region 5.

On the other hand, the n-channel MISFET Qn
A gate electrode 12 formed on the OI layer 3 and formed via a gate insulating film 11;
And an impurity semiconductor region 13 formed in the I layer 3. The p-channel MISFET Qp is formed on the SOI layer 3 and has a gate electrode 12 formed with a gate insulating film 11 interposed therebetween, and the SOI layer 3 on both sides of the gate electrode 12.
And the impurity semiconductor region 14 formed on the substrate.

Gate insulating film 11, like gate insulating film 6, is formed of a silicon oxide film having a thickness of, for example, 7 to 8 nm and formed by thermal oxidation. Gate electrode 12
Can be, for example, a tungsten film. Further, an n-type impurity such as arsenic or phosphorus is introduced into impurity semiconductor region 13, and a p-type impurity such as boron is introduced into impurity semiconductor region 14. As described above, since the gate electrode 12 is formed of the tungsten film, the n-channel MISFET Qn and the p-channel
The controllability of the threshold voltage of the SFET Qp can be improved. Thereby, the performance of the semiconductor integrated circuit device can be improved. Note that the gate electrode 12 can be a molybdenum film instead of the tungsten film. Such tungsten or molybdenum is a material having substantially the same work function as intrinsic silicon, and the controllability of the threshold voltage is improved by selecting such a material to form the gate electrode 12. . Therefore, the gate electrode 1
The material No. 2 is not limited to tungsten or molybdenum, and may be any material having substantially the same work function as intrinsic silicon. The impurity semiconductor regions 13 and 14 may form a so-called LDD (Lightly Doped Drain) structure.

A cap insulating film 15 made of a silicon nitride film is formed on the gate electrode 12 of the n-channel MISFET Qn and the p-channel MISFET Qp, and a sidewall spacer 16 made of, for example, a silicon nitride film is formed on the side surface. .

The impurity semiconductor regions 13 of the n-channel MISFET Qn and the p-channel MISFET Qp
A tungsten film 17 is formed on the upper surface of the substrate. The tungsten film 17 can be formed by selective growth, and is insulated from the gate electrode 12 by the sidewall spacer 16. As described above, since the tungsten film 17 is formed on the upper surfaces of the impurity semiconductor regions 13 and 14, the thickness of the SOI layer 3 is reduced, and even if the impurity semiconductor regions 13 and 14 are thinned, the resistance is reduced. be able to. Thus, high-speed performance of the elements in the peripheral circuit and the general circuit can be maintained, and a decrease in the performance of the semiconductor integrated circuit device can be prevented.

Select MISFET Qm, n-channel MIS
The FET Qn and the p-channel MISFET Qp are covered with an interlayer insulating film 18. The interlayer insulating film 18 is, for example, an SOG (Spin On Glass) film or a silicon oxide film (hereinafter referred to as a TEOS oxide film) formed by a plasma CVD method using TEOS (tetramethoxysilane) as a source gas.
Can be a TEOS oxide film planarized by a CMP (Chemical Mechanical Polishing) method and a laminated film of the TEOS oxide film.

On the interlayer insulating film 18, the bit line BL and the first layer wiring 19 are formed. Bit line BL and first layer wiring 19 can be, for example, a laminated film of a titanium nitride film and a tungsten film. As a result, the resistance of the bit line BL and the first layer wiring 19 is reduced and the DRA
The performance of M can be improved. Also, the bit line BL
And the first layer wiring 19 are formed simultaneously as described later. Thereby, the process can be simplified.

The bit line BL is connected via a plug 20 to an impurity semiconductor region 8 shared by a pair of select MISFETs Qm.
Connected to. Plug 20 can be, for example, a polycrystalline silicon film into which an n-type impurity has been introduced. A metal silicide film such as a cobalt silicide film may be formed at a connection between the plug 20 and the bit line BL. Thereby, the connection resistance between the plug 20 and the bit line BL can be reduced, and the connection reliability can be improved.

The first layer wiring 19 is connected to the n
Channel MISFET Qn and p channel MISFE
TQp is connected to tungsten film 17 formed on impurity semiconductor regions 13 and 14. The plug 22 can be, for example, a laminated film of a titanium nitride film and a tungsten film. Since the tungsten film 17 is formed between the plug 22 and the impurity semiconductor regions 13 and 14, the connection resistance can be reduced and the connection reliability can be improved.

The bit line BL and the first layer wiring 19 are covered with an interlayer insulating film 23. The interlayer insulating film 23 can be, for example, an SOG film, a TEOS oxide film planarized by a CMP method, or a laminated film of a TEOS oxide film. Note that the bit line BL and the first layer wiring 19 may be covered with a cap insulating film made of a silicon nitride film and a sidewall spacer.

A capacitor C for storing information is formed in the B1 region in the upper layer of the interlayer insulating film 23. An insulating film 24 is formed in the same layer as the capacitor C. Insulating film 2
Numeral 4 may be, for example, a silicon oxide film. By forming the silicon oxide film in the same layer as the capacitor C, it is possible to prevent the occurrence of a step between the B1 region and other regions due to the elevation of the capacitor C. As a result, a sufficient depth of focus can be provided for photolithography, and the process can be stabilized to cope with fine processing. Note that a silicon nitride film may be formed on the upper surface of the interlayer insulating film 23. This silicon nitride film can function as an etching stopper when forming the lower electrode 27 of the capacitor C as described later.

The capacitor C includes a lower electrode 27 connected via a plug 26 to a plug 25 connected to an impurity semiconductor region 8 opposite to the impurity semiconductor region 8 connected to the bit line BL of the select MISFET Qm; For example, a capacitance insulating film 28 made of a silicon nitride film and tantalum oxide
And a plate electrode 29 made of, for example, titanium nitride.

In the upper layer of the capacitor C, for example, TEO
A second layer wiring 31 is formed via an insulating film 30 made of an S oxide film. The second layer wiring 31 can be a laminated film of a titanium film, an aluminum film and a titanium nitride film, for example.

The second layer wiring 31 is connected to the first layer wiring 19 via a plug 32. Also, the second layer wiring 31 is
It is connected to the plate electrode 29 via the plug 33. The plugs 32 and 33 can be a laminated film of an adhesive layer formed of a laminated film of a titanium film and a titanium nitride and a tungsten film formed by a CVD method, for example.

The second layer wiring 31 is covered with an interlayer insulating film 34. A third layer wiring similar to the second layer wiring 31 may be formed on the interlayer insulating film 34. The interlayer insulating film 34
For example, a laminated film of a TEOS oxide film, an SOG film, and a TEOS oxide film can be used.

Next, a method of manufacturing the semiconductor integrated circuit device according to the present embodiment will be described in the order of steps with reference to FIGS.
3 to 18 are sectional views showing an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

First, an insulating film 2 and an SOI layer 3 as a single crystal silicon layer formed on a p-type semiconductor substrate 1
An OI substrate is prepared (FIG. 3).

Next, a photoresist film 35 is formed so as to open the memory cell array region B1 in which the memory cells of the DRAM are formed, and using this photoresist film 35 as a mask, the SOI layer 3 and the insulating film 2 are etched. ,
The main surface of the semiconductor substrate 1 is exposed (FIG. 4). A known dry etching method can be used for the etching.

Next, a shallow groove 36 is formed in the main surface of the semiconductor substrate 1.
Is formed in the SOI layer 3 (FIG. 5). Shallow groove 3
Known photolithography and etching techniques are used for the formation of 6, 37. The shallow groove 37 is formed at a depth where the insulating film 2 is exposed.

Thereafter, the semiconductor substrate 1 is subjected to thermal oxidation to form a silicon oxide film inside the shallow grooves 36 and 37, and then a silicon oxide film 38 is deposited by, for example, a CVD method to fill the shallow grooves 36 and 37 ( (Fig. 6).

Next, the silicon oxide film 38 on the semiconductor substrate 1 and the SOI layer 3 is removed to form isolation regions 4 and 5 (FIG. 7). The method of removing the silicon oxide film 38 is as follows.
Various examples can be given. For example, first, only the silicon oxide film 38 on the SOI layer 3 is subjected to CMP (Chemical Mechanical Polishing).
polishing), and then removing the silicon oxide film 38 on the semiconductor substrate 1 by an etch-back method.
Alternatively, the S surface is polished by the CMP method so that the surfaces thereof match on the semiconductor substrate 1 and the SOI layer 3.
A method of forming a layer for adjusting the etching rate, for example, a silicon nitride film on the silicon oxide film 38 on the OI layer 3 may be used. When the CMP method is used, the shallow grooves 36, 37
A silicon nitride film can be formed on the semiconductor substrate 1 and the SOI layer 3 outside the region, and can function as a polishing stopper layer for polishing by CMP.

At this stage, the semiconductor substrate 1 and the S
A well can be formed in the OI layer 3.

Next, a gate insulating film 6 is formed in the active region of the semiconductor substrate 1 by a thermal oxidation method, and a polycrystalline silicon film doped with a p-type impurity is formed on the entire surface of the semiconductor substrate 1.
A tungsten silicide film and a silicon nitride film are sequentially deposited. Thereafter, using the photoresist film 39 as a mask, the silicon nitride film, the tungsten silicide film, and the polycrystalline silicon film are patterned by using a photolithography technique and an etching technique to form a gate electrode 7 (word line WL) and a cap insulating film 9. (FIG. 8).

Next, a gate insulating film 11 is formed in the active region of the SOI layer 3 by a thermal oxidation method, and a tungsten film and a silicon nitride film are sequentially deposited on the entire surface of the semiconductor substrate 1. After that, using the photoresist film 40 as a mask, the silicon nitride film and the tungsten film are patterned using photolithography technology and etching technology,
The gate electrode 12 and the cap insulating film 15 are formed (FIG. 9).

Next, a photoresist film 41 is formed so as to open a region where the selection MISFET Qm and the n-channel MISFET Qn are formed.
Using n and cap insulating films 9 and 15 as masks, an n-type impurity such as arsenic or phosphorus is introduced by ion implantation to form impurity semiconductor regions 8 and 13 (FIG. 1).
0).

Next, a photoresist film 42 is formed so as to open a region where the p-channel MISFET Qp is formed, and the photoresist film 42 and the cap insulating film 15 are formed.
Using p as a mask, a p-type impurity such as boron is introduced by an ion implantation method to form impurity semiconductor region 14 (FIG. 11).

Next, a silicon nitride film (not shown) is deposited on the entire surface of the semiconductor substrate 1, and a photoresist film 43 is formed only in a region (B1 region) where a memory cell is to be formed.
Thereafter, using the photoresist film 43 as a mask, the silicon nitride film is anisotropically etched to form a silicon nitride film 10 only on the semiconductor substrate 1 in the B1 region and at the same time, a sidewall is formed on the side wall of the gate electrode 7 in the B region. The spacer 16 is formed (FIG. 12). The impurity may be ion-implanted in a self-aligned manner using the sidewall spacer 16 as a mask to form a high-concentration impurity region.

Next, the photoresist film 43 is removed, and S
A tungsten film 17 is formed on the impurity semiconductor regions 13 and 14 on the OI layer 3 by a selective growth method (FIG. 13). When the tungsten film 17 is formed, the tungsten film 17 and the gate electrode 12 are not short-circuited because the sidewall spacers 16 are formed.

Next, an SOG film is applied to the entire surface of the semiconductor substrate 1 and cured at a temperature of about 400 ° C.
Stabilize by performing a heat treatment at about 0 ° C. Further, a TEOS oxide film may be deposited by a plasma CVD method. After that, the SOG film or the TEOS oxide film is polished by the CMP method, and the surface thereof is flattened. Thereby, a step caused by the gate electrode 7 and the cap insulating film 9 is eliminated. After cleaning the surface, a TEOS oxide film may be further deposited to repair damage caused by scratches on the SOG film or the TEOS oxide film caused by the CMP. Thus, the interlayer insulating film 18 is formed.

Further, a connection hole is opened in the interlayer insulating film 18, plug implantation is performed, and then a polycrystalline silicon film doped with impurities is deposited.
Polishing is performed by the MP method to form plugs 20 and 25 (FIG. 14). Note that this connection hole is opened by two-stage etching, so that excessive etching of the semiconductor substrate 1 can be prevented.

Next, the impurity semiconductor regions 13 of the n-channel MISFET Qn and the p-channel MISFET Qp
A connection hole is formed in interlayer insulating film 18 so that tungsten film 17 on 14 is exposed, and for example, a titanium nitride film and a tungsten film are formed on the entire surface of semiconductor substrate 1, that is, on interlayer insulating film 18 including the inside of the connection hole. For example, the film is deposited by a sputtering method, and the titanium nitride film and the tungsten film on the surface of the interlayer insulating film 18 are polished and removed by a CMP method. Thus, the plug 22 made of the titanium nitride film and the tungsten film is formed. Note that the titanium nitride film can be a stacked film of a titanium film and a titanium nitride film.

Next, for example, a titanium nitride film and a tungsten film are sequentially deposited on the entire surface of the semiconductor substrate 1 by, for example, a sputtering method, and this is patterned by photolithography and dry etching to form a bit line BL.
Then, a first layer wiring 19 is formed (FIG. 15).

The bit line BL and the first layer wiring 19
Can be formed of a single-layer tungsten film. By forming the bit line BL and the first layer wiring 19 only with a tungsten film, it is possible to reduce the resistance value in the same sectional area state as compared with the case of a laminated film with a titanium nitride film. This is based on the fact that tungsten has a lower resistivity than titanium nitride. Further, the bit line BL and the first
In the layer wiring 19, for example, a cap insulating film made of a silicon nitride film and a sidewall spacer can be formed.

Next, for example, SO
After a G film is applied and cured at a temperature of about 400 ° C., a TEOS oxide film is deposited by a plasma CVD method. After that, the TEOS oxide film is polished by the CMP method to form the interlayer insulating film 23. As a result, the focus margin in the subsequent photolithography process can be improved, and a fine connection hole can be formed. After cleaning the surface, a TEOS oxide film is further deposited to
The scratch formed by MP may be covered.

Next, a connection hole is opened in the interlayer insulating film 23,
A polycrystalline silicon film doped with impurities is deposited, and this polycrystalline silicon film is polished by a CMP method to form a plug 26.
Is formed (FIG. 16).

Next, an insulating film 24 is deposited on the entire surface of the semiconductor substrate 1. The insulating film 24 can be deposited by plasma CVD, and has a thickness of, for example, 1.2 μm. Note that a silicon nitride film having a thickness of, for example, 200 nm can be formed before the insulating film 24 is deposited. This silicon nitride film can function as an etching stopper for wet etching when exposing the lower electrode 27 later.

Next, a groove is formed in the insulating film 24 in a region where the capacitor C is formed, and the plug 26 is exposed. Next, a polycrystalline silicon film covering the trench is deposited on the entire surface of the semiconductor substrate 1, and a silicon oxide film is further deposited on the entire surface of the semiconductor substrate 1. The polycrystalline silicon film can be doped with phosphorus, and its thickness can be 0.03 μm. Since the thickness of the polycrystalline silicon film is sufficiently small with respect to the dimension of the groove, the polycrystalline silicon film is deposited inside the groove with good step coverage. The silicon oxide film is deposited so as to be embedded in the trench. In consideration of the embedding property in the trench, the silicon oxide film is an SOG film or a TOG film.
A silicon oxide film formed by a CVD method using EOS can be used.

Next, the silicon oxide film and the polycrystalline silicon film on the insulating film 24 are removed, the lower electrode 27 of the capacitor C is formed, and wet etching is performed using the photoresist film as a mask to form a memory cell array region (B1 The insulating film 24 (in the region) and the silicon oxide film are removed (FIG. 17). Thereby, the lower electrode 27 is exposed.

The edge portion of the insulating film 24 is not strictly sharp as shown in the figure because it is etched by wet etching, but is shown sharply (at right angles) for simplicity.

Next, after nitriding or oxynitriding the surface of the lower electrode 27, a tantalum oxide film is deposited. The tantalum oxide film can be deposited by, for example, a CVD method using an organic tantalum gas as a raw material.

Further, a titanium nitride film is deposited by, for example, a CVD method. Thereafter, the titanium nitride film and the polycrystalline tantalum oxide film are patterned using a photoresist film to form a capacitance insulating film 28 and a plate electrode 29 (FIG. 18). Thus, the capacitor C including the lower electrode 27, the capacitor insulating film 28, and the plate electrode 29 is formed.

After that, a TEOS oxide film is deposited on the entire surface of the semiconductor substrate 1 to form an insulating film 30, openings are formed in the insulating film 30, and plugs 32 and 33 are formed. Plug 32, 3
3 is formed by depositing a laminated film of titanium and titanium nitride on the entire surface of the semiconductor substrate, further depositing a tungsten film by, for example, a blanket CVD method, and then etching back the tungsten film, the titanium nitride film, and the titanium film. be able to. Note that titanium and titanium nitride can be formed by a sputtering method.
It can also be formed by a CVD method. Further, a titanium film, an aluminum film, and a titanium nitride film are deposited on the entire surface of the semiconductor substrate 1 by a sputtering method, and are patterned to form the second layer wiring 31. Thus, the semiconductor integrated circuit device shown in FIG. 1 is almost completed.

Further, a TEOS oxide film, an SOG film, and a TEOS oxide film may be deposited to form an interlayer insulating film, and a third layer wiring may be formed in the same manner as the second layer wiring 31.

According to the semiconductor integrated circuit device of the present embodiment, the selection MISFET Qm is formed on the semiconductor substrate 1 which is a bulk substrate, and the n-channel MISFET Qn and the p-channel MISFET Qp of the peripheral circuit or general circuit are formed.
Is formed on the SOI layer 3, so that D having excellent noise resistance is formed.
In addition to configuring the RAM, the response speed of the peripheral circuit or the general circuit can be improved to improve the performance of the semiconductor integrated circuit device. In addition, since the gate electrode 7 of the selected MISFET Qm is formed of a polycrystalline silicon film in which a p-type impurity opposite to the conductivity type of the selected MISFET Qm is introduced at a high concentration, the leakage current can be increased without increasing the concentration of the channel impurity of the selected MISFET Qm. Can be reduced. Thereby, DRAM
Refresh characteristics can be improved. Also, n channel M
By making the gate electrodes 12 of the ISFET Qn and the p-channel MISFET Qp a tungsten film, the controllability of the threshold voltage can be improved. Further, an n-channel MISFET Qn and a p-channel MISFET Qp
Film 17 on impurity semiconductor regions 13 and 14 of FIG.
Is formed, the resistance of the n-channel MISFET Qn and the p-channel MISFET Qp formed on the SOI layer 3 due to the thinning of the impurity semiconductor regions 13 and 14 can be prevented, and the performance can be improved.

In this embodiment, the case where a laminated film of a polycrystalline silicon film and a tungsten silicide film is used for the gate electrode 7 has been exemplified. However, a single-layer polycrystalline silicon film, or a polycrystalline silicon film and a metal A film, for example, a laminated film of a polycrystalline silicon film, a titanium nitride film, and a tungsten film can also be used.

The selection MISFET Qm may be a p-channel MISFET. In this case, the polycrystalline silicon film is heavily doped with n-type impurities. Also in this case, the leakage current can be reduced by increasing the threshold voltage to the negative voltage side without increasing the concentration of the channel impurity.

In the present embodiment, the gate electrode 12
Although an example using a tungsten film is shown, a single-layer polycrystalline silicon film, a laminated film of a polycrystalline silicon film and a metal silicide film, or a laminated film of a polycrystalline silicon film and a metal film may be used. it can. In this case, the n-channel MISF
The conductivity type of the impurity semiconductor regions 13 and 14 of the ETQn and the p-channel MISFET Qp can be the same as the conductivity type of the polycrystalline silicon film. Thereby, the n-channel MISFET Qn and the p-channel MISFET Qp
And a high-performance semiconductor integrated circuit device corresponding to low-voltage driving can be configured.

In this embodiment, the tungsten film 1
7, the metal may be a metal other than tungsten, for example, titanium or cobalt, or a metal silicide film, for example, a tungsten silicide film, a titanium silicide film, a cobalt silicide film, or the like.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the present embodiment, the circuits other than the memory cells of the DRAM, that is, the peripheral circuits or general circuits are composed of the n-channel MISFET Qn and the p-channel MIS
This is applied to the case of a complementary MIS circuit including the FET Qp, but is not limited thereto.
Various changes can be made without departing from the scope of the invention. For example, a bipolar transistor or a JFET (Junc)
tion Field Effect Transistor) or general IG
The present invention is also applicable to a case including an active element such as an FET (Insulated Gate Field Effect Transistor) and a passive element such as a resistor and a capacitor. In the present embodiment, the bulk M
Although the ISFET is applied only to the memory cell array region B1, it can be applied to a part of other circuits, for example, a sense amplifier. Further, the structure of the memory cell of the DRAM is not limited to the structure shown in the present embodiment, but can be variously changed without departing from the gist thereof. The material of the lower electrode 27, the capacitor insulating film 28, the plate electrode 29, the first layer wiring 19, the second layer wiring 31 metal, or various insulating films is limited to the materials described in this embodiment. Instead, it can be changed without departing from the gist of the invention. Further, the conductivity type of the single-crystal silicon substrate, the impurity semiconductor region formed therein, or the polycrystalline silicon is not limited to the case of the present embodiment, and may be set to the opposite conductivity type without departing from the gist thereof. You may.

[0082]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) In a semiconductor integrated circuit device having a DRAM, a MISFET on an SOI substrate is characterized by high speed, and a stable memory operation is possible.

(2) In a semiconductor integrated circuit device having a DRAM, the controllability of the threshold voltage of the SOIMISFET used therein can be improved.

(3) In a semiconductor integrated circuit device having a DRAM, the threshold voltage can be increased without increasing the impurity concentration of the substrate of the memory cell selecting MISFET.

(4) In a semiconductor integrated circuit device having a DRAM, refresh characteristics can be improved.

(5) In a semiconductor integrated circuit device having a DRAM, the diffusion layer resistance of a SOIMISFET used therein can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a plan view showing an entire chip of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 5 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 7 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 8 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 9 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 10 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 11 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 12 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 13 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 14 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 15 is a sectional view illustrating an example of a method of manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention in the order of steps.

FIG. 16 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 17 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 18 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 SOI layer 4, 5 Isolation region 6 Gate insulating film 7 Gate electrode 7a Polycrystalline silicon film 7b Tungsten silicide film 8 Impurity semiconductor region 9 Cap insulating film 10 Silicon nitride film 11 Gate insulating film 12 Gate electrode 13 , 14 impurity semiconductor region 15 cap insulating film 16 sidewall spacer 17 tungsten film 18 interlayer insulating film 19 first layer wiring 20, 22 plug 23 interlayer insulating film 24 insulating film 25, 26 plug 27 lower electrode 28 capacitance insulating film 29 plate electrode Reference Signs List 30 insulating film 31 second layer wiring 32, 33 plug 34 interlayer insulating film 35 photoresist film 36 shallow groove 37 shallow groove 38 silicon oxide film 39-43 photoresist film A general circuit area B1 memory cell array area B2 peripheral circuit area BL bit Line Capacitor P bonding pad Qm select MISFET Qn n-channel MISFET Qp p-channel MISFET WL the word line

Claims (12)

[Claims] A first MISFET for selecting a memory cell of a DRAM; and a memory cell array region in which the memory cells are arranged in an array.
A semiconductor integrated circuit device having a second MISFET included in a peripheral circuit of M and the first and second M
A semiconductor integrated circuit device having a third MISFET included in a logical operation circuit and other logic circuits in addition to an ISFET, wherein the first MISFET is formed on a main surface of the semiconductor substrate, and 3. The semiconductor integrated circuit device according to claim 3, wherein the MISFET is formed on a single-crystal silicon layer formed on the insulating film on the main surface of the semiconductor substrate so as to be electrically insulated from the semiconductor substrate. 2. The semiconductor integrated circuit device according to claim 1, wherein the gate electrode of the first MISFET is a polycrystalline silicon film, a polycrystalline silicon film and a metal silicide film formed on the upper surface thereof, or A semiconductor integrated circuit device comprising a polycrystalline silicon film and a metal film formed on an upper surface thereof. 3. The semiconductor integrated circuit device according to claim 2, wherein the polycrystalline silicon film has a conductivity opposite to a conductivity type of an impurity semiconductor region forming a source / drain region of the first MISFET. A semiconductor integrated circuit device, characterized in that impurities indicating a mold are introduced at a high concentration. 4. The semiconductor integrated circuit according to claim 1, wherein a gate electrode of said first MISFET is made of a metal film having a work function substantially equal to that of intrinsic silicon. apparatus. 5. The semiconductor integrated circuit device according to claim 1, wherein the gate electrodes of the second and third MISFETs are a polycrystalline silicon film, a polycrystalline silicon film, and a polycrystalline silicon film. A semiconductor integrated circuit device comprising a metal silicide film formed on an upper surface, or a polycrystalline silicon film and a metal film formed on the upper surface thereof. 6. The semiconductor integrated circuit device according to claim 5, wherein the second or third MI is provided on the polycrystalline silicon film.
A semiconductor integrated circuit device, wherein an impurity having the same conductivity type as that of an impurity semiconductor region forming a source / drain region of an SFET is introduced at a high concentration. 7. The semiconductor integrated circuit device according to claim 1, wherein a gate electrode of said second and third MISFETs has a work function substantially equal to that of intrinsic silicon. A semiconductor integrated circuit device comprising a film. 8. The semiconductor integrated circuit device according to claim 4, wherein a material forming said metal film is tungsten or molybdenum. 9. The semiconductor integrated circuit device according to claim 1, wherein said peripheral circuit or logic circuit is an n-channel MISFE.
Complementary MIS composed of T and p channel MISFETs
A semiconductor integrated circuit device comprising a circuit mainly composed of an FET circuit. 10. The semiconductor integrated circuit device according to claim 1, wherein a source / drain region of said second and third MISFETs is selectively formed on an impurity semiconductor region. A semiconductor integrated circuit device having a metal layer or a metal silicide layer formed in a uniform manner. 11. A first method for selecting a memory cell of a DRAM.
MISFET and the memory cell array region where the memory cells are arranged in an array.
A semiconductor integrated circuit device having a second MISFET included in a peripheral circuit of the AM, or a semiconductor integrated circuit having a third MISFET included in a logic operation circuit or another logic circuit in addition to the first and second MISFETs A method for manufacturing a circuit device, comprising: (a) forming an insulating layer on a main surface of a semiconductor substrate, and forming a single-crystal silicon layer on the insulating layer, the single crystal silicon layer being electrically insulated from the semiconductor substrate; b) removing the single-crystal silicon layer and the insulating layer in the memory cell array region to expose a main surface of the semiconductor substrate; and (c) adding an element to the exposed main surface of the semiconductor substrate and the single-crystal silicon layer. Forming an isolation region; (d) forming the first MISFET on a main surface of the semiconductor substrate;
And forming the second and third layers on the single-crystal silicon layer.
Forming a MISFET, and (e) forming an information storage capacitive element above the first MISFET. A method of manufacturing a semiconductor integrated circuit device, comprising: 12. The method for manufacturing a semiconductor integrated circuit device according to claim 11, wherein forming the element isolation region in the single crystal silicon layer in the step (c) comprises forming a groove reaching the insulating layer into the single crystal silicon layer. A first method of depositing an insulating film filling the trench after forming the crystalline silicon layer and removing the insulating film on the single crystal silicon layer, or a second method using a selective oxidation (LOCOS) method And a method of manufacturing a semiconductor integrated circuit device.