JPH0750745B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a configuration of a capacitance forming section in a semiconductor device, and more particularly to a semiconductor device suitable for a highly integrated semiconductor memory device.

[Background of the Invention]

In recent years, in highly integrated dynamic random access memory (DRAM), destruction of memory cell information (soft error) due to external noise such as α rays has become a problem. For example, in the DRAM memory cell shown in FIG. 2, signals are stored in the capacitor 24 as electric charges. Here, 21 is a bit line, 22 is a word line, and 23 is a transfer line.
It is MOS.

However, the capacity of the capacitor 24 also decreases as the memory cell area decreases due to higher integration. Therefore, in order to secure the ratio of signal charge to noise charge (S / N ratio) with respect to external noise, it is necessary to make a capacitor having a small area and a high capacitance value.

Therefore, as described in Japanese Patent Publication No. 58-12739, conventionally, as shown in FIG. 3, a groove is deeply formed in the substrate 1 and the inside of the groove is filled with a polycrystalline silicon layer 31 through a thin insulating film 3. Further, the polycrystalline silicon portion 31 is set to a high potential to form a channel 32 on the outside of the in-groove oxide film 3, and the drain 9 of the field effect transistor portion and the outside of the in-groove oxide film 3 are electrically connected to each other. A capacitor is formed by the inner polycrystalline silicon 31, the oxide film 3 in the groove, and the channel 32 outside the oxide film in the groove, and the capacitance value added to the drain 9 of the field effect transistor portion is increased by utilizing the capacitor.

However, in this structure, since the channel 32 is formed on the outer peripheral surface of the groove, the drain 9 of the field effect transistor portion is formed.
Is equivalent to extending deeply into the groove, and the carrier generated in the substrate due to α rays etc. easily reaches the channel 32 outside the groove forming the capacitor after diffusion,
Since it is absorbed, the groove itself acts as an antenna for collecting carriers (electrons or holes) generated by α rays, and there is a problem that the strength against soft error does not increase as the capacitance value increases. In FIG. 3, 2 is an oxide film for element isolation, 10 is a source, P is a capacitor portion, and Q is an element isolation region.

Also, in this structure, as shown in FIG. 4, when two groove type capacitors are brought close to each other and the drain 9'is set to a high potential and 9 is set to a low potential, channels 32, 32 'are formed on the substrate side surface of the groove. Therefore, the two groove type capacitor parts P and P ′ are
It operates as an insulated gate field effect transistor having a source (P) and a drain (P ') having the same depth as the groove and using the element isolation oxide film 2 as a gate oxide film.
For this reason, if the two groove type capacitor parts P and P ′ are brought close to each other, a leak current corresponding to a punch through current is generated between them.
41 flows. This current causes the disappearance of the signal charges stored in the groove type capacitor parts P and P ', so that there is a problem in forming the groove type capacitor at a high density.

Furthermore, “An Isolation Merged Vertical Capacitor Cell” by IE Day, Technical Digest, 240 (1984), Shigeru Nakamura, etc. Isolation-Merged
The thin capacitor discussed in the literature entitled "Vertical Capacitor Cell") adopts the structure shown in Fig. 8 in order to avoid leakage current and achieve higher integration. , 92 is polycrystalline silicon, 91 is an oxide film,
Further, 56 represents a gate oxide film.

However, even in this structure, when the storage node of the memory cell, that is, the drain 9 of the field effect transistor and the polycrystalline silicon layer 90 electrically connected to the storage node have a high potential, the outside of the trench oxide film 3 is exposed. The problem that a channel is easily formed on the side surface has not been solved, and it has not been a fundamental solution to the above problem.

[Object of the Invention]

The object of the present invention is to address the above-mentioned problems of the prior art,
It is an object of the present invention to provide a semiconductor device for a semiconductor memory, which has a large tolerance to external noise due to α rays and the like, can sufficiently suppress the occurrence of soft errors, and can be highly integrated.

[Outline of Invention]

In order to achieve this object, the present invention enables a conductive layer serving as an outer electrode forming a capacitor in a groove to be kept at the same potential as that of a semiconductor substrate, so that a storage node portion of a memory cell is changed from a ground potential to a power supply potential. It is characterized in that the formation of a channel does not occur outside the trench oxide film at any potential in between.

Example of Invention

Hereinafter, the semiconductor device according to the present invention will be described in detail with reference to the illustrated embodiments.

FIG. 1 shows one embodiment of the present invention, in which the first insulating film 3, the first polycrystalline semiconductor layer 4, the second insulating film 5, and the second insulating film 5 are formed on the inner surface of the groove formed on the surface of the semiconductor substrate 1. By stacking the polycrystalline semiconductor layers 6 in this order, a capacitor is formed between the first polycrystalline semiconductor layer 4 and the second polycrystalline semiconductor layer 6, and the first insulating film 3 surrounds the capacitor. The structure.
Further, in order to make the first polycrystalline semiconductor layer 4 have the same potential as the substrate, the groove bottom portion of the first insulating film 3 is partially removed to electrically connect the first polycrystalline semiconductor layer 4 and the substrate 1 to each other. And a window 7 is opened in the insulating layer on the drain 9 of the field effect transistor which is the signal storage node portion to electrically connect the second polycrystalline semiconductor layer 6 and the drain 9.

Therefore, according to this embodiment, most of the polycrystalline semiconductor layers 4 and 6 constituting the capacitor have the insulating film 3 between them and the substrate 1 sandwiching the insulating film 3. Since the polycrystalline semiconductor layer 4 has the same potential, no channel is formed outside this insulating film. For this reason, the carrier generated in the substrate 1 due to external noise such as α rays diffuses in the substrate and approaches the groove type capacitor portion, but since the insulating film 3 makes it difficult, the charge of the capacitor is reduced. It cannot reach the polycrystalline semiconductor layer 4, which is the storage portion, and does not affect the signal charge of the capacitor. For this reason, the capacitor can be formed strongly against external noise due to α rays and the like.

Further, the advantage of the groove type capacitor in which no channel is formed outside the groove is that there is no interference between groove capacitors because there is no leak current path between adjacent grooves.

Therefore, according to this embodiment, even if the groove type capacitors are formed close to each other with a high density, interference between the signals of the capacitors as in the conventional example described in FIG. It is advantageous for high density.

By the way, the embodiment shown in FIG. 1 was manufactured as follows.

First, as shown in FIG. 5a, a thermal oxide film is formed on the P-type semiconductor substrate 1.
51 is formed to a thickness of 200Å, and then a thick oxide film 2 having a thickness of 4000Å intended for element isolation is formed at a desired portion by a selective oxidation method using a silicon nitride film. Thereafter, a silicon nitride film 52 is newly deposited on the surface to a thickness of 200Å, and a hole 53 is formed in a desired capacitor forming portion of the silicon nitride film. Next, as shown in FIG. 5b, the surface oxide film 51 and the silicon substrate 1 are etched by anisotropic silicon dry etching or ion milling using the silicon nitride film 52 as a mask to a depth of 4 μm. To form the groove 54.
Then, a thermal oxidation method is used to form an oxide film 3 in the groove having a thickness of 200Å. Next, as shown in FIG. 5c, the oxide film 3 at the bottom of the groove is removed by anisotropic dry etching of the oxide film. At this time, the oxide film 3 other than the groove forming portion is not etched because it is covered with the silicon nitride film 52, and the oxide film 3 on the groove side surface is also not removed because of anisotropic dry etching. Thereafter, the silicon nitride film 52 is removed by etching, and a P-type doped polycrystalline silicon layer 4 is laminated to a thickness of 2000 Å. Then, as shown in FIG. 5d, an etching process is performed by anisotropic silicon dry etching to leave the polycrystalline silicon on the side surfaces of the groove and remove the polycrystalline silicon on other portions.
Next, as shown in FIG. 5e, a high dielectric constant three-layer insulating film 5 consisting of three layers of a silicon oxide film 50Å, a silicon nitride film 200Å, and a silicon oxide film 100Å is laminated, and later formed into a desired shape together with a thermal oxide film 51. Etching processing. Next, an N-type doped polycrystalline silicon layer 6 is laminated in a thickness of 3000 Å to fill the groove, and is subsequently etched into a desired shape. However, at this time, processing is performed so that a part of the polycrystalline silicon layer 6 directly forms a part 55 that is directly connected to the main surface of the silicon substrate 1. Next, as shown in Fig. 5f, a 200 Å-thick gate oxide film 56 is formed by thermal oxidation, a polycrystalline silicon layer is laminated thereon to a 2000 Å thickness, and then this polycrystalline silicon layer is layered. A gate electrode 8 is formed by doping N type having a value of 19Ω and etching. At this time, an N-type diffusion layer 57 is formed by the impurities diffused from the N-type polycrystalline silicon layer 6 toward the substrate from the portion where the polycrystalline silicon 6 is connected to the silicon substrate 1. Next, as shown in FIG. 5g, arsenic ions are implanted from the surface side of the silicon substrate 1 through the oxide film by an ion implantation method at an area density of 5 × 10 ¹⁵ cm ⁻² and an acceleration energy of 80 KeV, and then heat treated. A diffusion layer serving as the drain 9 and the source 10 of the field effect transistor is formed. At this time, the N-type diffusion layer 57 and the drain 9 are connected, and the semiconductor device of FIG. 1 is obtained here.

Next, FIG. 6 shows another embodiment of the present invention. This embodiment is different from the embodiment of FIG. 1 in that the P-type high concentration layer 61 is formed at the bottom of the groove.
Is formed. In order to obtain the semiconductor device according to the embodiment shown in FIG. 6, in the step shown in FIG. 5b among the steps shown in FIGS. 5a to 5g, the ion implantation method is used and 1 × 10 1 of boron ions are used. 30 Ke at an areal density of ¹³ cm ^-2
Implantation is performed under the acceleration energy of V to form the P-type high-concentration layer 61, and thereafter, it may be manufactured by the same method as the embodiment of FIG.

According to this embodiment, if the in-groove polycrystalline silicon 6 is of N-type conductivity and the substrate 1 is of P-type conductivity, the band diagram between FIG. 6A and FIG. 6A is as shown in FIG. With respect to the electrons of, the potential barrier g due to the concentration difference between the high concentration layer 61 and the substrate 1
Is formed. Then, the electrons generated in the substrate due to the external noise cannot cross the potential barrier. Therefore, by covering the bottom of the groove with the P-type high-concentration layer 61 as in this embodiment, it is possible to further improve the performance against external noise.

Next, FIGS. 7a to 7h show still another embodiment of the present invention and its manufacturing method. In this example, first, as shown in FIG. 7a, a thermal oxide film 83 of 200 Å was formed on the surface of the P-type semiconductor substrate 1, and then boron ions were implanted at an areal density of 1 × 10 ¹⁴ cm ^-2 and an acceleration energy of 80 KeV. By annealing in a nitrogen atmosphere at 1000 ° C. for about 30 minutes, boron is activated and the high concentration P-type semiconductor layer 82 is formed. Thereafter, as shown in FIG. 7b, a low concentration P-type epitaxial layer 81 is formed on the high concentration P-type semiconductor layer 82.
Is formed to 3 μm. Next, a thermal oxide film 51 is formed on the epitaxial layer 81 with a thickness of 200Å. Next, as shown in FIG. 7c, a thick oxide film 2 with a thickness of 4000 Å for the purpose of element isolation is formed at a desired portion by a selective oxidation method using a silicon nitride film, and then a new oxide film is formed on the surface. A silicon nitride film 52 having a thickness of 1000 Å is formed on the substrate, and a hole 53 is formed in a desired capacitor forming portion of the silicon nitride film 52. Next, as shown in FIG. 7d, the surface oxide film 51 and the epitaxial region layer 81 are etched by anisotropic dry etching using the silicon nitride film 52 as a mask to form a groove 54 having a depth of 3 μm. Processing is performed so that the bottom is located in the high-concentration P-type semiconductor layer 82. Then, the oxide film 3 having a thickness of 180 Å is formed by using the thermal oxidation method. Next, as shown in FIG. 7e, only the oxide film at the bottom of the groove is removed by anisotropic dry etching using the silicon nitride film 52 as a mask. Then, the silicon nitride film used as the mask is completely removed by etching, and then a P-type doped polycrystalline silicon layer 4 is laminated by 2000 Å. Next, the gate electrode 8 is processed by using anisotropic dry etching.
At this time, since the dry etching resistant resist mask 84 for forming the gate electrode remains inside the groove, the polycrystalline silicon at the bottom of the groove is not etched, and the state after removing the resist is as shown in FIG. 7f. Next, as shown in FIG. 7g, a tantalum oxide film as a high-dielectric-constant insulating film 85 is laminated in 200 liters. Then, the surface density of the arsenic ions is 5 × 15 ^{15 at the} desired part by the ion implantation method from the surface side.
The source 10 and the drain 9 of the field effect transistor are formed by the subsequent heat treatment by implanting with cm ⁻² and the implantation energy of 80 KeV. Next, as shown in FIG. 7h, a contact hole 86 is etched in the insulating films 85 and 51. Then, the N-type doped polycrystalline silicon layer 6 is deposited to a thickness of 3000Å to fill the groove, and then the polycrystalline silicon layer 6 is etched into a desired shape to obtain a semiconductor device.

According to the embodiment shown in FIG. 7h, the oxide film 3 in the groove and the gate oxide film of the field effect transistor are formed in the same step, and the polycrystalline silicon layer 4 and the gate 8 of the field effect transistor are formed in the same step. By doing so, simplification of the process can be obtained.

Further, according to this embodiment, the area of the capacitance forming portion can be increased by extending the polycrystalline silicon layer 6 onto the gate electrode of the field effect transistor.

Further, according to this embodiment, the groove type capacitor has an epitaxial layer 81 having a high-concentration buried layer 82 of the same conductivity type as the substrate.
By connecting the bottom of the groove to the high-concentration layer 82, the potential of the high-concentration layer is fixed to the ground, and the potential of the polycrystalline silicon 4 on the ground potential side of the capacitor is stabilized.

〔The invention's effect〕

As described above, according to the present invention, a groove type capacitor using a two-layer structure of a polycrystalline semiconductor, and the capacitor portion is wrapped with an insulating film from the side surface, and the potentials of the semiconductor layers inside and outside the insulating film are made the same. Since the channel is not formed on the outer surface of this insulating film, the problems of the conventional technology can be addressed, and the carriers generated in the substrate due to α rays etc. can be prevented from diffusing and entering the capacitor part, This has the effect of improving the reliability of the signal and reducing the influence of external noise. Further, since the channel is not formed on the outer peripheral surface of the groove in this way, mutual interference such as leakage current between capacitors when the groove type capacitor is formed with high density can be eliminated, and the groove type capacitor can be formed with high density. There is an effect that can be formed.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a circuit diagram showing an example of a memory cell to which the present invention is applied, and FIG. 3 is a sectional view showing a conventional example of a semiconductor device. ,
FIG. 4 is a sectional view for explaining a problem in the conventional example, FIGS. 5a to 5g are sectional views showing a manufacturing process of an embodiment of the present invention, and FIG. 6 is another embodiment of the present invention. 7a to 7h are sectional views showing a manufacturing process of still another embodiment of the present invention, FIG. 8 is a sectional view showing another conventional example of a semiconductor device, and FIG. FIG. 3 is an explanatory diagram of a band structure in one embodiment of the present invention. 1 ... Semiconductor substrate, 2 ... Oxide film for element isolation, 3 ...
1st insulating film, 4 ... 1st polycrystalline semiconductor layer, 5 ... 2nd insulating film, 6 ... 2nd polycrystalline semiconductor layer, 7 ... window
8 ... Gate, 9 ... Drain, 10 ... Source, O ...
Field effect transistor part, P ... Groove type capacitor part, Q
...... Element isolation area section.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Takahiro Nagano 4026 Kuji Town, Hitachi City, Ibaraki Prefecture, Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-58-213460 (JP, A) JP-A-53 -121480 (JP, A) JP-A-59-141262 (JP, A) JP-A-59-191373 (JP, A) JP-A-59-191374 (JP, A)

Claims (3)

[Claims] 1. A semiconductor device comprising an electrostatic capacity having an inner wall surface of a groove formed on a main surface of a semiconductor substrate as an electrode supporting surface, wherein the electrostatic capacity is a charge storage capacity for signal storage. A first insulator layer formed on the wall surface except at least a part of its bottom, and a semiconductor layer formed on the surface of the first insulator layer and forming the semiconductor substrate at the bottom of the groove. A first conductor layer formed so as to be in direct contact with a second insulating layer formed from the bottom surface of the groove to the main surface of the semiconductor substrate while covering the surface of the first conductor layer. A body layer and a second conductor layer formed by reaching the signal storage node formed on the main surface of the semiconductor substrate from the surface of the second insulator layer, and the first conductor layer Since the bottom of the first conductor layer is in contact with the semiconductor substrate, the first conductor layer is The voltage is maintained at a predetermined constant voltage equal to or lower than the maximum threshold voltage that causes a channel between the first insulating layer and the semiconductor substrate, and in this state, the second conductive layer is charged. A semiconductor device characterized by being configured to perform storage. 2. The semiconductor layer according to claim 1, wherein the semiconductor layer of the semiconductor substrate which is in direct contact with the first conductor layer at the bottom of the groove is formed as a high-concentration diffusion layer. Semiconductor device. 3. A semiconductor device according to claim 1, wherein the semiconductor substrate has an epitaxial growth layer, and the groove is formed in the epitaxial growth layer.