JPS5856266B2 - MOS memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS memory cell, and in particular to an N-channel silicon gate MO with increased storage capacity.
8 RAM cells.

Single-transistor type semiconductor memory cells are widely used in N-channel silico-1 MO8 RAM devices and are disclosed in U.S. Pat.
No. 648,594, filed January 19, 1976 by Kitagawa and McAl
U.S. Application No. 682,687, filed May 3, White and McAdams.
) and Redwine, U.S. Application No. 691.735, filed June 1, 1976.

The rights to all of these inventions have been assigned to Texas Iso Instruments.

Also, Electronics Magazine (USA) September 13, 1973
It is also stated on pages 116 to 121 of the Japanese issue, pages 116 to 121 of the February 19, 1976 issue, and pages 81 to 86 of the May 13, 1976 issue.

The most widely manufactured devices of this type contain 4096 bits or 212 bits and are referred to in the industry as 4KRAMJs, but most recently have been called 16KRAMJs with 16384 bits.
is being manufactured.

Currently, most of the manufacturing costs of semiconductor devices are spent on bonding, packaging inspection, intermediate handling, etc., rather than the cost of creating the actual circuitry inside the small silicon chip. .

Therefore, for a given size chip, e.g. 30,000
Any circuit that can be contained within a square mil (0,762 m4) chip will cost about the same.

If a suitable yield can be obtained, 16
The cost per bit can be much lower by manufacturing 16,384 (2") bits of memory cells than by creating a 4-bit device.

However, as the size of a chip increases, the yield decreases, so for sizes larger than approximately 180 mils (4,572 mvt) on the minus side, the decrease in yield becomes a greater problem.

Therefore, it is desirable to reduce the area occupied by each bit or cell of the RAM.

The single-transistor type cell of the MO8 integrated circuit employs a storage capacitor type with a silicon oxide dielectric, which was developed by Jack Niskillby (JackS, K11by).
The invention is described in U.S. Pat. No. 3,350,760 (issued November 7, 1967), assigned to Texas Instruments Corporation.

These are so-called gate-type, i.e. voltage-dependent, and can have an ion implantation region under the gate, as described by Gerald D.
No. 645,171, filed December 29, 1975 by Cedar Kuo (C.
No. 722,841, filed September 13, 1976, by (Kuo), both assigned to Texas Instruments Corporation.

The size of the storage capacitor for a single transistor cell must be large so that the time between refresh cycles is long and a good signal is generated at the pins when the cell is accessed.

Larger arrays such as 128x128 or 256x256 have longer bit lines and higher capacitance, which tends to reduce signal amplitude because the ratio of storage capacitance to bit line capacitance is reduced.

Also, in larger arrays, the cell area is smaller, so the capacitance is smaller.

Capacitance can be increased by reducing the thickness of the oxide dielectric, but yield is reduced.

Storage capacitor reliability is important in dynamic RAMs that use single transistor cells.

This is because the capacitor constitutes a major portion of the total oxide area of the chip.

Generally, both device reliability and yield are inversely related to the chip area occupied by the thin film.

The capacitor dielectric area is more important than the transistor gate area.

This is because it is under larger and higher electric field distortion.

According to lifetime test data on N-channel MOS dynamic RAM devices, 80 to 80% of reliability defects
90% is due to oxide defects in the storage capacitor.

Increasing the area of the capacitor reduces the electric field strength within the storage capacitor dielectric for a given stored charge, increasing reliability.

Alternatively, the electric field strength may be reduced (by making the oxide film thinner, thereby increasing the capacitance per unit area and reducing the overall oxide film area).

SUMMARY OF THE INVENTION An object of the present invention is to provide a MOS memory having a plurality of memory cells including an insulated gate transistor and a storage capacitor, which has an improved storage capacitor and is highly integrated.

According to one embodiment of the present invention, an N-channel silicon gate MOS using interlayer capacitance between two layers of polycrystalline silicon
An improved storage capacitor for a memory cell is provided.

The 'th' layer provides the intermediate electrode of the storage capacitor for all cells of a row, and below this electrode is preferably provided an ion implantation region which serves to lower the voltage required to invert this region. .

This first layer is connected to a low voltage bias voltage source or ground potential.

The second layer of polycrystalline silicon acts as an access device.
It becomes the gate of the OS transistor and also makes a connection from the gate to a metal strip on top that is used as an address line.

According to the invention, the first and second layers of polysilicon are separated from each other by a thin dielectric, so that the second layer of polysilicon is also the top electrode of the capacitor structure.

The second layer of polysilicon contacts the drain of the MOS transistor in the N0 region between the transistor and the capacitor.

The implant area extends beyond the edge of the first layer of polysilicon to the MOS
Extend towards the transistor to ensure a low impedance path.

Furthermore, in the present invention, the capacitance of the storage capacitor element.

In order to increase the storage capacitance element relative to its occupied area, the storage capacitor element has a multilayer structure, and each electrode forming the element has a concave shape.

The principal features of novelty which are considered to be characteristic of the invention are set forth in the claims.

However, the invention itself, as well as other features and advantages of the invention, will become clearer from the following detailed description of specific embodiments taken in conjunction with the drawings.

The storage capacitance element constituting the MOS RAM cell according to the present invention has the sixth a.
As shown in Fig. 6b, it has a concave multilayer structure.

However, for ease of understanding, a planar storage capacitor element will be described with reference to FIGS. 1 to 4.

What is shown in these figures is substantially similar to the embodiment of the invention shown in FIGS. 5-6b, except for the shape of the storage capacitor element.

FIG. 1 shows the physical allocation of MOS RAM cells making up a MOS memory.

The cell acts as a transfer device or an access device.
N-channel MO8) includes a transistor 10 and a storage capacitor 11, the circuit of which is shown in the electrical diagram of FIG.

Sense line 12 is made up of N1 diffusion regions and is one of the Y lines that connect to a number of cells in a row.

For example, if there are 128 or 256 cells in one row,
Each cell has a transistor 10 and a capacitor 11 connected to a sense line 12.

U.S. Patent Application No. 691,734 to White and Kitagawa filed June 1, 1976, or U.S. Patent Application No. 682,687 to Kitagawa and McAlexander, filed May 3, 1976, or Hotoito and McAdams and If a read amplifier of the type shown in Redwine, U.S. patent application Ser. It will be placed in the center of the sense line.

The metal strip 13 forms an address line or column selection line extending in the horizontal direction (X direction) in FIG.
pcs, connect to all gates.

The area occupied by the cell in Figure 1 is approximately 1/2 square mil (0,0
00,322 square millimeters).

As best shown in FIGS. 3a and 3b, each MOS transistor 10 has a source (or drain)
including an N+ diffusion region 14 forming a.

The N0 region 14 is a part of the sense line 12, and the sense line 1
2 is a long continuous diffused N+ moat region extending in the vertical direction (Y direction) in FIG.

Transistor 10 further includes a gate 15 made of a second layer of polycrystalline silicon, as described below.

The other N0 area in the moat is gate 15 and capacitor 1.
The drain (or source) of the MOS transistor between 1 and 1
6 and also connects to the top of the capacitor.

The silicon oxide thin film layer 18 serves as a gate insulating film for the MOS transistor 10, and another thin oxide film 19 forms the lower dielectric of the capacitor 11.

Oxide layers 18 and 19 are formed in different manufacturing processes and therefore have different thicknesses.

The intermediate electrode of the capacitor 11 is made of a first layer of polycrystalline silicon, a long strip 20 connected to the supply voltage vx.

As will be described later, vX may be a high voltage such as Vdd, but a lower voltage is preferred, and in a preferred embodiment Vx is Vss or ground potential.

The first layer of polysilicon 20 is formed by the silicon oxide film layer 24.
and second layer polysilicon 20 and second layer polysilicon 2
The second layer of polysilicon 21 from which 1 is separated is the upper electrode of the multilayer capacitor 11 according to the invention.

A thick silicon oxide layer 22 covers the entire chip and the polysilicon layer and transistors.

As seen in FIG. 3b, metal strips 13 forming column address lines are overlying layer 22 and extend downward to contact the gates 15 of the second layer of polysilicon at contact areas 23.

An important feature of the invention is that capacitor 11 utilizes the capacitance between the first polysilicon layer 20 and the second polysilicon layer 21.

According to the invention, therefore, the capacitor comprises three elements: an inversion region 1γ formed in the silicon below the first layer of polysilicon 20 and functioning as a tip electrode;
Junction capacitance 11a between 0 and inversion region 1γ and V at one end of the row
They are an MO8 capacitor 11b between the first layer polysilicon lines 20 connected to X and inverting the region 11, and an interlayer capacitor 11c.

The total capacitance is approximately twice that of a conventional cell of the same size.

The storage capacitor 11 must be as large as possible to allow a long period between refresh cycles and allow the cell to write a large "level" to the sense line.

Thus, typically this level is only a few hundred millivolts, which is even smaller when making large arrays with 128 or 256 cells per row.

The voltage written to the sense line is approximately proportional to the ratio of the capacitance of storage capacitor 11 to the bit line.

Capacitance 11b is inversely proportional to oxide thickness and directly proportional to area, both of which are detrimental to yield and bar size standards, respectively, especially for 128x128 bits or 256x25
This is harmful when creating arrays of 6 bits or more.

The thickness of the oxide layer 19 is as described in U.S. patent application Ser. According to the application, the voltage applied to line 20 is less than Vdd;
That is, it is 5 to 7 volts, and therefore the electric field strain applied to the oxide film layer 19 is low, making it possible to improve the yield for a given area and thickness.

For this purpose, the region 1γ is implanted with phosphorus so that it is inverted at very low voltages, ie its threshold value is reduced.

By choosing the initial materials and implants appropriately, the voltage applied to the first layer of polysilicon 20 can actually be brought to the rOJ level or ground potential.

In addition to these advantages, the present invention allows for further increases in capacitance.

Next, the manufacturing method of the cells shown in Figs. 1 to 3 will be explained in Figs. 4a to 4.
This will be explained with reference to figure b.

The first material is a single crystal silicon slice, approximately 3 in diameter.
inches (76,2 mm) and 20 mils (0,508 m) thick.
m) is a semiconductor silicon doped with boron to give a dynamic resistivity of about 6 to 8 Ω.

FIG. 4a shows a very small bar 30 of silicon slices.
In order to make the illustration easier to understand, the vertical and horizontal dimension ratios are different from those of the actual product.

The small portion of bar 30 shown in FIGS. 4a-4e includes one cell and is less than 1 mil (25.4 microns) wide.

The area occupied by 16.384 cells, sense amplifiers, decoding circuits, input/output buffer bonding pads, etc. is preferably 30,000 mils square (0.76
2 關square) would be f.

A 256 x 256 bit or 65,536 bit array should be built on a bar no larger than about 60,000 square mils (1,524 square meters).

In this case, the area per cell is 1 mil (25.4 microns)
It should be much smaller than a square, about 1/2 mil (
12.7 microns) square.

In actual size, the various layers and regions of Figures 4a-4e would be very thin compared to the width dimension.

First, the silicon slices were heated for about 1,000 mL in an oxidizing atmosphere.
℃ for a time sufficient to form a silicon oxide thin film 31 with a thickness of about 100 OA.

A photoresist coating 32, such as KMER or Kodak metal etch resist, is applied to the oxide film.

The layer 32 is exposed to ultraviolet light through a mask provided to define the desired pattern of inversion capacitor regions 11 .

The photoresist 32 is developed to create window areas 33 as seen in Figure 4a.

10 at a concentration of approximately 5X 1012-5X 1013
Implanted at 0 KeV, each cell has a phosphorous doping region 34.
Create.

This region will later become the semiconductor region 11 of the capacitor.

Oxide layer 31 is left in place to protect the silicon surface and prevent diffusion from the implant area.

Then add a layer of approximately 1000 silicon nitride Sl3N4 to the oxide film by exposing the slice to an atmosphere of silane and ammonia in an RF plasma discharge device;
Another photoresist coating 36 is then applied and patterned to define what will become the moat area.

This situation is shown in FIG. 4b.

The slices are then processed using selective etching, such as a plasma etching technique, to remove the silicon nitride but leave the photoresist coating 36 and the silicon oxide film 31.

Next, the slice is subjected to an ion implantation process at approximately 100K.
Boron is implanted at a dosage of approximately 4.times.10@12 atoms/d using an eV beam to form a shallow P.sub.1 region 3.gamma. in a region not masked by the photoresist coating 36 and the nitride film 35.

The slices were then sliced for 10 minutes as described in co-pending US Application No. 648,595 by G.R.
Subjected to nitrogen annealing at 00°C.

The slice is then subjected to an extended oxidation treatment at 900 DEG C. in steam or oxygen to create a thick field oxide region 38, as seen in FIG. 4C, and a "mout" is formed where no field oxide grows.

That is, the portion masked by the nitride film layer 35 prevents the oxidation, but in the exposed region the silicon surface is approximately 50%
Retreating to a depth of 0OA, a layer 38 approximately 10,000 people thick forms.

The original P+ region 31 is consumed, but boron diffuses to the front of the oxidized surface to create a P+ region 39 in the bottom metal portion of the field oxide region 38.

These regions 39 act as channel stops and prevent the formation of parasitic transistors.

The remaining portions of nitride layer 35 are then removed with a hot phosphoric acid etchant and oxide layer 31 is removed with a hydrogen fluoride etchant.

The slice is thermally oxidized without a mask to form a thin oxide film on all exposed surfaces, creating a thin dielectric oxide layer 19 approximately 500 to 800 nm thick.

Polycrystalline silicon is deposited over the entire slice to a thickness of about 0.5 microns using a silane decomposition process in a reactor.

This polysilicon layer is phosphorus-diffused or implanted to lower its resistance and then a first layer of polysilicon strip 20 is defined.

Pattern using photoresist masking as shown in Figure 4c.

A mask used in this operation is made to define the polysilicon line of the first layer shown in FIG.

The rightmost end 40 of the region 11 is connected to the drain region 16 of the MOS transistor of the storage monkey in FIG. 3a.
, not the right edge of the polysilicon.

It is important that region 40 within implant area 11 extends beyond the right edge of poly layer 20.

The fourth layer of polysilicon is then thermally oxidized to form an interlevel dielectric layer 24.

For this purpose, the slices are exposed to oxygen at about 900° C. for 1 hour to create an oxide film with a thickness of about 80 Å to 1500 Å.

Preferably, the gate oxide 18 for the MOS transistor is formed at this time, and according to the aforementioned US Pat. No. 722.841, the gate oxide is thicker than the layer 19;
Capacitor 11 will have a larger value.

Referring now to FIG. 4d, the slice is coated with a layer of photoresist 41 and the polysilicon-mout contact area 4
The area 42 above the area 42 where the area should become 3 is exposed to UV light through a mask that covers it.

The photoresist is then developed to form a window in region 42, and the oxide film is etched away using the photoresist as an etch mask.

When a second layer of polysilicon is then deposited, it will be in direct contact with the silicon at the contact 43.

Again using the silane decomposition process, a second layer of polycrystalline silicon is applied to the entire slice surface to a thickness of about 0.5 microns.

The slice is then coated again with photoresist and exposed using a mask that defines the pattern of the second layer of polysilicon, ie the gate 15 of the MOS transistor and the top layer 21 of the capacitor.

Then, using the developed photoresist as a mask, the unnecessary polysilicon layer is etched using an etching agent that attacks silicon but not the silicon oxide film.

The slice is then subjected to a short etching step to remove the remainder of the gate oxide layer on the exposed areas of the silicon surface.

This part is where the diffusion N+ region will be created.

The slices are then phosphorus diffused using conventional techniques to create N+ regions 12 and 16.

The exposed polysilicon layer is also heavily doped by the tipping operation.

The depth of this diffusion into crystalline silicon is approximately 500 nm.

Since the edge of the gate oxide film 18 defines the edge of the channel of the MOS transistor, it serves for positional matching.

After N0 diffusion, the entire slice is covered with a thick layer 22 of silicon oxide, which is done using a low temperature deposition process so that no further diffusion of impurities in regions 12 and 16 occurs.

A thick oxide coating 22 is formed in a predetermined pattern using photoresist to create windows for contact areas 23.

A thin layer of aluminum is then deposited over the entire slice and the metal strips 1 are formed in a predetermined pattern using photoresist.
Leave 3.

This completes the essential manufacturing steps, after which the slices are overcoated, scored, divided into individual chips, and packaged according to methods known in the art.

When using the illustrated cell arrangement and the manufacturing process described above, less precision is required in mask alignment for a particular layer.

It does not matter if the mask defining the first layer of polysilicon 20 is offset in either direction (to the left or right as shown in FIG. 1) from the edge of the moat defining capacitor 11.

Even if there is a considerable error in the mask defining the second layer of polysilicon 21, there will be no major deviation in alignment with the first layer.

The positioning of the window 23, like the positioning of the mask that defines the metal strip 13, does not require very high precision.

Due to the portion 40 of the implanted capacitor region 1γ extending far past the right edge of the first layer polysilicon layer 20, the alignment of the mask that defines the opening 42 or contact region 43 also depends on the portion that will become the gate 15. No particularly precise positioning is required as long as it is formed to expose a small portion of the area between the intermediate polysilicon layer 20. In a conventional single transistor cell, the electrode corresponding to line 20 is typically +12 volts. must be connected to the potential Vdd.

It forms an inversion layer on the silicon surface and that layer is Vdd
This is because a potential Vt lower than the logic [J] is accepted as the storage voltage.

However, in the cell of the present invention, the storage capacitor is doped with a suitable type of dopant so as to exhibit depletion mode characteristics.
For example, phosphorus is implanted in region 17 for N-channel processing.

Therefore, a voltage much lower than Vdd (preferably V
ss) can be connected to the polysilicon electrode 20 of the storage capacitor to receive the same "I" level storage voltage.

Furthermore, Ni F Tarash (A, F, Ta5ch
), U.S. Patent Application No. 740,528, filed November 10, 1976, or Taras et al.
In accordance with US Patent Application No. 752,598, filed on May 20, 2006 (all pending applications and assigned to Texas Instruments Inc.), the P0 area may be implanted a little deeper than the area 11.

The P region directly f in the N implantation region is a P-n junction capacitor 1.
Capacitor 11 acts to increase the size of capacitor 1a.
The total value of increases significantly.

Next, embodiments of the present invention are shown in FIGS. 5, 5a, 6a,
This will be explained using FIG. 6b.

As mentioned above, in the present invention, in order to increase the capacity of the storage cell in comparison with its occupied area, the shape of the storage cell is made concave, as shown in FIGS. 6a and 6b. It is obtained by forming storage cells along V-shaped recesses formed by anisotropic etching.

This is what Mohanrao and Ji-Ching Lean (Jih-C)
hin Lien) Trundle Nis Cloak (Ra
ndall S, Mundt) and Taras 19
It is disclosed in US patent application Ser. No. 736.780, filed January 28, 1977 (assigned to Texas Instruments Corporation).

The cell includes a transistor 10, a capacitor 11, an N+ diffusion bit line 12, a metal word line 13, a first layer of polysilicon VX line 20, and a second layer of polysilicon 21.

As previously discussed, the gate 15 of transistor 10 is connected to bit line 13 by a metal-to-polysilicon contact 23.

All devices were the same as those in Figures 1-3, except that the V-shaped grooves 25 were etched using patterned Si02 as a mask and hydrazine as the etchant prior to the first oxidation step described above. The manufacturing method is the same except for that point.

Further, as noted above, Talash U.S. Application No. 740,52
No. 8 and No. 752,598, a P ten implant region 1γ can be introduced.

Here, boron is implanted using the same mask used for implanting phosphorus into region 17.

Since boron penetrates deeper than phosphorus, the P-type material on the lower side of the junction is more heavily doped than the original silicon 30, thus making the depletion layer narrower and increasing the P-n junction capacitance 11a. growing.

Another feature is that the leakage is mainly caused by thermally generated electron-hole pairs in the space charge region or the depletion region of the P-n junction, so the storage time before refresh is longer. If the distance is narrower, fewer electron-hole pairs will be generated.

Additionally, because a favorable potential gradient is created around the outside of the capacitor, vertical leakage currents tend to be minimized.

Although the invention has been described with reference to specific embodiments, this description should not be construed in a limiting sense.

Various modifications to the disclosed embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reference to the description of the invention.

Therefore, the following claims are intended to include such modifications or embodiments as falling within the scope of the invention.

[Brief explanation of drawings]

FIG. 1 is a drawing for explaining the present invention, and is a random access memory cell Gt in which storage cells are formed in a planar shape.
11\mA # of s-type semiconductor chip, large plan view, 2nd
The figures are electrical schematic diagrams of the cells in Figure 1, Figures 3a and 3b.
The figures are cross-sectional views taken along lines aa and bb in Fig. 1, respectively, and Fig. 4 awf is a sectional view taken along line a-a in Fig. 1 at each stage of the manufacturing process.
5 is a plan view of a memory cell according to an embodiment of the present invention; FIG. 5a is an electrical schematic diagram of the cell of FIG. 5; and FIG. 6a is a cross-sectional view of the cell of FIG. FIG. 6b is a perspective view of the cell taken along the line -a, and FIG. 6b is an elevational view of the cell taken along the line bb of FIG. Explanation of reference numbers: 10...MOS transistor, 11...storage capacitor, 12...
Sense wire, 13...Metal strip, 14...
...Source, 15...K-1-116...
...Drain, 17...Capacitor area,
18...Gate oxide film, 19...Oxide film, 20...First layer of polysilicon, 21...
. . . second layer of polysilicon, 22 . . . thick silicon oxide film layer, 24 . . . silicon oxide film layer.

Claims (1)

[Scope of Claims] 1. A MOS memory having a plurality of memory cells arranged in rows and columns, each including an insulated gate transistor and a storage capacitor, comprising: (a) a plurality of transistors extending in the Y direction and in each row; (b) a first conductive layer sandwiched between insulating layers and extending in the Y direction so as to supply intermediate electrodes of storage capacitance elements in all memory cells in one row; (c) a second conductive layer that contacts the source or drain of the transistor, extends over the fourth conductive layer and a portion of the insulating layer, and serves as the upper electrode of the storage capacitor in each memory cell; (d) a third conductive layer formed on the semiconductor surface, connected to the source or drain of the transistor, and serving as the lower electrode of the storage capacitance element in each memory cell; (e) running over the insulating layer on the second conductive layer in the direction; an X-conducting line extending in the X direction substantially perpendicular to and connected to the gate of the transistor; 2. A MOS memory characterized in that: the MOS memory is formed in a multi-storage capacitor element, and forms a multiple storage capacitor element together with the insulating layer. 2. The MO according to claim 1, wherein the recess is a recess formed by anisotropic etching on the semiconductor surface.
S memory.