JPS5812457Y2 - handmade takiokusouchi - Google Patents

Description

[Detailed description of the invention] The present invention relates to semiconductor devices, particularly highly integrated single-cell and semiconductor devices.
The present invention relates to a semiconductor memory device having a one-transistor configuration.

2. Description of the Related Art Conventionally, semiconductor memory devices have been known in which one memory cell is composed of only one transistor and one capacitor.

FIG. 1 is an explanatory diagram of the main part structure, and 1 is a semiconductor substrate;
2 is an insulating layer, 2' is a gate insulating film, 3 is a source region, 4
is the drain region, S is the source electrode, G is the gate electrode, C
is a capacitor electrode, L is an inversion layer, B is a bit line, W is a word line, and VDD is a power supply voltage.

In this conventional example, a high voltage is applied to the capacitor electrode C to generate an inversion layer in the vicinity of the surface of the semi-moving body substrate 1 immediately below the capacitor electrode C, a part of which is in contact with the drain region 4, and this inversion layer and the capacitor electrode Information is written and read by accumulating or discharging charge in the capacitance formed between the MO8 field effect transistor and the MO8 field effect transistor.

This semiconductor memory device can inherently be highly integrated due to its simple structure, but recent semiconductor integrated circuit devices and electronic devices are demanding even higher integration.

However, if the semiconductor memory device is to be highly integrated, for example, if the planar area of the storage capacity is reduced, it becomes impossible to reliably store information.

The purpose of this invention is to improve the degree of integration without reducing the size of memory capacity, and the present invention is based on a single MIS field effect transistor whose gate is connected to a word line and source is connected to a bit line. and one electrode is connected to the MIS
In a semiconductor memory device that integrates one memory cell formed by combining the drain of a field effect transistor and a memory capacitor whose other electrode is connected to a predetermined potential line, a first memory cell and a second memory cell are adjacent to each other. The storage capacity of the first memory cell is provided as one electrode, and the inversion layer near the surface of the semiconductor substrate, which is electrically connected to the drain of the MIS field effect transistor of the first memory cell, is used as one electrode, and the insulating film on the inversion layer is provided. The upper common electrode is used as the other electrode, and the second memory cell is formed on the insulating film on the common electrode with the common electrode as the other electrode, and the drain of the MIS field effect transistor of the second memory cell is formed on the insulating film on the common electrode. The present invention provides a semiconductor memory device characterized in that the other electrode is an electrode connected to the common electrode, and the common electrode is connected to the predetermined potential line, which will be described in detail below.

FIG. 2 is an explanatory diagram of the main parts of the present invention - an embodiment.

In the figure, 11 is a semiconductor substrate, 12 is an insulating layer, 12□
.

12□ is a gate insulating film, 13. ．． 13□ is the source area,
14. , 142 is a drain region, 15 is an insulating layer, Sl
, S2 are source electrodes, G1. G2 gate electrode, C1, C
2 is a capacitor electrode, L is an inversion layer, Bl, B2 are bit lines, W
1 and W2 are word lines, and VDD is a power supply voltage, respectively.

In addition, the capacitive electrode CI. C2 may be either metal or polycrystalline silicon.

FIG. 3 is a diagram equivalently representing the embodiment of FIG. 2 as a circuit.

In the figure, Q□ and Q2 represent MIS field effect transistors, and Cml and Cm2 represent storage capacities, respectively.

Comparing the circuit of FIG. 3 with the configuration of FIG. 2, one transistor includes a gate insulating film 12□, a source region 13□,
The transistor Q2 is composed of a drain region 14□ and corresponding electrodes, and the transistor Q2 is composed of a gate insulating film 12□, a source region 13°, a drain region 142, and corresponding electrodes. The storage capacitor Cm1 is formed between the inversion layer and the capacitor electrode C□, and the storage capacitor Cm2 of the transistor Q2 is formed between the capacitor electrode C1 and the capacitor electrode C2.

As can be seen from the above description, in this embodiment, the storage capacity in the conventional structure is approximately two storage capacities Cm in the area of one
1. Cm2 and separate transistors Q1 and
．． Q2, resulting in a significant increase in integration density and an effective area/bit of about 100 kHz compared to the conventional one.

FIG. 4 shows the main circuit of another embodiment, and FIG.
The same parts as those described with respect to the figures are indicated by the same symbols.

This embodiment differs from the previous embodiments in the configuration of storage capacity.

That is, the storage capacitance of the transistor Q1 has a configuration in which the capacitance between the inversion layer and the capacitor electrode C1 and the capacitor between the capacitor electrode C1 and the capacitor electrode C3 are connected in parallel. , the storage capacity of the transistor Q2 is the inversion layer I
The capacitor between L2 and capacitor electrode 01 and the capacitor between capacitor electrode C1 and capacitor C2 are connected in parallel.

In this embodiment, the storage capacity in the conventional structure is approximately the area of one transistor Q□.

In 1Q2, each is used to form the storage capacity.

However, the capacitance value is almost the same as that of the embodiment in FIG. 2 because the storage capacity is in two layers and two storage capacitances are connected in parallel.

In the above embodiment, the memory capacity is made up of two layers, but the invention is not limited to this, and the reliability of information storage can be increased by forming multiple layers to increase the memory capacity value per transistor. In addition, by properly arranging the transistors, the area for one storage capacity can be reduced.
While it is possible to form a storage capacity equivalent to three or more transistors, it is also possible to achieve higher integration.

As can be seen from the above explanation, according to the present invention, one MI
By multi-layering the capacitors constituting one cell in combination with S field effect transistors, it is possible to improve the degree of integration or increase the capacitance value to ensure accuracy in information storage.

[Brief explanation of the drawing]

Fig. 1 is a structural explanatory diagram of the conventional example, Fig. 2 is a structural explanatory diagram of the first embodiment of the present invention, Fig. 3 is a circuit diagram of the embodiment shown in Fig. 2, and Fig. 4 is a structural explanatory diagram of another embodiment. respectively. In the figure, 11 is a substrate, 12 is an insulating layer, 12□, 12
□ is an insulating film, 13□, 13□ are source regions, 14. ．． 1
4□ is a drain region, 15 is an insulating layer, Sl and S2 are source electrodes, G1. G2 is a gate electrode, C, C2 are capacitor electrodes, L is an inversion layer, B1 and B2 are bit lines, and VDD is a power supply voltage.

Claims (1)

[Scope of utility model registration request] A memory comprising one MIS field effect transistor whose gate is connected to a word line and whose source is connected to a bit line, one electrode is connected to the drain of the MIS field effect transistor, and the other electrode is connected to a predetermined potential line. In a semiconductor memory device in which one memory cell is integrated, a first memory cell and a second memory cell are provided adjacent to each other, and the memory capacity of the first memory cell is the same as that of the first memory cell. The inversion layer near the surface of the semiconductor substrate that is electrically connected to one drain of the MIS field effect transistor of the cell is used as one electrode, the common electrode on the insulating film on the inversion layer is used as the other electrode, and the second
The storage cell has the common electrode as the other electrode and an electrode formed on the insulating film on the common electrode and connected to the drain of the MIS field effect transistor of the second storage cell, and A semi-dynamic memory device characterized in that a common electrode is connected to the predetermined potential line.