JPH02206164A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize a much higher density by a method wherein charge-storage parts of a first memory cell capacitor and a second memory cell capacitor are formed as multilayers on an interlayer insulating film at the upper part and the lower part by sandwiching a cell plate electrode and individual insulating films. CONSTITUTION:An interlayer insulating film 7 is formed on a semiconductor substrate 8; a charge-storage part 10 of a first memory cell capacitor is formed on the insulating film 7; an insulating film 11 of the first memory cell capacitor is formed on it; a cell plate electrode 5 composed of a conductor 1 is formed on it. The electrode 5 is used in common as a cell plate of the first memory cell capacitor and a second memory cell capacitor. In addition, an insulating film 13 of the second memory cell capacitor is formed on the cell plate electrode 5; lastly, a charge-storage part, of the second memory cell capacitor, composed of the conductor 1 is formed. Thereby, a high density can be realized without reducing an area per memory cell.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device. [Prior Art] Recently, the density of semiconductor memory devices has been increasing, and in particular, the density of semiconductor memory devices has increased. The increase in the degree of integration and density of (DRAM) is remarkable. The development of RAM is largely due to the development of high-density technology for memory cells, which occupy an area of more than half of the chip size. FIG. 2 shows an example of such a memory cell.

FIG. 2(A) is a plan view of the memory cell, and FIG. 2(B) is
FIG. 2 is a cross-sectional view taken along line a-a' in FIG.

In FIG. 2, 1 is a conductor constituting a focus line, 2 is a drain portion connected to the conductor 1 constituting a bit line,
Reference numeral 3 denotes a gate electrode of a transistor for signal readout (MO3) constituting a word line.

4 is a gate oxide film of the MO3) transistor for reading out the signal, and 5 is a cell plate electrode connected to a cell plate voltage source. 6 is an insulating film for cell isolation, 7 is an interlayer insulating film between each conductor, 8 is a substrate of a conductivity type opposite to that of the drain part 2, 9 is a source part of a memory cell of the same conductivity type as the drain part 2, 10' 11 is a charge storage portion of a memory cell, and 11' is an insulating film constituting a memory cell capacitor. 14 is a contact window that connects the conductor 1 and the drain portion 2 constituting the bit line, and 15' is a contact window that connects the source portion 9 of the memory cell and the charge storage portion 10'.

What is shown in FIG. 2 above is a so-called stacked memory cell. By setting the gate electrode 3 constituting the word line to a logic voltage "H", this memory cell transmits information on the conductor 1 constituting the bit line from the drain section 2 to the source section 9 of the memory cell to charge the memory cell. Accumulation section 1
0' (write state), or read out the information stored in the charge storage section 10' of the memory cell to the conductor 1 constituting the B71 line (read state).

The above-described stacked memory cell does not use the substrate surface as a charge storage section, but uses the upper part of the interlayer insulating film 7 formed on the substrate 8, so that charges are transferred from the charge storage section 10' to the substrate 8. Leakage is considered to be an important factor in the structure of high-density memory cells.

[Problem to be solved by the invention]

In order to increase the density of such conventional memory cells, 1
When trying to reduce the actual memory cell area, the area of the opposing electrode of the memory cell capacitor becomes smaller, and therefore the capacitance value of the memory cell capacitor also decreases, making it difficult to read information accurately and leading to malfunctions. was there.

An object of the present invention is to provide a semiconductor memory device that can achieve higher density without reducing the area of each memory cell.

(Means for Solving the Problems) In the semiconductor memory device of the present invention, an interlayer insulating film is formed on a semiconductor substrate, a charge storage portion of a first memory cell capacitor is formed on the interlayer insulating film, and An insulating film of the first memory cell capacitor is formed on the insulating film, and a cell plate electrode made of a conductor is formed on the insulating film.The cell plate electrode is shared as a cell plate of the first and second memory cell capacitors. Further, an insulating film of a second memory cell capacitor is formed on this cell plate electrode, and finally a charge storage portion of the second memory cell capacitor made of a conductor is formed.

The charge storage section of the first memory cell capacitor and the charge storage section of the second memory cell capacitor are connected to the source section of the signal readout MO3) transistor of each memory cell, and are connected to the source section of the signal readout MOS transistor of the respective memory cell. , the configuration is such that information is read and written to each memory cell capacitor.

[For production]

According to the structure of the present invention, the charge storage portions of the first and second memory cell capacitors are formed in multiple layers above and below the cell plate electrode and each insulating film on the interlayer insulating film. The areas of the opposing electrodes of the first and second memory cell capacitors are larger than those formed side by side as in the conventional configuration, and therefore the capacitance value of the memory cell capacitors is correspondingly larger, making it possible to read information accurately and stably. memory cells can be realized.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention, in which (A) is a plan view of the main part, and (B) is a plan view of the main part.
) is a sectional view taken along line a-a'.

In FIG. 1, 1 is a conductor constituting a bit line, 2 is a drain portion connected to the conductor 1 constituting the bit line,
Reference numeral 3 denotes a gate electrode of a signal reading MO3I transistor constituting a word line.

4 is a gate oxide film of the MO3+- transistor for signal reading, and 5 is a cell plate electrode connected to a cell plate voltage source. 6 is an insulating film for cell isolation, 7 is an interlayer insulating film between each conductor, 8 is a substrate of the opposite conductivity type to the drain part 2, 9 is the source part of the memory cell of the same conductivity type as the drain part 2, and IO is 11 is the charge storage section of the first memory cell;
12 is a second insulating film constituting a memory cell capacitor;
The charge storage portion 13 of the memory cell 13 is an insulating film constituting a second memory cell capacitor. 14 is a contact window that connects the conductor 1 constituting the bit line and the drain part 2; 15 is a contact window that connects the source part 9 and the charge storage part 10 of the first memory cell; 1G is the contact window that connects the source part 9 and the charge storage part 10 of the first memory cell; This is a contact window that connects the charge storage section 12 of the second memory cell.

In this semiconductor memory device, an interlayer insulating film 7 is formed on a semiconductor substrate 8, a charge storage part 10 of a first memory cell capacitor is formed on this interlayer insulating film 7, and a first charge storage part 10 is formed on the interlayer insulating film 7.
An insulating film 11 of a memory cell capacitor is formed, and a cell plate electrode 5 made of a conductor is formed thereon. This cell plate electrode 5 is shared as a cell plate for the first and second memory cell capacitors.

Further, an insulating film 13 of a second memory cell capacitor is formed on this cell plate electrode 5, and finally a charge storage part 12 of the second memory cell capacitor made of a conductor is formed. The charge storage section 10 of the first memory cell capacitor and the charge storage section 12 of the second memory cell capacitor are connected to the signal readout MO of each memory cell.
3) The transistor is connected to the source portions 9, 9 of the transistor for signal reading. 3) The transistor is configured to read and write information in each memory cell capacitor.

In this manner, in this semiconductor memory device, the charge storage portions 10.12 of the first and second memory cell capacitors are configured one above the other with the cell plate electrode 5 in between.

As for the operation, similar to the conventional example shown in FIG. Through the source section 9, the information of the memory cell is written to the charge storage section IO. An operation of reading to the conductor 1 is performed.

According to the configuration of this embodiment, on the interlayer insulating film 7, the charge storage portions 10.12 of the first and second memory cell capacitors are connected to the cell plate electrode 5 and each insulating film 11.
13, the opposing electrode area of the first and second memory cell capacitors is larger than that of a conventional structure in which they are arranged side by side. Therefore, the capacitance value of the memory cell capacitor increases accordingly. This also increases the size of the memory cell, making it possible to read information accurately and realizing a stable memory cell.

〔Effect of the invention〕

According to the semiconductor memory device of the present invention, since these two memory cell capacitors are formed in a multilayer structure on the interlayer insulating film, a sufficient capacitance value of the memory cell capacitor can be secured, and -
It becomes possible to increase the density of layers, lead to miniaturization of chip size, and in turn, it becomes possible to supply low-cost semiconductor memory devices, which has extremely large practical effects.

[Brief explanation of the drawing]

FIG. 1(A) is a plan view of essential parts of an embodiment of a semiconductor memory device according to the present invention, and FIG. 1(B) is a-a-a of FIG. 1(A).
2(A) is a plan view of essential parts of an example of a conventional semiconductor memory device, and FIG. 2(B) is a sectional view taken along line a--
It is a sectional view taken along the a' line.

Claims (1)

[Claims] An interlayer insulating film formed on a semiconductor substrate, a charge storage part of a first memory cell capacitor formed on the interlayer insulating film, and a charge storage part of a first memory cell capacitor formed on the first memory cell capacitor. an insulating film of the first memory cell capacitor; a cell plate electrode shared by the first and second memory cell capacitors formed on the insulating film of the first memory cell capacitor; A memory cell structure consisting of an insulating film of a second memory cell capacitor formed above and a charge storage part of a second memory cell capacitor formed on the insulating film of the second memory cell capacitor. A semiconductor memory device having: