JPS61134059A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain the titled device capable of constructing a large capacitance memory a small occupation area, by a method wherein a transistor of the memory cell is arranged on another transistor in three dimensions, and a partial construction is used in common. CONSTITUTION:A polycrystalline Si 17 is the diffused region of a transistor Q1 and at the same time serves as the gate electrode of a transistor Q3. Because of a small width l between polycrystalline Si's 15 and 17, channel regions 22, 23 become continuous. In the case of a large width l, an N<+> region can be inserted between the channels 22 and 23. The transistors Q1, Q2 are constructed by superposition and allowed to have multifunctions such as making the Si 15 as the gates of the transistors Q1, Q2 and the Si 27 as the diffused layer of the transistor Q1 and the gate electrode as the transistor Q3; therefore, the memory cell can be constructed small. The part surrounded by a dot line is a unit of memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device including dynamic memory cells.

[Technical background of the invention and its problems]

This type of prior art will be explained with reference to FIG. Q in the diagram
1 to Q3 are N-channel transistors, C8 is a gate capacitance formed at the gate of transistor Q3, Wv is a read/write line, and 1 is a sense amplifier. Here, the threshold voltage of transistor Q1 is vTl, and transistor Q
Let the threshold voltage of 2 be vT2, and the relationship vT,>vT□. When reading data, change the w, ywW lines to v,.

By setting the level between and vT2, the transistor Ql has a power of 7. Trannostar Q2 is brought into conduction. The resistance between the node 2 and the ground in the closed state is determined by the amount of charge in the f-to-capacitor C8 of the transistor Q3, so this is read out as information by an external circuit. Data writing is performed by raising the Wv line to a level higher than vTl and turning on the transistor Q1.

The problem with the above conventional technology is that the three transistors Q1 to Q
If 3 is placed on the plane of an integrated circuit, the occupied area will be large and a large capacity memory cannot be constructed.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a semiconductor memory device that uses three transistors, occupies a small area, and can constitute a large-capacity memory.

[Summary of the invention]

The present invention reduces the area of an integrated circuit in plan view by arranging a transistor in a memory cell three-dimensionally above other transistors and using a part of the structure in common.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a sectional view showing the configuration of the same embodiment, and FIG. 2 is a plan view of the pattern. In the figure, 11 is a P-type silicon substrate, 12 is an element isolation region (oxide film), xs, x4 are N+ diffusion regions, and N+ diffusion regions 1 and 3 are the ground points in FIG. 3, and N diffusion region 14 is the This corresponds to node 2 in Figure 3.

15 is polycrystalline silicon doped with phosphorus, which also serves as both gate electrodes of transistors Q1eQz in FIG. 16 is P-type polycrystalline silicon, 17.18 is N-type polycrystalline silicon, and polycrystalline silicon 16.17. I
g forms the channel region, source, and drain regions of the transistor Ql. Polycrystalline silicon 17 is a diffusion region of transistor Q1, and at the same time is a diffusion region of transistor Qs.
-) Becomes an electrode. 19, 20.21 are transistors Q+tQz+QsLD)r'-t oxide films, respectively. 22 is the channel region of the transistor Q2;
23 is the channel region of the transistor Qs, and since the width between the polycrystalline silicon 15 and 17 is narrow, the channel 22
, 23 are connected. If @t is large, an N 2 region can be inserted between the channels 22 and 23.

In the configurations shown in FIGS. 1 and 2, the same circuit as in FIG. 3 is constructed, and therefore the circuit operation is the same as in this case.

The advantage of the configurations shown in FIGS. 1 and 2 is that the transistors Q1 and Qz are stacked one on top of the other, and the polycrystalline silicon 15 is used as the gate of the transistors Ql-Qz.

Transistor Q using polycrystalline silicon 17! Since it has multi-functionality, such as being used as a diffusion layer and an r-) electrode of the transistor Q3, the memory cell can be made smaller.

This situation is clear when looking at the plan view of FIG. 2, and the area surrounded by the dotted line is the 1-rate memory cell.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a semiconductor memory device that occupies a small integrated circuit area and can be configured as a large-capacity memory.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a plan view thereof, and FIG. 3 is a circuit diagram of a conventional dynamic memory cell. Ql, Qz, Ql...transistor, 11...
・P-type substrate, 13.14...N+ layer, 15...polycrystalline silicon layer, 16-18...polycrystalline silicon layer, 1
9-21... Gate oxide film, 22.23... Channel region.

Claims (1)

[Claims] first and second transistors are formed adjacently in a semiconductor substrate, a third transistor sharing a gate electrode with the second transistor is formed above the second transistor, and the third transistor A semiconductor memory device characterized in that the diffusion region of the first transistor and the gate electrode of the first transistor are the same, and a capacitor is formed in the gate electrode.