JPH0682804B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory cell configuration suitable for high integration of the semiconductor memory device.

[Prior Art] FIGS. 3A and 3B are diagrams showing a highly integrated dynamic semiconductor memory device proposed in, for example, lecture number FAM17.4 of the 1985 International Solid State Circuit Conference (ISSCC85). 3A is a plan view thereof, and FIG. 3B is a sectional view taken along the line XX 'in FIG. 3A. In the figure,
On the P type substrate 1, an N ⁺ type diffusion layer 5, a field oxide film 2,
A first polycrystalline silicon layer 3, a second polycrystalline silicon layer 7, a first Al wiring layer 6, a second Al wiring layer 8, an interlayer insulating film 9, etc. are laminated. The first Al wiring layer 6 serves as a bit line and is electrically connected to the N ⁺ type diffusion layer 5 through the contact hole 10. The second polycrystalline silicon layer 7 serves as a word line, and is short-circuited by the second Al wiring layer 8 at regular intervals to reduce its resistance.

Here, a trench isolation region is formed around the memory cell MC. Utilizing the side surface of this trench digging separation region, the first
The information charge storage capacitance C _P is formed by the polycrystalline silicon layer 3, the capacitor insulating film 4 (a part of the field oxide film 2) and the N ⁺ type diffusion layer 5. The information charge storage capacitance C _F is also formed in the flat portion of the memory cell MC with the same configuration. Thus, by utilizing the grooved isolation portion on the outer peripheral portion of the memory cell MC as the information charge storage capacitance, even if the chip area is reduced and the flat portion area for forming the capacitance C _F is reduced,
It is possible to obtain a semiconductor memory device that has a sufficiently wide operation margin and can secure a sufficient information charge capacity.

[Problems to be Solved by the Invention] By the way, a structure of the above-mentioned conventional example in which an information charge storage region is formed in a trench isolation region is disclosed in, for example, JP-A-51-74535
When applied to the folded bit line configuration shown in the publication, the cross-sectional structure taken along the line YY 'in FIG.
As shown in the figure. In the structure shown in FIG. 4, the N ⁺ type diffusion layer 5 forming one electrode of the information charge storage capacitor is P
Since it is formed directly on the mold substrate 1, the contact area between the information charge storage capacitor and the P-type substrate 1 becomes large, and as a result α
The minority carriers (electron-hole pairs) injected by radiation such as particles are easily collected in the charge storage capacity. Therefore, there is a problem in that the stored information of the memory cell is susceptible to noise errors and the structure is not so effective for soft error resistance.

The present invention has been made to solve the above-mentioned problems, and it is possible to secure the amount of information storage charges even when highly integrated, and minimize the influence of the injection of minority carriers such as α particles. It is an object of the present invention to provide a highly integrated dynamic semiconductor memory device capable of achieving the above.

[Means for Solving Problems] A semiconductor memory device according to the present invention is arranged in a matrix in a plurality of rows and a plurality of columns, and each of the first and second semiconductor memory devices is provided.
A plurality of memory cells each having a MOS transistor and a capacitive element connected between one electrodes of these MOS transistors; and a plurality of memory cells arranged in a plurality of rows, each of which is arranged in a corresponding row. First and second MOS
A plurality of word lines connecting the gate electrodes of the transistors and a true bit connected to the other electrode of the first MOS transistor of the plurality of memory cells arranged in a plurality of columns, each of which is arranged in a corresponding column A plurality of bit line pairs each having a line and a complementary bit line connected to the other electrode of the second MOS transistor of the plurality of memory cells arranged in the corresponding column. A feature of this semiconductor memory device is that a pair of electrodes forming a capacitive element of each memory cell is provided on a surface of a semiconductor substrate located between first and second MOS transistors of a memory cell including the capacitive element. That is, it is formed in the element isolation groove provided in the formed element isolation groove.

[Operation] According to the semiconductor memory device of the present invention having the above configuration, the following operation can be obtained.

Since a pair of electrodes of the capacitive element is formed in the element isolation groove that isolates and insulates between the first and second MOS transistors of each memory cell, compared to the case where the capacitive element is formed on the surface of the semiconductor substrate. As a result, the flat area occupied by each memory cell can be reduced, and high integration of the chip can be achieved.

Since neither of the pair of electrodes of the capacitive element is directly formed on the surface of the semiconductor substrate, minority carriers injected by radiation such as α particles are less likely to be collected in the capacitive element. Therefore, the stored information in the memory cell is less likely to be affected by noise errors, which effectively acts as a soft error prevention measure.

The first MOS transistor connected to one of the true bit line and the complementary bit line forming the bit line pair and the second MOS transistor connected to the other share one capacitive element, and these two Since one bit is composed of MOS transistors, even if noise occurs on only one side of a MOS transistor that shares a capacitive element, the same noise is always added to both MOS transistors via the capacitive element and common noise is generated. Therefore, the data itself stored in the capacitive element is not affected by noise at all.

[Embodiment] FIGS. 1A and 1B are views showing a semiconductor memory device according to an embodiment of the present invention. In particular, FIG. 1A shows a plan view thereof, and FIG. 1B shows a line X in FIG. 1A. A cross-sectional view along the line -X 'is shown. In the figure, an N ⁺ type diffusion layer 5 is formed in an appropriate region on the P type silicon substrate 1. The N ⁺ type diffusion layer 5 serves as the source and drain regions of the gate transistor of each memory cell. P-type silicon substrate 1 between the N ⁺ -type diffusion layer 5 for forming the N ⁺ -type diffusion layer 5 and the source region forming a drain region forms a channel region 11 of the transistor. A polycrystalline silicon layer 15 serving as a word line is formed so as to pass over the channel region 11. Aluminum wiring 6 serving as a bit line is formed so as to be orthogonal to this word line 15. Here, the two bit lines 6 shown in FIG. 1A are so-called folded bit lines BL,
It constitutes ▲ ▼. Therefore, these bit lines
BL and ▲ ▼ are connected to the same sense amplifier (not shown). A plurality of memory cells each formed with a pair of two gate transistors are arranged along the bit line pair consisting of these bit lines BL, ▲ ▼. The pair of bit lines BL, ▲ ▼ are electrically connected to the source or drain region of the corresponding gate transistor of the pair of two gate transistors through the contact hole 10.

It should be noted that FIG. 1A shows only two sets of memory cells formed along a pair of bit lines BL, ▲ ▼, and other memory cells are omitted, but in reality, the same is true. Memory cells are arrayed in a matrix in the row and column directions.

Here, a trench isolation region 17 is formed around the N ⁺ type diffusion layer 5 and the channel region 11. This ditch isolation area 17
Inside, a pair of counter electrodes 12 and 13 are formed facing each other with a predetermined distance. The counter electrodes 12 and 13 and the capacitor insulating film 14 between them form a memory cell capacity, that is, an information charge storage capacity. Grooving isolation area 17
Includes a memory cell isolation groove 17b for isolating and insulating each memory cell and an element isolation groove 17a for isolating two gate transistors (MOS transistors) forming each memory cell. 12 and 13 are 2
An information charge storage capacitor is mainly formed in the element isolation groove 17a extending in the row direction (direction parallel to the bit line) between the two gate transistors. Further, the source and drain regions of each gate transistor have their side end portions on the upper portions of the side walls of the portion extending in the column direction (direction parallel to the word line) of the memory cell isolation trench 17b, and In the contact hold 16, one of the pair of counter electrodes 12 and 13 of the information charge storage capacitor is connected to the source or drain region. The counter electrode 12 is connected to the source or drain region of the gate transistor of the memory cell belonging to the bit line BL via the contact hole 16. The counter electrode 13 is connected via a contact hole 16 to the source or drain region of the gate transistor of the memory cell belonging to the bit line {circle around (1)}. Therefore,
One memory cell belonging to bit line BL and bit line ▲
One information charge storage capacitor is shared with one memory cell belonging to ▼. One thing to note here is 1
Two memory cells that share one information charge storage capacity are
A pair is formed on the bit line BL, and each gate transistor is controlled by the same word line.

Although a partial configuration of the memory cell array is shown in FIG. 1A, a larger number of word lines and folded bit line pairs are formed in the actual memory cell array, whereby the memory cells are arranged in a matrix.

In the semiconductor memory device configured as described above, since the information charge storage capacity is formed in the trench isolation region, sufficient information charge storage capacity can be secured even if the flat area of the chip is reduced, and as a result, the chip High integration can be achieved. Further, since the counter electrodes 12 and 13 are formed so as not to contact with the side walls of the trench isolation region 17, the contact area between the information charge storage capacitor and the P-type substrate 1 can be minimized,
As a result, it is possible to reduce the injection of minority carriers generated in the substrate due to α particles or the like into the information charge storage capacitance. Therefore, the occurrence of soft errors can be reduced.

FIG. 2 is an equivalent circuit diagram of the semiconductor memory device shown in FIGS. 1A and 1B. As shown in the figure, the gate transistor T of the memory cell belonging to the bit line BL has an information charge storage capacitance C.
Connected to one end of. The gate transistor T'of the memory cell belonging to the bit line (5) is connected to the other end of the information charge storage capacitor C. The gate transistor T
And T ′ form a pair, and their on / off are controlled by the same word line WL. As is apparent from FIG. 2, one memory cell belonging to the bit line BL and one memory cell belonging to the bit line (1) share one information charge storage capacity C to form one bit. Ie 2
One memory cell constitutes one bit. This 2-cell / 1-bit configuration has the following advantages.

Since the complementary signals are always output to the bit line pair, the dummy cell becomes unnecessary. Therefore, it is not necessary to consider the fluctuation of the reference voltage of the Dummy cell.

When the information charges are read to the bit line, the read signal voltage difference can be continuously output with the maximum width regardless of the precharge voltage of the bit line.

The noise voltage due to power supply voltage fluctuations, substrate voltage fluctuations, etc. is always in the common mode and is coupled to the memory cells, so that the operation margin does not change with respect to both high / low information.

From the above-mentioned advantages, when it is attempted to secure the same operation margin as that of the conventional semiconductor memory device, the value of the information charge storage capacity forming a pair can be made half or less of that of the conventional configuration, It is possible to reduce the size of the memory cell array section.

Further, in the configuration of the above-mentioned embodiment, two memory cells have one
Since the capacity of each memory cell is shared, even if noise is added to the memory cell on only one side due to noise due to α particles, etc., it always becomes common noise and is coupled to the other memory cell, so that the operation margin does not change at all.

As described above, by forming the inter-polycrystalline silicon capacitor in the trench isolation region and combining the counter electrode type 2 cell / 1 bit configuration with the folded type bit line configuration, the information charge storage capacity is large and the operation A highly integrated dynamic semiconductor memory device having a wide margin and a small chip area can be obtained.

Further, the element isolation groove 17a is formed by the aluminum wiring 6 (bit line BL, ▲
Since it is provided in parallel with ▼), the element isolation trench 17b is formed along the longitudinal direction of each gate transistor. Therefore, the pair of electrodes 12 and 13 of the capacitive element provided in the element isolation groove 17b can be arranged to face each other along the longitudinal direction of each gate transistor, and the area between the counter electrodes can be increased, and the capacitance can be increased. Can be achieved.

Furthermore, a pair of counter electrodes 12 and 13, one electrode (source or drain region) of each gate transistor, and a side end portion (contact hole 16) of one electrode partially exposed in the memory cell isolation groove 17b are electrically connected. Is connected to
In addition to the entire area of the element isolation groove 17a, the memory cell isolation groove 1
The facing portions of the facing electrodes 12 and 13 can also be formed in the vicinity of the side end portion of the one electrode of the gate transistor 7b. Therefore, the area between opposed electrodes per unit plane area can be further increased, and the capacitance can be further increased.

Furthermore, since the memory cell isolation trenches 17b communicating with the element isolation trenches 17a are provided in a grid pattern for separating the memory cells arranged in a matrix, the counter electrode 12 for each memory cell is formed. , 13 can be arranged regularly in the same matrix as the memory cells so that they face in the same direction, and can be efficiently arranged, effectively increasing the capacity per unit area and increasing the integration density. Can be improved.

[Effects of the Invention] As described above, according to the present invention, a trench isolation region is formed between each pair of memory cells on a folded bit line pair, and a memory capacitor is formed in the trench isolation region. And the memory cell of one bit line and the memory cell of the other bit line are shared to realize a memory cell array of 2 cells / 1 bit, so that a wide operation margin and a soft error can be obtained. It is possible to obtain a semiconductor memory device having high reliability with respect to the above and further highly integrated.

[Brief description of drawings]

1A and 1B are a plan view and a sectional view showing a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of the semiconductor memory device shown in FIGS. 1A and 1B. 3A, 3B and 4 are a plan view and a sectional view showing a conventional semiconductor memory device. In the figure, 1 is a P type silicon substrate, 5 is an N ⁺ type diffusion layer,
6 is an Al wiring to be a bit line, 10 is a contact hole, 11
Is the channel of the transistor, 12 and 13 are counter electrodes, 14
Is a capacitor insulating film, 15 is a polycrystalline silicon layer to be a word line, 16 is a contact hole, and 17 is a trench isolation region. Incidentally. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (5)

[Claims] 1. A plurality of rows and a plurality of columns are arranged in a matrix, each of which includes a first MOS transistor and a second MOS transistor.
A plurality of memory cells each having a capacitive element connected between one electrodes of the first and second MOS transistors, and a plurality of memory cells arranged in a plurality of rows, each of which is arranged in a corresponding row A plurality of word lines that connect the gate electrodes of the first and second MOS transistors with a plurality of columns, and the first MOS transistors of a plurality of memory cells arranged in a plurality of columns Bit lines having a true bit line connected to the other electrode of the second MOS transistor and a complementary bit line connected to the other electrode of the second MOS transistor of the plurality of memory cells arranged in the corresponding column. And a pair of electrodes forming the capacitive element of each memory cell, the pair of electrodes being located between the first and second MOS transistors of the memory cell including the capacitive element. The semiconductor memory device which is characterized in that provided in the formed element isolation trench. 2. The device isolation groove is provided in parallel with the bit line.
The semiconductor memory device according to the item. 3. A surface of the semiconductor substrate is provided with a memory cell isolation groove for communicating with the element isolation groove and isolating the memory cells, and the first and second memory cell isolation grooves are provided. One electrode of each MOS transistor is formed on the surface of the semiconductor substrate with a side end part of which is exposed in the memory cell isolation groove, and one electrode of a pair of electrodes of each capacitive element. Is electrically connected at the side end of the one electrode of the first MOS transistor of the memory cell including the capacitive element, and the other electrode is connected to the second end of the memory cell including the capacitive element. 2. The semiconductor memory device according to claim 1, wherein the one end of the MOS transistor is electrically connected to the side end. 4. The element isolation trenches are provided in parallel with the bit lines, and the memory cell isolation trenches for communicating with the element isolation trenches for separating each memory cell are formed on the surface of the semiconductor substrate. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is provided in the shape of a circle. 5. The first and second MOS of each memory cell
Each one electrode of the transistor is formed on the surface of the semiconductor substrate with a side end part of which is exposed in a part of the memory cell isolation trench that is orthogonal to the element isolation trench. One of the pair of electrodes of the capacitive element is
A second MOS transistor of the memory cell which is electrically connected at the side end portion of the one electrode of the first MOS transistor of the memory cell including the capacitive element, and the other electrode of which is the other electrode of the memory cell including the capacitive element. 5. The semiconductor memory device according to claim 4, wherein said one electrode is electrically connected at a side end portion thereof.