JPH01302851A - Structure of memory cell of semiconductor memory - Google Patents

Abstract

PURPOSE:To easily design a shape of a memory capacitor, to secure a sufficient cell capacity and to make a manufacturing process easy by forming the memory capacitor on the side of a layer which is situated above a bit line laid on a substrate. CONSTITUTION:The following are provided: an extraction electrode 51 which has a contact part 52 coming into contact with a drain region D of an access transistor 47 formed on a substrate 40 and an extraction part 53 extracted directly above a substrate face from the contact part 52 over a bit line laid on the substrate 40; a memory capacitor 59 where one part of one electrode 57 comes into contact with the extraction part 53. For example, an opening part 55 in the direction of a layer thickness is formed in a third insulating layer 54 laminated on a first insulating film and a second insulating film 48, 49 laminated on a wiring layer 47 containing a bit line; a capacitor electrode 57 and a cell plate 58 which sandwich a dielectric film 56 are formed inside the opening part 55; a memory capacitor 59 is constituted of the dielectric film 56, the capacitor electrode 57 and the cell plate 58.

Description

[Detailed Description of the Invention] [Summary] In particular, with regard to the memory cell structure of a semiconductor memory such as a DRAM having a memory capacitor, the present invention aims to facilitate the shape design of the memory capacitor and to simplify the manufacturing process. an extraction electrode having a contact portion that contacts the drain region of an access transistor formed thereon and an extraction portion that extends directly above the substrate surface from the contact portion beyond the bit line laid on the substrate; and one electrode. a memory capacitor, a portion of which is in contact with the lead-out portion.

[Industrial application field]

The present invention relates to a memory cell structure of a semiconductor memory, and particularly to a memory cell structure of a semiconductor memory such as a DRAM having a memory capacitor.

In recent years, as a result of various technological developments such as microfabrication technology, development and improvement of circuit technology and cell structure, the degree of integration of semiconductor memories, particularly DRAMs, has significantly improved. In general, an increase in the degree of integration leads to a reduction in the cell area, leading to a decrease in storage capacity and vulnerability to soft errors. There was a limit to increasing capacity.

Therefore, various cell structures that can obtain a relatively large cell capacity with a small cell area have been put into practical use, contributing to the realization of large-capacity semiconductor memories.

[Prior Art] As a conventional cell structure of this type, a trench capacitor type cell structure as shown in FIG. 4 is known. In FIG. 4, 1 is a substrate, 2 is a drain region, 3 is a source region, 4 is a word line functioning as a gate electrode, and 5 is a first
, an insulating film, 6 a separation layer, 7 a bit contact pad,
8 is a capacitor contact pad, 9 is a dielectric film, 10
1 is a cell plate, 11 is a second insulating film, and 12 is a bit line.

In the trench capacitor type cell structure, a trench is dug inside the substrate 1, and a capacitor consisting of a capacitor contact pad 8, a dielectric film 9, and a cell plate 10 is formed in the trench. Although the capacitance can be increased, the area of the depletion layer also increases as the cell capacitance increases, resulting in an increase in the amount of absorbed charge and the disadvantage that soft errors are more likely to occur.

On the other hand, as another cell structure, a stacked capacitor type cell structure as shown in FIG. 5 is also known. In FIG. 5, 21 is a substrate, 22 is a drain region, 23 is a source region, 24 is a word line functioning as a gate electrode, and 25
is a first insulating film, 26 is a separation layer, 27 is a bit contact pad, 28 is a capacitor contact pad, 29 is a dielectric film, 30 is a cell plate, 31 is a second insulating film,
32 is a bit line. The stacked capacitor type cell structure has a capacitor contact pad 28 and a dielectric film 29 above the access transistor and wiring area of the cell itself.
Since the contact area between the drain region 22 and the capacitor contact pad 28 is small, the diffusion layer region is small and the capacitor is excellent in soft error resistance. However, since the capacitor area is limited, sufficient cell capacity cannot be obtained.

[Problem to be solved by the invention]

Although the conventional stacked capacitor type cell structure has a small diffusion N SJt region and has excellent soft error resistance, the bit line 32 is located above the capacitor, so it is difficult to design the capacitor shape. However, there is a problem in that a complicated shape design is required in the extremely narrow space between the substrate 21 and the bit line 32, which reduces manufacturing reliability. Also, recent DRA
Although there is a tendency for the cell area of M to be further reduced, there are limits to capacitor shape design to obtain sufficient cell capacity in a narrow space, making it difficult to respond to recent trends. Note that sufficient cell capacity can be obtained by expanding the space between the substrate 21 and the bit line 32;
This is undesirable because it increases the line resistance and stray capacitance.

The present invention was made in view of these problems, and
The purpose is to facilitate the shape design of a memory capacitor, ensure sufficient cell capacity, and simplify the manufacturing process.

[Means to solve the problem]

In order to achieve the above object, in the present invention, a contact portion that contacts the drain region of an access transistor built on a substrate and a bit line laid out on the substrate are drawn out from the contact portion directly above the substrate surface. The memory capacitor includes a lead-out electrode having a drawn-out part, and a memory capacitor in which a part of one electrode contacts the drawn-out part.

(Function) In the present invention, the memory capacitor is formed in a layer above the bit line laid on the substrate.

Therefore, the memory capacitor can be freely designed without being restricted by the arrangement of bit lines, and the manufacturing process can be simplified while ensuring sufficient cell capacity.

〔Example] Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a structural diagram of a memory cell showing a first embodiment of the present invention.

In FIG. 1, 40 is a substrate, and an access transistor 41 having a source region S and a drain region is built into the substrate 40. In addition, 42 is a separation layer.

On the substrate 40 are a bit contact pad 43 that contacts S of the access transistor 41 and a capacitor contact pad 4 that contacts D of the access transistor 41.
4 and a word line 46 wrapped in an oxide film 45 is formed, and a bit line (not shown) is laid in the wiring layer 47 in the direction of the surface of the substrate 40.
It is connected to the bit contact pad 43 mentioned above. A first insulating film 48 and a second insulating film 49 are laminated on the wiring layer 47, and openings 50 are formed in the first insulating film 48 and the second insulating film 49 in the lamination direction. ing. An extraction electrode 51 is provided in the opening 50,
The lower part (substrate 40 side) of the extraction electrode 51 constitutes a contact portion 52 that contacts D of the access transistor 41 together with the capacitor contact pad 44 . Also,
The upper part of the extraction electrode 51 is arranged along the surface of the second insulating film 49, and this upper part is located on the upper layer side in the direction perpendicular to the surface of the substrate 40 than the wiring layer 47 including a bit line (not shown). It constitutes a drawer section 53. 54 is a third insulating layer, and an opening 55 is formed in the third insulating layer 54 in the layer thickness direction. A dielectric film 56 is disposed within the opening 55.
Capacitor electrode 57 and cell plate 58 sandwiched between
These dielectric film 56, capacitor electrode 57, and cell plate 58 constitute a memory capacitor 59. Note that the cell plate 58 is shared with other memory capacitors, and the capacitor electrode 57 is arranged along the surface of the third insulating layer 54 with a predetermined area.

According to such a configuration, a wiring layer 47 including a bit line is formed on the substrate 40, and then a first insulating film 48 and a second insulating film 49 are laminated on this wiring layer 47, and then the wiring layer 47 is formed on the substrate 40. An electrode 51 is formed, and a third insulating layer N54 is further laminated on the second insulating film 49, and a memory capacitor 59 is formed on this third insulating layer 54. Therefore, the cell capacitance of the memory capacitor 59 can be easily set to a desired size by adjusting the thickness of the third insulator N54 (indicated by H in the figure) and the area of the capacitor region. Since this adjustment is performed in a layer above the wiring layer 47, it is not affected by the arrangement of bit lines and the like. That is, the memory capacitor can be formed after forming the wiring layer including the bit line, and the manufacturing process can be simplified.

FIG. 2 is a diagram showing a second embodiment of the present invention.

In this embodiment, the same parts as those in the first embodiment are given the same reference numerals as in FIG. 1, and the explanation thereof will be omitted. In FIG. 2, reference numeral 70 denotes a bit line laid in the plane direction of the substrate 40, and a part of the bit line 70 is connected to the bit contact pad 43. Further, an opening 71 is formed in the bit line 70, and a lead-out electrode 51 protected by an insulator 72 is inserted into the opening 71. Note that the lead electrode 51 electrically connects the capacitor contact pad 44 and the memory capacitor 59 as in the first embodiment.

With such a configuration, the memory capacitor 59 can be arranged independently without being affected by the bit line 70, so the cell capacitance can be easily adjusted.
The same effects as in the first embodiment can be obtained.

FIG. 3 is a diagram showing a third embodiment of the present invention, and in this embodiment, the same components as in the first embodiment are given the same reference numerals as in the first embodiment, and their explanations will be explained below. Omitted. In FIG. 3, 80 is an opening formed in the first insulating film 48, 81 is a groove also formed in the first insulating film 48, and the inner walls of the opening 80 and the groove 81 are provided with bits. line 82
is formed. The bit line 82 runs in the horizontal direction in the figure along the groove 81 and is connected to the bit contact pad 43 at the opening 80 .

With such a configuration, the memory capacitor 59 can be arranged independently without being affected by the bit line 82, so the cell capacitance can be easily adjusted.
The same effects as in the first embodiment can be obtained.

[Effects of the Invention] According to the present invention, since the memory capacitor is formed on the upper surface layer side of the substrate rather than the bit line laid on the upper surface of the substrate, the memory capacitor can be formed without being limited by the arrangement of the bit line. The shape can be easily set and sufficient cell capacity can be ensured. Further, the memory capacitor may be formed after forming the wiring layer including the bit line, which can simplify the manufacturing process.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram showing a first embodiment of the invention, FIG. 2 is a structural diagram showing a second embodiment of the invention, and FIG. 3 is a structural diagram showing a third embodiment of the invention. , FIG. 4.5 is a diagram showing a conventional example, FIG. 4 is a diagram showing its trench capacitor type cell structure, and FIG. 5 is a diagram showing its stacked capacitor type cell structure. 40... base + anti, 41... access transistor, 51...
...Extracting electrode, 52...Contact part, 53...Extracting part, 57...Capacitor electrode (one electrode), 59
...Memory capacitor, 70.82...Bit line, D...Drain region. Patent applicant: Fujitsu Limited W-, 7 Agent: Patent attorney Sada Igeta, '21)''・^
;°'- Fig. 1 Storehouse 2 Oval of the law and order Fig. 2 Fig. 5 Osa and temperance cup Fig. 3 Fig. 4

Claims (1)

[Claims] It has a contact portion that contacts the drain region of an access transistor built on the substrate, and a lead-out portion that extends beyond the bit line laid on the substrate and extends from the contact portion directly above the substrate surface. A memory cell structure for a semiconductor memory, comprising: an extraction electrode; and a memory capacitor in which a part of one electrode contacts the extraction part.