JPH01302852A - Structure of memory cell of semiconductor memory - Google Patents

Abstract

PURPOSE:To secure a sufficient cell capacity by an easy manufacturing process without being restricted by a shape and an arrangement of a bit line by a method wherein a main part of a memory capacitor is formed on the side of a layer above the bit line. CONSTITUTION:The following are provided: a bit line 41 which is laid on 1 semiconductor substrate 42 where an access transistor TR has been formed, whose one part is connected to 1 source region S of the access transistor TR and where an opening part 44 has been formed in a prescribed part; a memory capacitor 55 which is formed on the side of a layer of a substrate face above the bit line 41, whose prescribed part A is situated inside the opening part 44 of the bit line 41 and whose inside tip part 56 is connected to a drain region D of the access transistor TR. For example, a memory capacitor 55 is constituted of a capacitor extraction electrode 52, a dielectric layer 53 and a cell plate 54; a prescribed part A corresponding to an opening part 44 of a bit line 41 of the memory capacitor 55 is situated inside the opening part 44.

Description

Detailed Description of the Invention (Summary) In particular, with regard to the memory cell structure of semiconductor memories such as DRAMs having memory capacitors, sufficient cell capacity can be achieved through a simple manufacturing process without being limited by the shape or arrangement of bit lines. The purpose of this is to provide a memory cell structure for semiconductor memory that can ensure high performance.The semiconductor memory cell structure is laid out on a semiconductor substrate in which an access transistor is built, a part is connected to the source region of the access transistor, and a hole is formed in a predetermined part. a bit line formed with a portion formed therein; and a bit line formed on the upper side of the substrate surface than the bit line, a predetermined portion internally within the opening of the bit line, and an internal tip connected to the drain region of the access transistor. and a memory capacitor.

[Industrial application field]

The present invention relates to a memory cell structure of a semiconductor memory, and particularly to a memory cell structure of a semiconductor memory such as a DRAM that includes a memory capacitor.

In recent years, as a result of various technological developments such as microfabrication technology, development and improvement of circuit technology and cell structure, the degree of integration of semiconductor memories, particularly DRAMs, has significantly improved. In general, an increase in the degree of integration leads to a reduction in the cell area, which leads to a decrease in storage capacity and vulnerability to soft errors. There was a limit to increasing capacity.

Therefore, various cell structures that can obtain a relatively large cell capacity with a small cell area have been put into practical use, contributing to the realization of large-capacity semiconductor memories.

[Conventional technology]

As a conventional cell structure of this type, a trench capacitor type cell structure as shown in FIG. 4 is known.

In FIG. 4, 1 is a substrate, 2 is a drain region, 3 is a source region, 4 is a word line functioning as a gate electrode, and 5
1 is a first insulating film, 6 is a separation layer, 7 is a bit contact pad, 8 is a capacitor contact pad, 9 is a dielectric film, IO is a cell plate, 11 is a second insulating film, and 12 is a bit line. In the trench capacitor type cell structure, a trench is dug inside the substrate 1, and a capacitor consisting of a capacitor contact pad 8, a dielectric film 9, and a cell plate 10 is formed in the trench. Although the capacitance can be increased, the depletion layer area also increases as the cell capacitance increases.
As a result, the amount of absorbed charge increases, making soft errors more likely to occur.

On the other hand, as another cell structure, a stacked capacitor type cell structure as shown in FIG. 5 is also known.

In FIG. 5, 21 is a substrate, 22 is a drain region, 2
3 is a source region, 24 is a word line functioning as a gate electrode, 25 is a first insulating film, 26 is a separation layer, 27 is a bit contact pad, 28 is a capacitor contact pad, 29 is a dielectric film, and 30 is a cell plate. , 31 is the second
, and 32 is a bit line. In the stacked capacitor type cell structure, a capacitor consisting of a capacitor contact bat 28, a dielectric film 29, and a cell plate 30 is formed above the access transistor and wiring area of the cell itself, and the drain 2M region 22 and the capacitor contact pad Since the contact area of 28 is small, the diffusion layer area is small and the soft error resistance is excellent. However, since the capacitor head capacity is limited, it is difficult to obtain sufficient cell capacity.

[Problems to be Solved by the Invention] In the conventional stacked capacitor type cell structure, the diffusion layer area is small and has excellent soft error resistance, but the structure is such that the bit cotton 32 is located above the capacitor. Therefore, when designing the capacitor shape,
There is a problem in that a complicated shape design is required in the extremely narrow space between the substrate 21 and the bit line 32, which reduces manufacturing reliability.

In addition, in recent DRAMs, there is a tendency to reduce the cell area by 2 stages, but there are limits to capacitor shape design to obtain sufficient cell capacity in a narrow space, and the recent trend difficult to respond to. Note that sufficient cell capacity can be obtained by expanding the space between the substrate 21 and the bit line 32;
In this case, the bit line 32 becomes long, which is undesirable because line resistance and stray capacitance increase.

The present invention was made in view of these problems, and
It is an object of the present invention to provide a memory cell structure of a semiconductor memory that can secure sufficient cell capacity through a simple manufacturing process without being limited by the shape or arrangement of bit lines.

[Means to solve the problem]

In order to achieve the above object, in the present invention, an access transistor is laid on a semiconductor substrate in which an access transistor is formed, a part is connected to the source region of the access transistor, and an opening is formed in a predetermined part. bit line and
a memory capacitor formed above the bit line on the substrate surface, a predetermined portion of which is internal to the opening of the bit line, and an internal tip of which is connected to the drain region of the access transistor; It consists of

[For production]

In the present invention, the main part of the memory capacitor is formed on the upper layer side of the bit line.

Therefore, the shape of the main part of the memory capacitor can be determined without conflicting with the bit line, and the manufacturing process can be facilitated while ensuring sufficient cell capacity.

〔Example] Hereinafter, the present invention will be explained based on the drawings.

1 to 3 are diagrams showing one embodiment of a memory cell structure of a semiconductor memory according to the present invention, and are examples applied to a DRAM.

First, the pattern layout of this embodiment will be explained with reference to FIG. In FIG. 1, 40 is a word line, 41 is a bit line, and these word lines 4
A large number of 0 and bit lines 41 are arranged on a substrate (semiconductor substrate) 42 so as to cross each other. A large number of access transistors TR each having a source region S and a drain region are formed in the substrate 42, and the access transistors TR are located on the back side of the bit line 41 (in the direction penetrating the paper).

Note that 43 is a bit contact hole and 44 is an opening formed in the bit line 41, and the width of the bit line 41 in the area where these bit contact holes and flowering parts are located is slightly widened to maintain strength. ing.

FIG. 2 is a diagram showing a plane taken along arrow I-1' in FIG. In FIG. 2, 42 is a substrate, TR is an access transistor built into the substrate 42, and the access transistor TR has the above-mentioned source region S and drain region. In addition, 45 is an isolation layer, 40 is a word line, 46 is an oxide film, 47 is a bit contact pad formed on the source region S, 48 is a capacitor contact pad formed on the drain region S, 49 is a first
an insulating film 41, a bit line having a flowering portion 44, 5
0 is a second insulating film, 51 is a sidewall layer, 52 is a capacitor extraction electrode, 53 is a dielectric layer, and 54 is a cell plate, and the capacitor extraction electrode 52, dielectric layer 53, and cell plate 54 are memory capacitors. 55. The memory capacitor 55 is a predetermined portion A corresponding to the opening 44 of the bit line 41, and resides inside the opening 44, and its existing tip 56 connects to the drain region of the access transistor TR via the capacitor contact pad 48. connected to.

Next, the manufacturing process of this example will be explained with reference to FIG.

A word line 4 surrounded by an oxide film 46 is formed on a substrate 42 in which an access transistor TR of 73゛a and a separation layer 45 are formed.
After forming a bit contact pad 47 and a capacitor contact pad 48, a first (7) insulating film 49 is formed by CVD 5in2 or the like.

・, 3''b Process 1 After forming a bit contact hole (indicated by a broken line in FIG. 3(a)) in the first insulating film 49 in accordance with the position of the bit contact pad 47, the bit line 41 and the A second insulating film 50 is formed.

Second insulating film 50, bit line 41, first insulating film 4
A contact hole (indicated by a broken line in FIG. 3(b)) is formed to penetrate through the capacitor contact pad 9 and reach the capacitor contact pad 48.

Note that at this time, an opening 44 is formed in the bit line 41. Then, CVD is applied to the entire surface of the second insulating film 50.
After forming S i Oz, a sidewall layer 51 is formed using RIE or the like.

A memory capacitor 55 is made by laminating the capacitor extraction electrode 52, dielectric material 53, and cell plate 54 in sequence, and the fourth insulating layer 58 and A1 wiring are formed as necessary by 10D by λ1. Form 59 and complete.

As described above, in this embodiment, the step of forming the memory capacitor 55 (step of FIG. 3(d)) is performed after the step of forming the bit line 41 (step of FIG. 3(b)). Then, the cell capacitance is adjusted by changing the layer thickness of the second insulating film 50. Therefore, the cell capacitance can be adjusted without being restricted by the shape or arrangement of the bit line 41, and sufficient cell capacitance can be obtained through an easy manufacturing process.

〔Effect of the invention〕

According to the present invention, it is possible to realize a memory cell structure of a semiconductor memory that can secure sufficient cell capacity through a simple manufacturing process without being limited by the shape or arrangement of bit lines.

[Brief explanation of the drawing]

1 to 3 are diagrams showing one embodiment of the memory cell structure of a semiconductor memory according to the present invention, FIG. 1 is a diagram showing its pattern layout, and FIG. 2 is a diagram showing the I-1' arrow in FIG. 1. FIG. 3 is a diagram illustrating the manufacturing process. 4.5 is a diagram showing a conventional example, FIG. 4 is a diagram showing its trench capacitor type cell structure, and FIG. 5 is a diagram showing its stacked capacitor type cell structure. 41... Bit line, 42... Substrate (semiconductor substrate), 44...
- Opening portion, 55...Memory capacitor, 56...Internal tip, S...Source region, D...Drain jIM, TR... ...Access transistor.

Claims (1)

[Scope of Claims] A bit line laid on a semiconductor substrate in which an access transistor is formed, a part of which is connected to the source region of the access transistor, and an opening is formed in a predetermined part; a memory capacitor formed on the upper side of the substrate surface than the bit line, a predetermined portion of which is internal to the opening of the bit line, and an internal tip of which is connected to the drain region of the access transistor; Characteristic memory cell structure of semiconductor memory.