JP2835414B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, DRAM (Dynamic Random Ac)
ESS Memory).

[0002]

2. Description of the Related Art Conventionally, demand for semiconductor devices has been rapidly expanding due to the remarkable spread of information devices such as computers. There is a demand for a semiconductor memory device that has a large-scale storage capacity and can operate at high speed. In response to this, technological developments relating to high integration, high-speed response, and high reliability of semiconductor memory devices are being promoted.

[0003] Among semiconductor memory devices, a DRAM is known as a device capable of randomly inputting and outputting storage information. In general, a DRAM includes a memory cell array section which is a storage area for storing a plurality of pieces of storage information, and a peripheral circuit section necessary for input / output with the outside. A memory cell array portion occupying a large area on a semiconductor chip is formed by arranging a plurality of memory cells for storing unit storage information in a matrix. That is, usually, a memory cell is composed of one MOS transistor and one capacitor connected thereto. This memory cell is widely known as a one-transistor one-capacitor type memory cell. The memory cell having such a configuration has a simple structure, so that it is easy to improve the degree of integration of the memory cell array, and is widely used in large-capacity DRAMs.

FIG. 9 is a plan layout diagram showing a memory cell array portion of a conventional DRAM, and FIG. 10 is a cross-sectional view (a) along XX and a cross section along YY of the memory cell array portion shown in FIG. FIG. First, a planar layout of the memory array unit will be described with reference to FIG. Word lines 103a, 103b, 103c, 103d are formed at predetermined intervals in the vertical direction. Then, in the horizontal direction, the word lines 103a, 1
A plurality of bit lines 107 are arranged at predetermined intervals in a direction orthogonal to 03b, 103c, and 103d. An element isolation oxide film 1 is interposed between two adjacent bit lines 107.
An element formation region 112 where no 02 is formed is formed. Capacitor lower electrodes (storage nodes) 108 are connected to impurity diffusion layers (not shown) located at both ends of the element formation region 112. A polypad (lead electrode) 105 is formed so as to cover a region between the word lines 103a and 103b in the element forming region 112 and a region between the word lines 103a and 103b in the bit line 107. The contact between the poly pad 105 and the silicon substrate (not shown) is a pad-substrate contact portion 110
It is performed in. Poly pad 105 and bit line 10
7 is the pad-bit line contact portion 1
11 is performed. In this way, two memory cells sharing one bit line 107 are formed in the element formation region 112.

Next, a sectional structure of a memory cell array portion of a DRAM will be described with reference to FIG. First, the XX section will be described with reference to FIG.
The memory cell array section includes a silicon substrate 101 and an element isolation oxide film 102 made of a SiO ₂ film formed on the silicon substrate 101. Element isolation oxide film 102
On top, word lines 103a, 103b, 103c, 103d made of polysilicon are formed at predetermined intervals. Word lines 103a, 103b, 103c, 1
03d, an insulating film 104a made of SiO ₂
104b, 104c and 104d are formed respectively. A poly pad 105 is formed on the element isolation oxide film 102 between the word lines 103a and 103b.
It is formed to extend over 103b. Then, an interlayer insulating film 106 made of SiO ₂ is formed so as to cover the entire surface. The poly pad 10 is provided on the interlayer insulating film 106.
A contact hole 106a for contact between bit line 107 and bit line 107 is formed. A bit line 107 is formed on the contact hole 106a and the interlayer insulating film 106, and the bit 107 and the poly pad 105 are electrically connected at a pad-bit line contact portion 111.

Next, a section taken along the line YY will be described with reference to FIG. In this cross section, an impurity diffusion layer 109 is formed between adjacent element isolation oxide films 102, and a poly pad 105 is electrically connected to the impurity diffusion layer 109. This impurity diffusion layer 109 is formed in the source / drain region of the transistor. As described above, conventionally, the impurity diffusion layer 109 forming the source / drain region of the transistor and the bit line 107 are electrically connected via the poly pad 105. The poly pad 105 is indispensable when elements are miniaturized with the integration of a semiconductor device. That is, when a memory cell is miniaturized with the integration of a semiconductor device, a word line (gate electrode)
The spacing is reduced, and the width of the impurity diffusion layer formed between the word lines is reduced accordingly. It is very difficult in the manufacturing process to form a bit line directly connected to such a narrowed impurity diffusion layer, and disadvantages such as the edge portion of the gate electrode (word line) being cut off due to mask displacement. Occurs. In such a case, forming a polypad extending over the gate electrode between the impurity diffusion layer and the bit line facilitates formation of the bit line. Thus, the poly pad becomes indispensable when the element is miniaturized. Further, conventionally, in order to increase the degree of freedom in forming a contact portion between the poly pad and the bit line, the poly pad connected to the impurity diffusion layer is drawn out onto the element isolation oxide film, and the contact portion with the bit line is formed thereon. Is formed.

[0007]

As described above, in the conventional DRAM memory cell array portion, when the element is miniaturized, the contact portion between the bit line 107 and the impurity diffusion layer 109 is formed by using the poly pad 105. Formed easily.

However, when the element is further miniaturized, the contact diameter W of the contact hole 106a becomes smaller. In this case, the depth H of the contact portion is constant. Therefore, the aspect ratio (H
/ W) is increased. When the aspect ratio is increased, it is difficult to form a contact hole, which leads to problems such as disconnection of a bit line and an increase in resistance. As a result, in the related art, when the element is miniaturized, there is a problem in that the reliability of the element is disadvantageously reduced, and the reliability of the element is reduced.

The first and second aspects of the present invention have been made in order to solve the above-mentioned problems, and a contact hole can be formed even when the contact diameter becomes smaller with miniaturization of the element. It is an object of the present invention to provide a semiconductor device which can easily ensure element reliability.

[0010]

According to the present invention, there is provided a semiconductor device comprising: a lower conductive layer formed on a main surface of a semiconductor substrate; and a lower conductive layer located on the lower conductive layer and electrically connected to the lower conductive layer. A connection layer; and an upper conductive layer located above the intermediate connection layer and electrically connected to the intermediate connection layer. The thickness of the intermediate connection layer in the connection region between the intermediate connection layer and the upper electrode layer includes the connection region between the lower conductive layer and the intermediate connection layer other than near the connection region between the intermediate connection layer and the upper conductive layer. It is formed thicker than the thickness of the intermediate connection layer in the region.

[0011]

In the semiconductor device according to the present invention, the thickness of the intermediate connection layer in the vicinity of the connection region between the intermediate connection layer and the upper conductive layer is smaller than that in the vicinity of the connection region between the intermediate connection layer and the upper conductive layer. Since it is formed thicker than the thickness of the intermediate connection layer in the region including the connection region with the intermediate connection layer,
The depth of the contact hole for connecting the upper conductive layer and the intermediate connection layer is reduced, and the aspect ratio is improved.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan layout diagram showing a memory cell array portion of a DRAM according to one embodiment of the present invention.
2 (a) and 2 (b) are a cross-sectional view (a) along XX and a cross-sectional view (Y) along YY of the memory cell array section shown in FIG. First, referring to FIG. 1, a memory cell array portion of a DRAM according to the present embodiment includes word lines 3a, 3b, 3c,
3d, bit lines 7 formed at predetermined intervals in a direction orthogonal to the word lines 3a, 3b, 3c, 3d, and an element formation region 12 formed in a predetermined region between adjacent bit lines 7, A capacitor lower electrode (storage node) 8 connected to an impurity diffusion layer (not shown) located at both ends of the element formation region 12, an element formation region between word lines 3a and 3b, and a bit between word lines 3a and 3b A polypad 5 formed to cover the line 7.

The contact between the element forming region 12 and the bit line 7 is made via the poly pad 5. That is, the element formation region 12 and the poly pad 5 are electrically connected at the pad-substrate contact portion 10, and the bit line 7 and the poly pad 5 are electrically connected at the pad-bit line contact portion 11. Here, in the memory cell array portion of the present embodiment, the bent portions 3 are provided at portions corresponding to the pad-bit line contact portions 11 of the word lines 3a and 3b.
a ₁ and 3b ₁ are formed respectively. in this way,
By forming the bent portion 3a ₁ and 3b _1, the pad - the word lines 3a at the bit line contact portion 11, 3b
The space between them is narrower than other parts.

Next, referring to FIG. 2, the memo shown in FIG.
The cross-sectional structure of the recell array will be described. First, figure
2 (a), with respect to the XX section in FIG.
explain. In this cross section, the entire surface of the silicon substrate 1 is covered with Si.
O_TwoAn element isolation oxide film 2 is formed. element
On the isolation oxide film 2, the word lines 3a, 3b,
Word lines 3a, 3b, 3 at intervals corresponding to 3c, 3d.
c, 3d are formed. Word lines 3a, 3b, 3
The insulating films 4a, 4b, 4c, 4d cover the c, 3d.
Is formed. A word line between the word lines 3a and 3b.
Poly pads 5 made of silicon are used as word lines 3a and 3b.
Formed so as to extend therethrough via insulating films 4a and 4b.
ing. Then, the entire surface is SiO_TwoInterlayer insulating film 6 made of
Are formed. The bit line 7 and the
Contact hole 6 for making contact with repad 5
a is formed. Contact hole 6a and interlayer insulation
Bit lines 7 are formed on the film 6. Bit line 7
The poly pad 5 corresponds to the pad-bit line contact portion 11.
Are electrically connected. Next, referring to FIG.
For comparison, a YY cross section of the memory cell array portion shown in FIG.
Will be described. In this cross section, between the element isolation oxide films 2
Impurities forming the source / drain region of the transistor
An object diffusion layer 9 is formed. The impurity diffusion layer 9 has poly
The pad 5 is connected, and the poly pad 5 is
It is formed to extend on the deoxidized film 2. Soshi
The contact between the bit line 7 and the poly pad 5 is
Pad-bit of poly pad 5 extending on isolation oxide film 2
This is performed at the contact contact portion 11. Where the figure
As shown in FIG. 2A, the spacing between the poly pads 5 is small.
When formed between the broken word lines 3a and 3b,
The upper surface of the pad 5 is flattened without being concave as in the prior art.
It is. That is, the poly pad 5 is formed in the meantime.
Spacing L between side portions of edge films 4a and 4b and polypad 5
Thickness T on word lines 3a and 3b₁Is 2T₁
> L to satisfy the relationship of L ₁The shape
To achieve. By doing so, the shape between the word lines 3a and 3b is formed.
The formed poly pad 5 does not become concave as
The upper surface of the repad 5 is flattened. As a result, the pad
Thickness T of poly pad 5 at bit line contact portion 11_Two
Is the thickness T of the poly pad 5 on the word lines 3a and 3b.₁
It will be formed thicker than that. This section is taken along the line YY
When viewed from the side, a cross section as shown in FIG. 2B is obtained. Real truth
In the embodiment, the pad-bit line contact portion
The thickness of the polypad 5 at 11 is made thicker than the other parts.
As a result, the contact depth H of the bit line 7 is₀Is conventional
Is reduced by increasing the thickness of poly pad 5 compared to
You. As a result, the aspect ratio (H₀/ W₀) Compared to conventional
All smaller and better. Therefore, compared to the conventional
The formation of the contact hole 6a becomes easy, and the
It is said that the disconnection and the resistance of the bit line 7, which were problems, increase.
Problems can be reduced. As a result,
Reliability can be improved as compared with the related art.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of the memory cell array portion shown in FIG. Next, the manufacturing process will be described with reference to FIGS. First, an element isolation oxide film 2 is formed on a silicon substrate 1 as shown in FIG. Word lines 3a, 3b, 3c, 3d having a pattern shape as shown in FIG. 1 are formed on element isolation oxide film 2. Word line 3
a, 3b, 3c, and 3d, respectively.
a, 4b, 4c and 4d are formed. Next, as shown in FIG. 3B, polysilicon to be the poly pad 5 is deposited on the entire surface. Then, as shown in FIG. 3C, the polysilicon is patterned so as to extend over the word lines 3a and 3b to form a poly pad 5. Next, FIG.
As shown in (d), after forming an interlayer insulating film 6 made of SiO ₂ on the entire surface, a contact hole 6a is formed. Finally, as shown in FIG. 2A, a bit line made of a WSi film is formed on the contact hole 6a and the interlayer insulating film 6 by a sputtering method.

FIG. 4 shows a DRA according to a second embodiment of the present invention.
13 is a cross-sectional view of a memory cell array section of M. FIG. Referring to FIG. 4, in the second embodiment, word lines 3a, 3b, 3
insulating films 14 formed so as to cover c and 3d, respectively.
a, 14b, 14c and 14d are formed thicker. Thereby, the insulating film 14 is provided between the word lines 3a and 3b.
a, 14b are in contact with each other and the insulating films 14a, 1
4b is embedded. By forming the poly pad 5 on such a shape, the surface of the poly pad 5 is flattened as shown in FIG. Therefore, the same effects as obtained in the first embodiment shown in FIGS. 1 and 2 can be obtained. That is, the contact depth H ₀ of the bit line 7
Is reduced in the direction of decreasing the depth, so that the aspect ratio is improved and the formation of the contact hole 6a is facilitated. As a result, problems such as poor contact between the bit line 7 and the poly pad 5 conventionally used can be reduced.

FIG. 5 is an overall plan layout diagram of the memory cell array portion shown in FIG. Referring to FIG. 5, word lines 3a and 3b and word lines 3c and 3d have bent portions 3a ₁ , 3b ₁ and 3c ₁ , 3d _{1 at} portions corresponding to both sides of pad-bit line contact portion 11, respectively. Are formed.

FIG. 6 is a plan layout diagram showing a third embodiment in which the word line pattern of the memory cell array section shown in FIG. 5 is different. Referring to FIG.
13a ₁ , 13b ₁ , 13c ₁ , 13
d ₁ is the bent portions 3a ₁ , 3b ₁ , 3c ₁ ,
Unlike 3d _1, the pad - has a shape which projects only the bit line contact portion 11 side.

FIG. 7 is a plan layout diagram showing a fourth embodiment in which the word line pattern of the memory cell array section shown in FIG. 5 is different. In the fourth embodiment, the word lines 23a, 23b, 23c, each of the bent portions 23a ₁ of the _{23d, 23b 1, 23c 1,} 23d 1 pad - the opposite side together projects not bit-line contact portion 11 side only It has a shaped shape.

FIG. 8 is a plan layout diagram showing a fifth embodiment in which the word line pattern of the memory cell array section shown in FIG. 5 is different. With reference to FIG.
In the embodiment, the pattern shapes of the pair of word lines 33a and 33b having the common element formation region 12 are different from each other. That is, the word line 33a is connected to the pad-
Even the portion corresponding to the bit line contact portion 11 does not have a bent shape, and the pad-bit line contact portion 1
The arrangement is entirely close to one side. On the other hand, the word line 33b is connected to the pad-bit line contact portion 1
1 has a bent portion 33b1 protruding at a portion corresponding to ₁ . The relationship between the word lines 33a and 33b is the same as the relationship between the word lines 33c and 33d.

With the above-described word line pattern shapes shown in FIGS. 6 to 8, the same effects as in the first embodiment shown in FIGS. 1 and 2 can be obtained.

In this embodiment, an example of application to a polypad used in a memory cell array portion of a DRAM has been described. However, the present invention is not limited to this, and other elements having a three-layer structure through a pad can be used. Applicable.

[0023]

As described above, claims 1 and 2 are as described above.
According to the invention described in (1), the thickness of the intermediate connection layer in the vicinity of the connection region between the intermediate connection layer and the upper conductive layer is set to a value other than the vicinity of the connection region between the intermediate connection layer and the upper conductive layer. By forming the intermediate connection layer thicker in the region including the connection region between the upper conductive layer and the intermediate connection layer, the depth of the contact hole for connecting the upper conductive layer and the intermediate connection layer is reduced, and the aspect ratio is improved. As a result, it has been possible to provide a semiconductor device capable of easily forming a contact hole and ensuring the reliability of the element even when the contact diameter is reduced with miniaturization of the element.

[Brief description of the drawings]

FIG. 1 is a plan layout view showing a memory cell array portion of a DRAM according to an embodiment of the present invention.

FIGS. 2A and 2B are a sectional view taken along line XX and a sectional view taken along line YY of the memory cell array unit shown in FIG.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of the memory cell array section shown in FIG.

FIG. 4 is a sectional view of a memory cell array portion of a DRAM according to a second embodiment of the present invention.

FIG. 5 is an overall plan layout diagram of the memory cell array section shown in FIG. 1;

FIG. 6 is a plan layout diagram showing a third embodiment in which the word line pattern of the memory cell array section shown in FIG. 1 is different.

FIG. 7 is a plan layout view showing a fourth embodiment in which the word lines of the memory cell array section shown in FIG. 1 have different pattern shapes;

FIG. 8 is a plan layout view showing a fifth embodiment in which the word lines of the memory cell array section shown in FIG. 1 have different pattern shapes.

FIG. 9 is a plan layout diagram showing a memory cell array section of a conventional DRAM.

10 is a cross-sectional view (a) along XX and a cross-sectional view (Y) along YY of the memory cell array section shown in FIG. 9;
It is.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation oxide film 3a, 3b, 3c, 3d, 13a, 13b, 13c, 1
3d, 23a, 23b, 23c, 23d, 33a, 33
b, 33c, 33d word lines _{3a 1, 3b 1, 3c 1} , 3d 1, 13a 1, 13
b ₁ , 13c ₁ , 13d ₁ , 23a ₁ , 23b ₁ , 23
c ₁ , 23d ₁ , 33b ₁ , 33d ₁ bent portion 4a, 4b, 4c, 4d, 14a, 14b, 14c, 1
4d insulating film 5 poly pad (lead electrode) 6a contact hole 7 bit line 8 capacitor lower electrode (storage node) 9 impurity diffusion layer 10 pad-substrate contact portion 11 pad-bit line contact portion

Claims (2)

(57) [Claims] A lower conductive layer formed on a main surface of a semiconductor substrate; an intermediate connection layer located above the lower conductive layer and electrically connected to the lower conductive layer; And an upper conductive layer electrically connected to the intermediate connection layer, wherein a thickness of the intermediate connection layer near a connection region between the intermediate connection layer and the upper conductive layer is the intermediate connection Characterized by being formed thicker than the thickness of the intermediate connection layer in a region including a connection region between the lower conductive layer and the intermediate connection layer, other than near the connection region between the layer and the upper conductive layer, Semiconductor device. 2. A connection region between the upper conductive layer and the intermediate connection layer and a connection region between the lower conductive layer and the intermediate connection layer are formed at a predetermined interval in a direction along the semiconductor substrate. The semiconductor device according to claim 1, wherein: