JPH04365375A - Semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent insulation reliability of a dielectric layer from being deteriorated by making a first electrode layer oppose a second electrode layer through the dielectric layer at a bottom surface and a side surface of a recessed portion of the first electrode. CONSTITUTION:A capacitor 10 consists of a lamination structure of a lower electrode 11, a dielectric layer 12, and an upper electrode 13. A recessed portion 25 whose depth D1 measures 2,000-5,000Angstrom is formed on a surface of the lower electrode 11. The recessed portion 25 consists of a bottom surface 26 and a side surface 27 and an upper electrode 13 is formed on a surface of the lower electrode 11 including the bottom surface 26 and the side surface 27. Then, the lower electrode 11 opposes the upper electrode 13 through the dielectric layer 12 even on the bottom surface 26 and the side surface of the recessed portion 25, and this part constitutes a capacitor. Thus the deterioration of insulation reliability of the dielectric layer 12 is prevented while maintaining the capacitance of a chargeaccmulation portion at a specified amount.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION This invention relates to a semiconductor memory device, and in particular to a dynamic random access memory (DRA).
The present invention relates to a structure capable of improving capacitor capacitance due to miniaturization of M) and a manufacturing method thereof.

0002

2. Description of the Related Art In recent years, the demand for semiconductor memory devices has been rapidly expanding due to the remarkable spread of information equipment such as computers. Furthermore, in terms of functionality, it is required to have a large storage capacity and be capable of high-speed operation. Along with this, technological development regarding higher integration, high-speed response, and high reliability of semiconductor memory devices is progressing.

Among semiconductor memory devices, DRAM is one that allows random input/output of stored information. In general, D
A RAM is composed of a memory cell array, which is a storage area that stores a large amount of stored information, and peripheral circuits necessary for input/output with the outside. FIG. 19 is a block diagram showing the configuration of a general DRAM. In this figure, DRAM50
comprises a memory cell array 51 for accumulating data signals of storage information, a row and column address buffer 52 for externally receiving address signals for selecting memory cells constituting a unit memory circuit, and a row and column address buffer 52 for receiving the address signals. A row decoder 53 and a column decoder 54 for specifying a memory cell by decoding, a sense refresh amplifier 55 for amplifying and reading a signal accumulated in a specified memory cell, and a data input/output for data input/output. Buffer 56 and data out buffer 57
and a clock generator 5 that generates a clock signal.
8.

The memory cell array 51, which occupies a large area on a semiconductor chip, is formed by arranging a plurality of memory cells in a matrix for storing unit storage information. FIG. 20 shows an equivalent circuit diagram for 4 bits of memory cells forming the memory cell array 51. The illustrated memory cell is one MOS (Metal O
The figure shows a so-called 1-transistor, 1-capacitor type memory cell that is composed of a (Xide Semiconductor) transistor and one capacitor connected to the transistor. Since this type of memory cell has a simple structure, it is easy to improve the degree of integration of the memory cell array, and it is widely used in large-capacity DRAMs.

Furthermore, DRAM memory cells can be divided into several types depending on the structure of the capacitor. FIG. 21 is a cross-sectional structural diagram of a memory cell having a typical stacked type capacitor, as shown in, for example, Japanese Patent Publication No. 60-2784. Referring to FIG. 21, the memory cell includes one transfer gate transistor and one stacked type capacitor (hereinafter referred to as a stacked type capacitor).

The transfer gate transistor includes a pair of source/drain regions 6 formed on the surface of a silicon substrate 1 and a gate electrode (word line) 4 formed on the surface of the silicon substrate with an insulating layer interposed therebetween. The stacked type capacitor includes a lower electrode (storage node) 11 that extends from the upper part of the gate electrode 4 to the upper part of the field isolation film 2, and a part of which is connected to one side of the source/drain region 6; 11, and an upper electrode (cell plate) 13 further formed on the surface. Furthermore, a bit line 15 is provided above the capacitor via an interlayer insulating layer 20.
is formed, and the bit line 15 is connected to a bit line contact portion 16.
It is connected to the other source/drain region 6 of the transfer gate transistor via. The feature of this stacked type capacitor is that by extending the main part of the capacitor to the upper part of the gate electrode and field isolation film, the opposing area between the electrodes of the capacitor is increased and the capacitance of the capacitor is ensured.

Generally, the capacitance of a capacitor is proportional to the opposing area between electrodes and inversely proportional to the thickness of the dielectric layer. Therefore, from the viewpoint of increasing capacitance, it is desirable to increase the opposing area between the electrodes of the capacitor. on the other hand,
As DRAMs become more highly integrated, the memory cell size has been significantly reduced. Therefore, the planar occupied area of the capacitor formation region also tends to be reduced. However, from the viewpoint of stable operation and reliability of DRAM as a memory device, the amount of charge that can be stored in a 1-bit memory cell cannot be reduced. In order to satisfy these contradictory constraints, various improvements have been proposed in the capacitor structure that can reduce the planar occupied area of the capacitor and increase the facing area between electrodes.

FIG. 22 shows "Symposium on
VLSI Tech. p65 (1989)”
1 is a cross-sectional structural diagram of a memory cell equipped with a so-called cylindrical stacked type capacitor published in . Referring to FIG. 22, the transfer gate transistor includes a gate electrode (word line) 4c surrounded by an insulating layer 22. Note that illustration of the source/drain regions is omitted. Further, the word line 4d is surrounded by an insulating layer 22.
and is formed on the surface of the silicon substrate 1 with a shield gate insulating film 41 interposed therebetween.
is formed on the surface of Capacitor lower electrode 11
is composed of a base portion 11a formed on the surface of the insulating layer 22 covering the surfaces of the gate electrode 4c and the word line 4d, and a cylindrical portion 11b extending vertically upward from the surface of the base portion 11a. Furthermore, a dielectric layer and an upper electrode are sequentially laminated on the surface of the lower electrode 11 (not shown). The cylindrical stacked type capacitor has not only the base portion 11a but also the cylindrical portion 11b as a charge storage region.
It is also possible to use this cylindrical portion 11b.
This makes it possible to increase the capacitance of the capacitor without increasing the planar area occupied by the capacitor. Also,
The nitride film 42 partially remains on the surface of the insulating layer 22.

Next, the manufacturing process of the memory cell shown in FIG. 22 will be explained with reference to FIGS. 23 to 28.

First, referring to FIG. 23, a shield gate insulating film 41, a shield electrode 40, word lines 4c, 4d, an insulating layer 22, and a nitride film 42 are formed in a predetermined shape on the surface of a silicon substrate 1.

Next, referring to FIG. 24, silicon substrate 1
A polycrystalline silicon layer is deposited on the surface and patterned into a predetermined shape. This forms the base portion 11a of the lower electrode 11 of the capacitor.

Furthermore, referring to FIG. 25, a thick insulating layer 43 is formed over the entire surface. Then, an opening 4 is formed in the insulating layer 43 by etching to reach the base portion 11a of the lower electrode.
form 4. Furthermore, a polycrystalline silicon layer 110b is deposited on the inner surface of this opening 44 and the surface of insulating layer 43.

Further, referring to FIG. 26, polycrystalline silicon layer 110b is selectively etched away by anisotropic etching. As a result, the lower electrode 11 of the capacitor
A cylindrical portion 11b extending vertically upward from the surface of the base portion 11a is formed, and the lower electrode 11 is completed.

Furthermore, as shown in FIG. 27, the lower electrode 1
A dielectric layer 12 and an upper electrode 13 are sequentially formed on the surface of the substrate 1 .

Furthermore, as shown in FIG. 28, after covering the entire surface of the silicon substrate 1 with an interlayer insulating layer 20, a contact hole is formed at a predetermined position, and a bit line contact portion 16 is formed inside the contact hole. Form. Thereafter, a bit line connected to the bit line contact portion 16 is formed on the surface of the interlayer insulating layer 20 (not shown).

[0016]

[Problems to be Solved by the Invention] Conventional cylindrical stacked type capacitor, base portion 11a of lower electrode 11
After forming the cylindrical portion 11b, the cylindrical portion 11b was formed on the base portion 11a. In other words, the base portion 11a and the cylindrical portion 11
b was connected to form the lower electrode 11. therefore,
At the connection part between the base part 11a and the cylindrical part 11b,
It was easy for unevenness to occur due to cavities and protrusions. When unevenness occurs, an electric field is concentrated in the area, resulting in a problem that the insulation reliability of the dielectric layer in that area deteriorates.

Furthermore, in the conventional cylindrical stacked type capacitor, the base portion 11a and the cylindrical portion 11b of the lower electrode 11 are formed in different manufacturing processes, requiring multiple film forming steps and mask patterning steps. The process was complicated.

An object of the present invention is to provide a semiconductor memory device which can prevent deterioration of insulation reliability of a dielectric layer and has a capacitor having a predetermined capacitance.

Another object of the present invention is to provide a method for manufacturing a semiconductor memory device that can prevent deterioration of insulation reliability of a dielectric layer and simplify the manufacturing process of a capacitor having a predetermined capacitance. It is.

[0020]

A semiconductor memory device according to claim 1 includes a semiconductor substrate having a main surface, first and second impurity regions formed spaced apart from each other in the vicinity of the main surface, and a first impurity region formed in the vicinity of the main surface. a first conductive layer formed on the main surface between the region and the second impurity region and forming a channel by applying a voltage to the main surface; and a second conductive layer electrically connected to the second impurity region. layer and a charge storage section. The charge storage section is electrically connected to the first impurity region and has a thickness of 300 mm.
A first electrode layer having a thickness of 0 to 8000 angstroms, a second electrode layer formed opposite to the first electrode layer, and a dielectric layer formed between the first electrode layer and the second electrode layer. ing.

[0021] The first electrode layer has a depth of 2000 to 5000 mm.
A recessed portion having a side surface and a bottom surface integrally formed with a thickness of angstroms is formed, and the first electrode layer faces the second electrode layer via the dielectric layer also on the bottom surface and side surface of the recessed portion.

A method for manufacturing a semiconductor memory device according to a second aspect includes the steps of forming a first conductive layer on the main surface of a semiconductor substrate, and forming first and second conductive layers near the main surface so as to sandwich the first conductive layer. 2
forming an impurity region; forming a second conductive layer on the main surface to be electrically connected to the second impurity region; and forming a second conductive layer on the main surface to be electrically connected to the first impurity region. , a step of forming a first electrode layer with a thickness of 3000 to 8000 angstroms, a step of etching the first electrode layer to form a recess with a depth of 2000 to 5000 angstroms, and a first electrode layer including a bottom surface and a side surface of the recess. The method includes a step of forming a dielectric layer on the surface of one electrode layer, and a step of forming a second electrode layer on the surface of the dielectric layer.

A method for manufacturing a semiconductor memory device according to claim 3 is dependent on claim 2, and includes a step of forming an adjacent first electrode layer between the step of forming the second conductive layer and the step of forming the dielectric layer. a step of forming a first electrode layer separation layer made of an insulating material at the boundary with the first electrode layer formation region where the first electrode layer is to be formed; ,
A step of forming a second electrode layer with a thickness of 3000 to 8000 angstroms, etching the first electrode layer to form a recess with a depth of 2000 to 5000 angstroms, and forming a first electrode layer on the first electrode layer separation layer. separating the layers.

[0024]

[Operation] In the semiconductor memory device according to claim 1,
A recessed portion having a bottom surface and side surfaces integrally formed is formed in the first electrode layer of the charge storage section. Therefore, since there is no connection at the boundary between the bottom and side surfaces of the recess, there is no unevenness at the boundary between the bottom and side surfaces of the recess, preventing deterioration of the insulation reliability of the dielectric layer at the boundary. can do.

[0025] Also, on the bottom and side surfaces of the recess, the first
Since the electrode layer faces the second electrode layer via the dielectric layer, it is possible to maintain the capacitance of the charge storage portion at a predetermined level even if the planar area occupied by the first electrode layer is reduced.

In the method for manufacturing a semiconductor memory device according to the second aspect, since the recess is formed in the first electrode layer by etching, the recess can be easily formed.

In the method for manufacturing a semiconductor memory device according to the third aspect, since the formation of the recess and the separation of the first electrode layer are performed at the same time, the manufacturing process can be simplified. Since there is a first electrode layer separation layer at the boundary between the adjacent first electrode layer formation area, when the first electrode layer is formed over the entire main surface of the semiconductor substrate, the first electrode layer separation layer is The thickness of the first electrode layer is smaller than that of other parts. Therefore, even if the separation of the first electrode layer and the formation of the recess are performed simultaneously, the first electrode layer can be separated before the recess reaches the first impurity region.

[0028]

EXAMPLE The reason why the thickness of the first electrode layer was set to 3000 to 8000 angstroms and the depth of the recessed portion was set to 2000 to 5000 angstroms will be explained below. Referring to FIG. 29, the planar occupied area of the lower electrode 11, which is the first electrode layer, in a submicron DRAM is, for example, 0.55×
1.35=0.743μm2. In addition, due to requirements such as overlay margin in the mask patterning process, the planar occupied area of the recess 25 is set to, for example, 0.35×0.
．． 95=0.403μm2. Here, the film thickness of the lower electrode 11 is assumed to be D2, and the depth of the recess 25 is assumed to be D1.

At this time, in view of the circuit operation requirements of the DRAM, the capacitance of the capacitor formed by the lower electrode 11 and the upper electrode (not shown) must be, for example, 30 fF or more. therefore,

[0030]

[Math 1]

Here, if D2 is larger than necessary, a step will be created between the memory cell array region and other parts, making it difficult to pattern the layer above the lower electrode 11, so it is better to make D2 as small as possible. Therefore, when the thickness of the dielectric layer is 50 angstroms, D1
≒5000 angstroms, D2≒6000 angstroms. Considering the type and thickness range of the dielectric layer, it is preferable that 2000 angstroms≦D1 ≦5000 angstroms and 3000 angstroms≦D2 ≦8000 angstroms.

[0032] Hereinafter, one embodiment of the present invention will be explained in detail using the drawings. FIG. 2 is a plan view of a memory cell array of a DRAM according to a first embodiment of the present invention, and FIG.
2 is a cross-sectional structural diagram taken along the cutting line A-A in FIG. 2. FIG. First, mainly referring to FIG. 2, a silicon substrate 1
A plurality of word lines 4a, 4 extending parallel to the row direction are provided on the surface.
b, 4c, 4d, a plurality of bit lines 15, 15, 15 extending parallel to each other in the column direction, and a plurality of memory cells MC arranged near the intersection of the word line and the bit line. . Referring to FIGS. 1 and 2, the memory cell is composed of one transfer gate transistor 3 and one capacitor 10. The transfer gate transistor 3 includes a pair of source/drain regions 6 formed on the surface of the silicon substrate 1 and a gate insulating film 5 on the surface of the silicon substrate 1 located between the source/drain regions 6.
Gate electrodes (word lines) 4b, 4c formed via
Equipped with. The periphery of the gate electrodes 4b and 4c is covered with an interlayer insulating layer 20. Further, a thick interlayer insulating layer 20 is formed on the surface of the silicon substrate 1 on which the transfer gate transistor 3 is formed. Interlayer insulation layer 20
A contact hole 14 reaching one source/drain region 6 of the transfer gate transistor 3 is formed in a predetermined region of the transfer gate transistor 3 .

The capacitor 10 has a laminated structure of a lower electrode (storage node) 11, a dielectric layer 12, and an upper electrode (cell plate) 13. The lower electrode 11 is formed on the inner surface of the contact hole 14 and on the interlayer insulating layer 2.
It is formed in contact with the surface of a nitride film (not shown) formed on the surface of 0. A recess 25 is formed on the surface of the lower electrode 11, and the depth D1 of the recess 25 is 200 mm.
The thickness is 0 to 5000 angstroms. Recess 25
consists of a bottom surface 26 and a side surface 27;
A dielectric layer 12 is formed on the surface of the lower electrode 11 including the electrode 7 . An upper electrode 13 is formed on the dielectric layer 12 . Since the lower electrode 11 faces the upper electrode 13 with the dielectric layer 12 interposed in the bottom surface 26 and side surface 27 of the recessed portion 25, these portions also constitute a capacitive portion.

As the dielectric layer 12, an oxide film, a nitride film, a composite film of an oxide film and a nitride film, a metal oxide film, or the like is used. Upper electrode 13 is formed to cover almost the entire surface of the memory cell array. Further, for the upper electrode 13, polycrystalline silicon into which impurities are introduced or a metal layer such as a high melting point metal is used. The surface of the upper electrode 13 is covered with an insulating layer 23. Then, a wiring layer 24 having a predetermined shape is formed on the surface of the insulating layer 23.

A bit line 15 is connected to the source/drain region 6 on one side of the transfer gate transistor 3. The bit line 15 is the lower electrode 1 of the capacitor 10
It is formed at a lower position than the recess 25 of No. 1. Referring again to FIG. 2, the bit line 15 is connected to the bit line contact portion 1.
6, the line width is partially increased. Further, one side of the source/drain region 6 of the transfer gate transistor 3 extends to a region below the bit line 15 in a region that is in contact with the bit line 15 . A contact with the bit line is formed by the extended source/drain region 6 and the contact portion 16 of the bit line 15 whose line width has been expanded. In this way, since the contact is formed by mutually extending the contact portions between the source/drain region 6 and the bit line 15, the bit line 15 and the pair of impurity regions 6 of the transfer gate transistor are parallel to each other. Can be configured.

Further, referring to FIG. 1, since bit line 15 is formed at a position lower than bottom surface 26 of recess 25, isolation region 18 between adjacent capacitors 10 is configured to be as narrow as possible. be able to. In other words, it is possible to expand the planar area of the bottom surface 26 of the lower electrode 11 of the capacitor 10. Therefore, the planar area occupied by the bottom surface 26 is expanded, and the side surface 2 located at the outermost periphery thereof is expanded.
By increasing the circumferential length of the capacitor 7, the capacitance of the capacitor 10 as a whole increases. As shown in FIG. 2, the planar shape of the capacitor 10 is shown as a rectangle, but this is only a schematic representation, and the capacitor 10 is actually shaped like an oblong or cylindrical shape with rounded corners. is formed.

Next, the manufacturing process of the memory cell shown in FIG. 1 will be explained using FIGS. 3 to 13.

First, as shown in FIG.
A field oxide film 2 and a channel stop region (not shown) are formed in a predetermined region on the main surface. moreover,
A thermal oxide film 5, a polycrystalline silicon layer 4 by CVD, and an oxide film 22a are sequentially formed on the surface of silicon substrate 1.

Next, as shown in FIG. 4, word lines 4a, 4b,
4c and 4d are formed. A patterned oxide film 22a remains on the surfaces of word lines 4a to 4d.

Furthermore, as shown in FIG. 5, an oxide film 22b is deposited over the entire surface of the silicon substrate 1 using the CVD method.

Furthermore, as shown in FIG. 6, the oxide film 22b
An insulating layer 22 of an oxide film is formed around the word lines 4a to 4d by performing anisotropic etching. Then, impurity ions 30 are implanted into the surface of the silicon substrate 1 using the word lines 4a to 4d covered with the insulating layer 22 as masks, and the source and
A drain region 6 is formed.

Furthermore, as shown in FIG. 7, a conductive layer such as a doped polysilicon layer or a metal layer, a metal silicide layer, etc. is formed on the surface of the silicon substrate 1.
Pattern into a predetermined shape. This causes bit line 1
5 and bit line contacts 16 are formed.

Next, as shown in FIG. 8, the silicon substrate 1
An interlayer insulating film 20 is formed on the surface. Furthermore, as shown in FIG. 9, the interlayer insulating film 20 is patterned using a photoresist and etching method to form contact holes 14 that reach the source/drain regions 6.

Further, as shown in FIG. 10, a polycrystalline silicon layer 110 having a thickness of 3,000 to 8,000 angstroms is deposited on the inner surface of the contact hole 14 and the surface of the interlayer insulating film 20 using the CVD method.

Furthermore, as shown in FIG. 11, the surface of polycrystalline silicon layer 110 is patterned using a photoresist and etching method. This separates the polycrystalline silicon layer 110 and forms the lower electrode 11 of each capacitor.

Furthermore, as shown in FIG. 12, a recess 25 is formed in the lower electrode 11 using a photoresist and etching method. Then, a dielectric layer 12 such as a nitride film is formed on the surface of the lower electrode 11.

Then, as shown in FIG. 13, the dielectric layer 1
An upper electrode 13 such as a polycrystalline silicon layer is formed on the surface of 2 using the CVD method. Thereafter, an insulating layer 23, a wiring layer 24, and the like are formed to complete the process of manufacturing a DRAM memory cell.

In the above embodiment, one recess 25 is formed in one lower electrode 11, but two or more recesses 25 may be formed in one lower electrode 11. In this way, the surface area of the lower electrode 11 can be made larger, so that even if the planar area occupied by the lower electrode 11 is reduced, the capacitance of the capacitor can be maintained at a predetermined level. Figure 14 shows
An example in which two recesses 25 are provided in one lower electrode 11 will be shown. 14 are the same as those in FIG. 1, so a description of the structure of the embodiment shown in FIG. 14 will be omitted.

Other embodiments of the invention will be described below. After the steps shown in FIGS. 3 to 8, as shown in FIG.
A capacitor isolation layer 31 made of a silicon oxide film is formed using a photoresist and etching method.

As shown in FIG. 16, interlayer insulating film 20 is patterned using photoresist and etching to form contact holes 14 reaching source/drain regions 6.

As shown in FIG. 17, a polycrystalline silicon layer 110 with a thickness of 3,000 to 8,000 angstroms is formed on the inner surface of the contact hole 14, the surface of the interlayer insulating film 20, and the surface of the capacitor isolation layer 31 using the CVD method. accumulate.

As shown in FIG. 18, polycrystalline silicon layer 1
10 is patterned using a photoresist and etching method to separate the lower electrode 11, and at the same time, a recess 25 with a depth of 2000 to 5000 angstroms, indicated by D2, is formed in the lower electrode 11. At this time, since the capacitor isolation layer 31 is present, the thickness of the polycrystalline silicon layer 110 is smaller on the capacitor isolation layer 31 than elsewhere. Therefore, the separation of the lower electrode 11 and the recess 25
Even if the formation of the lower electrode 11 is performed at the same time, the separation of the lower electrode 11 is completed before the recess reaches the source/drain region 6. Therefore, even if the separation of the lower electrode 11 and the formation of the recess 25 are performed at the same time, the contact between the source/drain region 6 and the lower electrode 11 will not be destroyed.

Next, the capacitor isolation layer 31 is removed using hydrofluoric acid or the like, and a dielectric layer 12 such as a nitride film is formed on the surface of the lower electrode 11. As a result, a structure similar to that shown in FIG. 12 is obtained. The subsequent steps are the same as those in the embodiment described earlier, so the explanation thereof will be omitted.

[0054]

Effects of the Invention In the semiconductor memory device according to the present invention, the first electrode of the charge storage section is formed with a recess whose bottom surface and side surfaces are integrally formed, and the first electrode is also formed on the bottom surface and side surfaces of the recess. The layer is arranged to face the second electrode layer with the dielectric layer interposed therebetween. Therefore, it is possible to prevent the insulation reliability of the dielectric layer from deteriorating while maintaining the capacitance of the charge storage section at a predetermined level.

In the method for manufacturing a semiconductor memory device according to the present invention, since the recesses are formed in the first electrode layer by etching, the recesses can be easily formed.
It becomes possible to facilitate the manufacturing process of a semiconductor memory device.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structural diagram taken along the cutting line A-A in FIG. 2;

FIG. 2 is a plan view of an embodiment of a semiconductor memory device according to the present invention.

FIG. 3 is a process diagram showing a first step of an embodiment of a method for manufacturing a semiconductor memory device according to the present invention.

FIG. 4 is a process diagram showing a second step of an embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 5 is a process diagram showing a third step of an embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 6 is a process diagram showing a fourth step of an embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 7 is a process diagram showing a fifth step of an embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 8 is a process diagram showing a sixth step of an embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 9 is a process diagram showing a seventh step of an embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 10 is a process diagram showing an eighth step of an embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 11 is a process diagram showing a ninth step of an embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 12 is a process diagram showing a tenth step of an embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 13 is a process diagram showing an eleventh step of an embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 14 is a sectional view of another embodiment of the semiconductor memory device according to the present invention.

FIG. 15 is a process diagram showing the first step of another embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 16 is a process diagram showing the second step of another embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 17 is a process diagram showing the third step of another embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 18 is a process diagram showing the fourth step of another embodiment of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 19 is a block diagram of a conventional DRAM.

FIG. 20 is an equivalent circuit diagram of a memory cell of a conventional DRAM.

FIG. 21 is a cross-sectional structural diagram of a memory cell including a stacked type capacitor of a DRAM showing an example of the conventional technology.

FIG. 22 is a cross-sectional structural diagram of a DRAM memory cell showing another conventional example.

23 is a process diagram showing a first step of the method for manufacturing the memory cell shown in FIG. 22; FIG.

24 is a process diagram showing a second step of the method for manufacturing the memory cell shown in FIG. 22. FIG.

25 is a process diagram showing a third step of the method for manufacturing the memory cell shown in FIG. 22; FIG.

26 is a process diagram showing a fourth step of the method for manufacturing the memory cell shown in FIG. 22. FIG.

27 is a process diagram showing a fifth step of the method for manufacturing the memory cell shown in FIG. 22. FIG.

28 is a process diagram showing a sixth step of the method for manufacturing the memory cell shown in FIG. 22. FIG.

FIG. 29 is a perspective view of the lower electrode for explaining the range of the thickness of the lower electrode and the range of the depth of the recess.

FIG. 30 is a graph for explaining the range of thickness of the lower electrode and the range of depth of the recess.

[Explanation of symbols]

1 Silicon substrate 4b, 4c Gate electrode 6 Source/drain region 11 Lower electrode 12 Dielectric layer 13 Upper electrode 15 Bit line 25 Recess 26 Bottom 27 Side

Claims (3)

[Claims] 1. A semiconductor memory device that stores information in the form of charge accumulation, comprising: a semiconductor substrate having a main surface; and first and second impurity regions spaced apart from each other in the vicinity of the main surface. and a first conductive layer formed on the main surface between the first impurity region and the second impurity region and forming a channel by applying a voltage to the main surface;
a second conductive layer electrically connected to the second impurity region; and a second conductive layer electrically connected to the first impurity region and having a thickness of 30 mm.
a first electrode layer having a thickness of 00 to 8000 angstroms, a second electrode layer formed opposite to the first electrode layer, and a dielectric layer formed between the first electrode layer and the second electrode layer. a charge storage portion comprising: a recessed portion having a depth of 2000 to 5000 angstroms and integrally formed with a bottom surface and side surfaces; In the semiconductor memory device, the first electrode layer faces the second conductive layer with the dielectric layer interposed therebetween. 2. A method for manufacturing a semiconductor memory device in which information is stored in the form of charge accumulation, comprising the steps of: forming a first conductive layer on the main surface of a semiconductor substrate; and sandwiching the first conductive layer. forming first and second impurity regions near the main surface; forming a second conductive layer on the main surface so as to be electrically connected to the second impurity region;
forming a first electrode layer having a thickness of 3,000 to 8,000 angstroms on the main surface so as to electrically connect with the first impurity region; and etching the first electrode layer to a depth of 2,000 to 8,000 angstroms. forming a 5000 angstrom recess, and forming a dielectric layer on the surface of the first electrode layer including the bottom and side surfaces of the recess;
forming a second electrode layer on the surface of the dielectric layer;
A method for manufacturing a semiconductor storage device comprising: 3. Between the step of forming the second conductive layer and the step of forming the dielectric layer, at the boundary between the first electrode layer formation area where the adjacent first electrode layer is to be formed, forming a first electrode layer separation layer made of an insulating material;
forming a first electrode layer with a thickness of 3000 to 8000 angstroms on the entire main surface so as to be electrically connected to the first impurity region; and etching the first electrode layer to a depth of 2000 to 8000 angstroms. 3. The method of manufacturing a semiconductor memory device according to claim 2, comprising the step of forming a recess of 5000 angstroms and separating the first electrode layer on the first electrode layer separation layer.