JP2750975B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a capacitor.

[0002]

2. Description of the Related Art Conventionally, among semiconductor memory devices, a DRAM (Dy
namic Random Access Memory) is known. In general, a DRAM includes a memory cell array unit which is a storage area for storing a large amount of storage information, and a peripheral circuit unit necessary for input / output with the outside. A memory cell array portion occupying a large area on a semiconductor chip is formed by arranging a plurality of memory cells for storing unit storage information in a matrix. That is, a memory cell usually has one MOS transistor and one MOS transistor connected thereto.
And a number of capacitors. This memory cell is
It is widely known as a one-transistor one-capacitor type memory cell. Since the memory cell having such a configuration has a simple structure, it is easy to improve the degree of integration of the memory cell array, and is widely used in large-capacity DRAMs.

[0003] Memory cells of a DRAM can be classified into several types according to the structure of a capacitor. Among them, the stacked type capacitor is formed so as to extend above the semiconductor substrate, so that the facing area between the electrodes of the capacitor can be increased and the capacitance of the capacitor can be increased. Stacked type capacitors are
With such features, the capacitance of the capacitor can be ensured even when the element is miniaturized with the integration of the semiconductor device. As a result, with the integration of semiconductor devices, stacked type capacitors have come to be widely used.

FIG. 21 is a sectional structural view showing a memory cell portion of a conventional semiconductor device (DRAM) having a stacked type capacitor. Referring to FIG. 21, a conventional DR
The memory cell portion of the AM includes a semiconductor substrate (silicon substrate) 1
12, source / drain regions 110 and 111 formed at predetermined intervals on main surface of silicon substrate 112 so as to sandwich channel region 113, and formed on channel region 113 via gate insulating film 109. Silicide (WSi ₂ ) forming the gate electrode
108, a polysilicon film 107 forming a gate electrode together with tungsten silicide 108, a sidewall 114 formed on a side wall portion of the gate electrode (107, 108), and a source / drain region 111 formed so as to cover the entire surface. An insulating film 101 having contact holes 101a and 101b respectively on the upper surface 110, and an extraction electrode (bit connection) electrically connected to the source / drain region 110 via the contact hole 101b.
106, a capacitor lower electrode 102a made of polysilicon electrically connected to the source / drain region 111 via the contact hole 101a, and a capacitor insulating film 104 made of SiO ₂ formed so as to cover the capacitor lower electrode 102a. And the capacitor insulating film 104
And a capacitor upper electrode 103 made of polysilicon formed so as to cover the capacitor.

[0005] Source / drain regions 110 and 111
, Channel region 113, gate electrodes 107 and 1
08 constitutes a transfer gate transistor of the memory cell. In the writing operation, signal charges corresponding to the data signal from the bit line
By transmitting a voltage to the drain region 110 and applying a voltage to the gate electrodes 107 and 108 to turn on the transfer gate transistor, the signal charge is accumulated in the capacitor lower electrode 102 a via the source / drain region 111. On the other hand, in the read operation, the signal charge accumulated from the capacitor lower electrode 102a turns on the transfer gate transistor by applying a voltage to the gate electrodes 107 and 108.
As a result, data is read from the bit line 106 via the source / drain region 110.

FIGS. 22 to 26 are cross-sectional structural views for explaining the manufacturing process (first to fifth steps) of the capacitor portion of the conventional memory cell portion shown in FIG. FIG.
Next, a description will be given of a conventional capacitor manufacturing process with reference to FIGS.

First, as shown in FIG. 22, a source / drain region 1 is formed in a predetermined region on a main surface of a silicon substrate 112.
11 is formed. After forming the insulating film 101 on the entire surface, a contact hole 101a is formed in a region of the insulating film 101 located on the source / drain region 111. Polysilicon layer 102 constituting capacitor lower electrode over the entire surface
To form A resist pattern 105 is formed on a portion of the polysilicon layer 102 where a capacitor is to be formed by using photolithography.

[0010] Next, as shown in FIG. 23, the capacitor lower electrode 102 a is formed by anisotropic etching using the resist pattern 105 as a mask.

Next, as shown in FIG.
１０５ 105 is removed. Next, as shown in FIG.
SiO so as to cover the capacitor lower electrode 102a. _TwoFrom
A capacitor insulating film 104 is formed. To cover the whole surface
Polysilicon layer (capacitor upper electrode) 103
I do.

[0010] In this manner, a capacitor constituting a conventional memory cell portion has been formed.

[0011]

As described above, conventionally, in order to increase the capacitance of the capacitor, a stacked type capacitor having a structure in which it is mounted above the silicon substrate 112 as shown in FIG. 21 is employed. Was.

However, when the semiconductor device is integrated and further miniaturized, there is a problem that it is difficult to secure a constant capacitor capacitance with the structure of FIG.

Here, as a method of increasing the capacitance of the capacitor without increasing the plane area of the capacitor, a method of increasing the height of the capacitor lower electrode 102a, a method of reducing the thickness of the capacitor insulating film 104, and a method of increasing the capacitor insulating film 10
As method 4, a method using a material having a high relative dielectric constant is also conceivable.

However, in the method of increasing the height of the capacitor lower electrode 102a, the height of the step is increased.
There is a problem that the disconnection failure of the wiring increases in a later process. Further, the method of reducing the thickness of the capacitor insulating film 104 has a problem that the dielectric strength is weakened.
Further, the method using a material having a high relative dielectric constant as the capacitor insulating film 104 has a problem that a technique for uniformly forming a stable film as compared with SiO ₂ has not been established.

As described above, conventionally, when a semiconductor device is integrated and further miniaturized, it has been difficult to secure a constant capacitor capacity without causing the various inconveniences described above.

The present invention has been made to solve the above-described problems, and does not cause the above-described various inconveniences even when elements are further miniaturized in accordance with high integration of a semiconductor device. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of securing a sufficient capacitor capacity for a semiconductor device.

[0017]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first conductive layer on a substrate; and forming a first insulating layer on the first conductive layer. Forming a resist pattern in a predetermined region on the first insulating layer; and performing anisotropic etching using the resist pattern as a mask to remove a predetermined thickness of the first insulating layer and the first conductive layer. Forming a side wall portion of the first insulating layer and a step portion of the first conductive layer, and performing a predetermined amount of side wall portion of the first insulating layer by isotropic etching using the resist pattern as a mask. Removing,
After removing the resist pattern, an insulating film is formed on the first insulating layer and the first conductive layer, and then anisotropically etched to form a sidewall portion of the first insulating layer and the first conductive layer. Forming a side wall insulating film on the side wall of the step portion;
Removing the insulating layer, anisotropically etching the first conductive layer by a predetermined thickness using the sidewall insulating film as a mask, removing the sidewall insulating film, and removing the surface of the first conductive layer. A step of forming a second insulating layer thereon; and a step of forming a second conductive layer so as to cover the second insulating layer.

[0018]

In the method of manufacturing a semiconductor device according to the first aspect, a resist pattern is formed in a predetermined region on a first conductive layer formed on a substrate and a first insulating layer on the first conductive layer. A sidewall portion of the first insulating layer and a step portion of the first conductive layer are formed by anisotropic etching as a mask, and a sidewall of the first insulating layer is isotropically etched by using a resist pattern as a mask. A portion is removed by a predetermined amount, an insulating film is formed on the first insulating layer and the first conductive layer, and then anisotropically etched to form a sidewall portion of the first insulating layer and the first conductive layer. A sidewall insulating film is formed on the side wall of the stepped portion, and then the first insulating layer is removed. The first conductive layer is anisotropically etched by a predetermined thickness using the sidewall insulating film as a mask. The membrane is removed The second insulating layer is formed on the surface of the first conductive layer, and the second conductive layer is formed so as to cover the second insulating layer. Capacitor lower electrode is easily formed.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 to 12 show a semiconductor device (DR) having a stacked type capacitor according to an embodiment of the present invention.
FIG. 14 is a cross-sectional view for describing the manufacturing process (AM to AM) in the first to twelfth steps. With reference to FIGS. 1 to 12, a description will be given of a manufacturing process of the capacitor portion of the present embodiment.

First, as shown in FIG. 1, a source / drain region 14 constituting a transfer gate transistor of a memory cell is formed in a predetermined region on a main surface of a semiconductor substrate (silicon substrate) 15. After forming the insulating layer 1 on the entire surface, a contact hole 1a is formed in a region of the insulating layer 1 located on the source / drain region 14. A polysilicon layer 2 is formed on the entire surface by a thickness equal to the height of the capacitor lower electrode finally by a CVD method or the like. An oxide film (SiO ₂ ) 5 is formed on the polysilicon layer 2. The thickness of oxide film 5 is determined by the thickness of a mask material (nitride film) when patterning the peripheral wall portion of the capacitor lower electrode in a later step. This oxide film 5 has 2
It is formed with a thickness of about 000-6000 °.

Next, as shown in FIG. 2, a resist pattern 6 is formed on the oxide film 5 located above the region where the capacitor lower electrode is to be formed, using photolithography.

Next, as shown in FIG. 3, by performing anisotropic etching using the resist pattern 6 as a mask,
The oxide film 5 other than the portion located below the resist pattern 6 and the predetermined thickness of the polysilicon layer 2 other than the portion located below the resist pattern 6 are removed. Here, similarly to the oxide film 5, the etching amount of the polysilicon layer 2 defines the width of a mask material (sidewall) at the time of patterning the capacitor lower electrode, and the polysilicon 2 for connecting between concentric peripheral walls described later. Will be determined. For this reason, the thickness (2
(Approximately 000-6000 °). If the polysilicon layer 2 is excessively etched, the height of the outer peripheral wall decreases, and the capacitance of the capacitor decreases accordingly. Therefore, it is necessary to optimize the etching amount according to the application.

Next, as shown in FIG. 4, a predetermined region on the side wall of oxide film 5 is removed by isotropic etching using resist pattern 6 as a mask. Since the amount of etching by the isotropic etching determines the distance between a plurality of peripheral walls of the capacitor lower electrode described later, the amount of isotropic etching is determined in consideration of the distance between the finally formed peripheral walls. Also need to be optimized. Also,
It is necessary to make the etching amount larger than the width of the sidewall formed on the side wall of the oxide film 5 in a later step, and to stop the etching to such an extent that the adhesion between the oxide film and the resist pattern 6 can be maintained.

Next, as shown in FIG. 5, the resist pattern 6 is removed. Next, as shown in FIG. 6, a nitride film 7 is formed so as to cover the entire surface. Since the thickness of the nitride film 7 determines the width of the peripheral wall of the capacitor lower electrode,
It is formed to have a certain thickness (2000 to 6000 °).

Next, as shown in FIG. 7, the entire surface of the nitride film 7 is anisotropically etched to form sidewalls 7b and 7b on both side walls of the oxide film 5 and on both side walls of the step portion of the polysilicon layer 2, respectively. 7a is formed.

Next, as shown in FIG. 8, the oxide film 5 is removed. Next, as shown in FIG. 9, anisotropic etching is performed using sidewalls 7a and 7b made of a nitride film as a mask, thereby forming capacitor lower electrode 2 of a stacked type capacitor consisting of two peripheral walls 2a and 2b.
(2a, 2b) are formed. This capacitor lower electrode 2
The planar shape of (2a, 2b) is as shown in FIG. During the anisotropic etching, the polysilicon layer 2 outside the peripheral wall 2a outside the capacitor lower electrode is used.
In FIG. 8 (see FIG. 8), the polysilicon layer 2 existing between the peripheral wall 2a and the peripheral wall 2b is over-etched so as not to cause etching residue.

Next, as shown in FIG. 10, the side walls 7a and 7b (see FIG. 9) made of a nitride film are removed.

Next, as shown in FIG. 11, a capacitor insulating film 4 is formed by oxidizing the surface of the capacitor lower electrode 2 (2a, 2b).

Finally, as shown in FIG. 12, a capacitor upper electrode 3 made of polysilicon is formed so as to cover the capacitor insulating film 4. As a result, the capacitor lower electrode 2 is electrically connected to the source / drain region 14.
(2a, 2b), a stacked type capacitor including the capacitor insulating film 4 and the capacitor upper electrode 3 is formed.

FIG. 13 is a plan view for explaining the relationship between the mask pattern shape used in the manufacturing process of the first embodiment shown in FIGS. 1 to 12 and the shape of the capacitor lower electrode formed using the same. FIG. 14 is a perspective view of FIG. Referring to FIGS. 13 and 14, if this mask pattern 8 is used, the process shown in FIG.
The pattern of the side wall 7a made of a nitride film as shown in FIG. That is, the formed sidewall 7a is larger than the mask pattern 8 by the thickness of the sidewall 7a. This means that, in the manufacturing method of this embodiment, when the mask pattern 8 having the same size as the mask pattern used for manufacturing the conventional stacked type capacitor shown in FIG. It means that the plane area becomes large. However, since the capacitor lower electrode 2 of the present embodiment has a shape composed of a plurality of peripheral walls shown in FIGS. 13 and 14, the surface area thereof is significantly larger than that of the conventional capacitor lower electrode shown in FIG. To increase. Therefore, even if the plane area is increased by the side wall 7a, the surface area of the capacitor lower electrode is further increased, so that the capacitor capacity can be significantly increased with the same plane area as compared with the conventional case. If necessary,
From the beginning, the mask pattern 8 may be finer by the thickness of the sidewall 7a. Thus, capacitor lower electrodes (2a, 2b) having the same plane area as the conventional capacitor lower electrode 102a shown in FIG. 26 can be formed.

FIG. 15 shows a DR to which a capacitor formed by the manufacturing process described with reference to FIGS. 1 to 12 is applied.
FIG. 3 is a cross-sectional view showing a memory cell portion of an AM. Referring to FIG. 15, this memory cell portion is
And source / drain regions 13 and 14 formed at predetermined intervals on main surface of silicon substrate 15 so as to sandwich channel region 16, and are formed on channel region 16 with gate insulating film 12 interposed therebetween. Tungsten silicide (WSi ₂ ) 11 constituting the gate electrode, polysilicon film 10 constituting the gate electrode together with tungsten silicide 11, sidewall 17 formed on the side wall portion of polysilicon film 10 and tungsten silicide 11, and An insulating layer 1 having contact holes 1a and 1b on source / drain regions 14 and 13, respectively, and an extraction electrode (electrically connected to source / drain region 13 via contact hole 1b) Bit line) 9 through the contact hole 1a. A capacitor lower electrode 2 having two peripheral walls 2a and 2b, and a capacitor insulating film 4 formed to cover the capacitor lower electrode 2; And a capacitor upper electrode 3 formed on the substrate. As described above, by applying the capacitor structure formed by the manufacturing method of the present embodiment to the DRAM, even if the element is further miniaturized with the high integration of the semiconductor device, various inconveniences as in the prior art are obtained. , Sufficient capacitor capacity can be ensured.

FIG. 16 is a plan view for explaining the relationship between the mask pattern shape used in the method of manufacturing the stacked type capacitor structure according to the second embodiment of the present invention and the shape of the capacitor lower electrode formed thereby. FIG.
FIG. 7 is a perspective view of FIG. Referring to FIGS. 16 and 17, mask pattern 2 having a hole at the center as described above
If the same manufacturing process as that of the first embodiment shown in FIGS. 1 to 12 is performed using FIG.
It is possible to form the capacitor lower electrode 22 having the peripheral walls 22a, 22b, 22c, 22d. That is, when the mask pattern 28 having a hole at the center of the second embodiment is used, the planar shape of the side walls 7a and 7b of the first embodiment shown in FIG. 9 is changed as shown in FIG. Four peripheral wall-like side walls 27a, 27
b, 27c and 27d can be formed. By doing so, the capacitance of the capacitor can be further increased. As shown in FIG. 17B, the capacitor lower electrode 22 formed by the manufacturing method of the second embodiment has an outermost peripheral wall 22a and an innermost peripheral wall 22a.
d decreases, and the second peripheral wall 22c and the third peripheral wall 22b from the inside increase.

FIG. 18 is a plan view for explaining the relationship between the shape of the mask pattern used in the method of manufacturing a stacked capacitor according to the third embodiment of the present invention and the shape of the capacitor lower electrode to be formed. Referring to FIG.
When the circular mask pattern 38 is used, the formed peripheral side walls 37a and 37b are also circular, and the peripheral walls 32a and 32b of the capacitor lower electrode are also circular. Thus, it is possible to effectively prevent electric field concentration occurring at a corner when the capacitor lower electrode is square.

FIG. 19 is a plan view for explaining the relationship between the shape of the mask pattern used in the method of manufacturing the stacked type capacitor according to the fourth embodiment of the present invention and the shape of the capacitor lower electrode to be formed. Referring to FIG.
In the fourth embodiment, four circular peripheral sidewalls 47a, 47b, 47c, 47d are formed by using a circular mask pattern having a circular hole in the center.
Can be formed, and as a result, the four peripheral walls 42a,
A capacitor lower electrode having 42b, 42c and 42d can be formed. As a result, the electric field concentration can be reduced as in the third embodiment.

FIG. 20 is a plan view for explaining the relationship between the shape of a mask pattern used in the method of manufacturing a stacked capacitor according to the fifth embodiment of the present invention and the shape of a capacitor lower electrode to be formed. Referring to FIG.
By using the mask pattern 58 having a shape corresponding to the blank space of the integrated circuit in this manner, the peripheral wall-like side walls 57a and 57b corresponding to the shape can be formed, and as a result, the peripheral wall 5 corresponding to the shape can be formed.
A capacitor lower electrode having 2a and 52b can be formed. In the fifth embodiment, in the portion corresponding to the very fine mask pattern portion 58a of the mask pattern 58, the side wall 57 reflecting the shape thereof is used.
b cannot be formed. This is because the oxide film 5 completely disappears when the oxide film 5 is isotropically etched in the step shown in FIG. However, if any oxide film 5 remains in the step shown in FIG. 4 as in the mask pattern portion 58b of the mask pattern 58, the side wall 57b is formed along the linear oxide film 5, so that FIG. The inner peripheral wall 52b having the shape as shown in FIG. As in the fifth embodiment, it is possible to form capacitor lower electrodes of various shapes using blank spaces of an integrated circuit, even if they are not circular or square.

[0037]

As described above, according to the first aspect of the present invention, the first conductive layer and the first insulating layer are formed on the substrate, and the predetermined region on the first insulating layer is formed. After a resist pattern is formed, anisotropic etching is performed using the resist pattern as a mask. As a result, the first insulating layer and the predetermined thickness of the first conductive layer other than the portion located below the resist pattern are removed, and the side wall portion of the first insulating layer and the step portion of the first conductive layer are removed. Is formed and isotropically etched using the resist pattern as a mask to remove a predetermined region of the side wall portion of the first insulating layer. After removing the resist pattern, the side wall portion of the first insulating layer and the first region are removed. Forming a side wall insulating film on the side wall of the step portion of the conductive layer;
The first conductive layer is anisotropically etched by a predetermined thickness using the side wall insulating film as a mask, the side wall insulating film is removed, and the second insulating layer is formed on the surface of the first conductive layer. By forming a layer and forming the second conductive layer so as to cover the second insulating layer, a capacitor lower electrode composed of a plurality of peripheral walls is formed. Even when the number of elements is increased and the elements are further miniaturized with the increase in the degree of integration of the semiconductor device, a sufficient capacitor capacity can be ensured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a first step of a manufacturing process of a semiconductor device (DRAM) having a stacked type capacitor according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a second step of a process for manufacturing a semiconductor device (DRAM) having a stacked type capacitor according to one embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a third step in the process of manufacturing a semiconductor device (DRAM) having a stacked type capacitor according to one embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a fourth step in the process of manufacturing a semiconductor device (DRAM) having a stacked type capacitor according to one embodiment of the present invention.

FIG. 5 is a cross-sectional view for explaining a fifth step in the process of manufacturing a semiconductor device (DRAM) having a stacked type capacitor according to one embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining a sixth step in the process of manufacturing a semiconductor device (DRAM) having a stacked type capacitor according to one embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining a seventh step in the process of manufacturing a semiconductor device (DRAM) having a stacked type capacitor according to one embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining an eighth step in the process of manufacturing a semiconductor device (DRAM) having a stacked type capacitor according to one embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a ninth step of a process for manufacturing a semiconductor device (DRAM) having a stacked type capacitor according to one embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a tenth step of a process for manufacturing a semiconductor device (DRAM) having a stacked capacitor according to an embodiment of the present invention.

FIG. 11 is a sectional view illustrating an eleventh step of a process for manufacturing a semiconductor device (DRAM) having a stacked type capacitor according to an embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining a twelfth step of the process for manufacturing a semiconductor device (DRAM) having a stacked type capacitor according to one embodiment of the present invention.

FIG. 13 is a plan view for explaining the relationship between the mask pattern shape used in the manufacturing process of the first embodiment shown in FIGS. 1 to 12 and the shape of the capacitor lower electrode to be formed.

14 is a perspective view of the mask pattern and the shape of a capacitor lower electrode shown in FIG. 13;

FIG. 15 is a cross-sectional view showing a memory cell portion of a DRAM to which a capacitor formed by the manufacturing process shown in FIGS. 1 to 12 is applied;

FIG. 16 is a plan view illustrating the relationship between the shape of a mask pattern used in a method of manufacturing a stacked type capacitor according to a second embodiment of the present invention and the shape of a capacitor lower electrode formed.

FIG. 17 is a perspective view of a mask pattern and a capacitor lower electrode shown in FIG. 16;

FIG. 18 is a plan view illustrating a relationship between a mask pattern shape used in a method of manufacturing a stacked type capacitor according to a third embodiment of the present invention and a capacitor lower electrode shape to be formed.

FIG. 19 is a plan view illustrating a relationship between a mask pattern shape used in a method of manufacturing a stacked capacitor according to a fourth embodiment of the present invention and a capacitor lower electrode shape to be formed.

FIG. 20 is a plan view illustrating a relationship between a mask pattern shape used in a method of manufacturing a stacked type capacitor according to a fifth embodiment of the present invention and a capacitor lower electrode shape to be formed.

FIG. 21 is a cross-sectional view showing a memory cell portion of a conventional semiconductor device (DRAM) having a stacked type capacitor.

FIG. 22 is a cross-sectional view for describing a first step of the manufacturing process of the capacitor portion of the conventional DRAM shown in FIG. 21.

FIG. 23 is a cross-sectional view for describing a second step of the manufacturing process of the capacitor portion of the conventional DRAM shown in FIG. 21.

24 is a cross-sectional view for describing a third step of the manufacturing process of the capacitor portion of the conventional DRAM shown in FIG. 21.

25 is a cross-sectional view for describing a fourth step of the manufacturing process of the capacitor portion of the conventional DRAM shown in FIG. 21.

26 is a cross-sectional view for describing a fifth step of the manufacturing process of the capacitor portion of the conventional DRAM shown in FIG. 21.

[Explanation of symbols]

1: Insulating layer 1a, 1b: Contact hole 2: Polysilicon layer (capacitor lower electrode) 2a, 2b: Peripheral wall 3: Capacitor upper electrode (polysilicon layer) 4: Capacitor insulating film (SiO ₂ ) 5: Oxide film 6: Resist pattern 7: nitride film 7a, 7b: sidewall 8: mask pattern 9: extraction electrode (bit line) 10: gate electrode (WSi) 11: gate electrode (polysilicon film) 12: gate insulating film 13: source / drain Region 14: source / drain region 15: semiconductor substrate (silicon substrate) 16: channel region 22: capacitor lower electrode 22a, 22b, 22c, 22d: peripheral wall 27: nitride film 27a, 27b, 27c, 27d: sidewall 28: mask Pattern 32a, 32b: Peripheral wall 37a, 37b: Side wall 3 : Mask pattern 42a, 42b, 42c, 42d: peripheral wall 47a, 47b, 47c, 47d: sidewall 48: mask pattern 52a, 52b: peripheral wall 57a, 57b: sidewall 58: mask pattern , The same or corresponding parts.

Claims (1)

(57) [Claims] A step of forming a first conductive layer on a substrate; a step of forming a first insulating layer on the first conductive layer; and a resist in a predetermined region on the first insulating layer. Forming a first insulating layer by performing anisotropic etching using the resist pattern as a mask to remove the first insulating layer and a predetermined thickness of the first conductive layer; Forming a sidewall portion of the first insulating layer and a step portion of the first conductive layer; and removing a predetermined amount of the sidewall portion of the first insulating layer by isotropic etching using the resist pattern as a mask. Removing the resist pattern, forming an insulating layer on the first insulating layer and the first conductive layer, and then performing anisotropic etching, thereby forming a sidewall portion of the first insulating layer, The side of the step portion of the first conductive layer Forming a sidewall insulating film, removing the first insulating layer, anisotropically etching the first conductive layer by a predetermined thickness using the sidewall insulating film as a mask, Removing the sidewall insulating film; forming a second insulating layer on the surface of the first conductive layer; and forming a second conductive layer so as to cover the second insulating layer. A method for manufacturing a semiconductor device, comprising: