JPS6132466A - Semiconductor ic device - Google Patents

Abstract

PURPOSE:To improve the dielectric strength of an insulation film provided in a fine hole, by a method wherein the corner of a fine hole or a fine groove provided in a semiconductor substrate is formed smoothly. CONSTITUTION:A heat treatment mask 15 is formed on insulation films 3 and 4A which serve as semiconductor element forming regions in order to form a field insulation film. The mask 15 is formed by partly covering the upper part of a conductive layer 4 in such a manner that the corner of the fine hole 2 in the part other than the connection of a capacitor element for information accumulation with a switching element becomes smooth, and that the insulation film at that part is formed more thickly. Thereafter, the field insulation film 5 is formed on heat treatment, using the mask 15. Oxygen is introduced by heat treatment into the corner of the fine hole 2 at a superposition with the field insulation film 5 in this process. Thereby, the accute corners of the fine hole 2 are oxidized into smooth corners 2A and 2B. Further, the insulation film 3 at the corners 2A and 2B is formed more thickly than the other part.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technique for preventing deterioration of the dielectric strength voltage of an insulating film, and particularly to a technique for preventing deterioration of the dielectric strength voltage of an insulating film used in a semiconductor integrated circuit device. It relates to techniques that are effective when applied to

[Background Art] A semiconductor integrated circuit device (hereinafter referred to as DRAM) is equipped with a dynamic random access memory in which a series circuit of an information storage capacitive element and a switching element is used as a memory cell.
[Dynamic Random 8cces Me]
In order to create a large information rut,
There is a trend toward higher integration.

Therefore, a three-dimensional information storage capacitive element is constructed by providing a pore formed by an anisotropic etching technique on the main surface of a semiconductor substrate, and providing an insulating film along the pore and a conductive layer on top of the insulating film. A technique is known to improve the degree of integration of DRAM by reducing the planar area of memory cells (Japanese Patent Publication No. 58-1989).
12739).

However, as a result of experiments and studies on this technology, the present inventor found that since the corners of the pores are formed in an acute-angled shape, electric fields are likely to occur at the corners, and that the capacitive element for information storage is T that the dielectric strength voltage of the insulating film is extremely low
I found 7 IA elephants.

According to the experimental results of the present inventors, the insulating film of the information storage capacitor element which is three-dimensionally depleted is 30 to 40[%] f! i! I was unable to obtain a dielectric strength of 7 degrees.

Due to the low dielectric strength, the insulating film of the information storage capacitive element is easily destroyed, and if it is destroyed.

A short circuit occurs between the semiconductor substrate held at a predetermined potential and the conductive layer held at a different predetermined potential, which causes the electrical charge that is stored information to disappear, reducing the electrical reliability of the DRAM. This causes a problem.

[Object of the Invention] An object of the present invention is to provide technical means capable of improving the dielectric strength voltage of an insulating film used in a semiconductor integrated circuit device.

Another object of the present invention is to provide technical means that can improve the electrical reliability of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

In other words, by forming the corners of the pores or grooves provided in the semiconductor substrate into smooth shapes, electric field concentration at the corners can be reduced, so that the dielectric strength voltage of the insulating film provided in the pores can be reduced. can be improved.

As a result, the electrical reliability of the semiconductor integrated circuit device can be improved.

Hereinafter, the configuration of the present invention will be explained along with another embodiment as applied to a DRAM employing the halted bit line method.

[Example] FIG. 1 is a diagram illustrating the structure of an example of the present invention.
2 is a plan view of a main part of a memory cell of a RAM, and FIG. 2 is a sectional view taken along the line 11-11 in FIG. 1. FIG. In FIG. 1, insulating films other than the field insulating film provided between each conductive layer are not shown in order to make the structure easier to understand.

In addition, in all the times in the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations will be omitted.

In FIGS. 1 and 2, reference numeral 1 denotes a semiconductor substrate made of P-type single crystal silicon, which is used to configure a DRAM.

A pore 2 is a region for forming an information storage capacitive element, and is provided on the main surface of the semiconductor substrate l, extending inward from the main surface. Is this pore 2 information? ? This is for configuring a volumetric volume element three-dimensionally. That is, the pores 2 are for reducing the planar area of the information storage capacitive element on the semiconductor substrate l and improving the degree of integration of the DRAM.

Then, the pore 2 is formed at corners 2A, 2B, and 2 other than the connecting portion between the information storage capacitive element and the switching element described later.
c is formed in a smooth shape. The corner portion 2A is formed with this smooth shape.

2B and 2C are for improving the dielectric strength voltage of the insulating film.

Reference numeral 3 denotes an insulating film, which is provided at least along the pore 2 and above the main surface of the semiconductor substrate l. This insulating film 3 is
This is for configuring an S-type information storage capacitive element.

This insulating film 3 is formed so that the film thickness at the tSS2O corners 2A and 2B is thicker than at other parts.

Reference numeral 4 denotes a conductive layer, which is provided above the insulating film 3 so as to fill the pore 2 . This conductive layer 4 is adapted to be applied with a predetermined voltage, and is used to constitute a MiS type information storage capacitive element.

The information storage capacitive element C mainly includes a semiconductor substrate 1,
It is composed of pores 2, an insulating film 3, and a conductive layer 4. This information storage capacitive element C has a conductive layer 4 of, for example, 5 [
A voltage of about 100% is applied t7 to form a depletion region extending from the main surface of the semiconductor substrate 1 to the inside thereof through the insulating film 3.
, charges that become information transmitted from the bit line are accumulated in the depletion region via a switching element to be described later.

This information storage capacitive element C is particularly suitable for the corner 2B of the pore 2.
Since it is formed in a smooth shape, electric field concentration can be reduced and its dielectric strength can be improved. Furthermore, in particular, the insulating film 3 formed at the corner 2B is
Since it is formed with a thicker film thickness than other parts, its dielectric strength can be improved.

4A is an insulating film provided on the conductive layer 4 so as to cover it.

Reference numeral 5 denotes a semiconductor substrate 1 so as to be located between predetermined memory cells and a peripheral port 1 (not shown), for example, a semiconductor element forming region (active region) constituting an address selection circuit, a reading circuit, a writing circuit, etc. A field insulating film (insulating film for element isolation) provided on the upper main surface of the
This is to electrically separate them.

A DRAM memory cell is surrounded and defined by a field insulating film 5 such that a pair of patterns repeat in the direction in which a bit line (to be described later) extends.

Then, the field insulating film 5 and the pores 2
are provided in a superimposed manner.

Reference numeral 6 denotes a connection hole, which is provided by removing the insulating film 4A above the conductive layer 4. This connection hole 6 is for electrical connection with a conductive plate provided above.

A conductive plate 7 is electrically connected to the conductive layer 4 through the connection hole 6, and is provided on the field insulating film 5 and the insulating film 4A in areas other than the switching element formation region.

This conductive plate 7 is for applying a predetermined voltage to the conductive layer 4.

The conductive plate 7 is formed by the first conductive layer forming step in the manufacturing process, and is made by, for example, diffusing phosphorus into a polycrystalline silicon film using chemical vapor deposition (hereinafter referred to as CVD) technology. Form using.

7A is an insulating film, which is provided to cover the conductive plate 7. This insulating film 7A is for electrically separating the conductive plate 7 and the word line provided above it.

Reference numeral 8 denotes an insulating film, which is provided on the upper part of the main surface of the semiconductor substrate 1 in the switching element formation region. This insulating film 8 is mainly used to constitute a gate insulating film of the MISFET.

Reference numeral 9 denotes a conductive layer, which is provided above the insulating film 8. This conductive layer 9 is for configuring the gate electrode of the MISFET.

A conductive layer 10 is electrically connected to and integrated with the conductive layer 9 in the column direction, and is provided extending over the insulating film 7A in the column direction. This conductive layer IO is for forming a word line WL.

The conductive layers 9 and 10 are formed in the second conductive layer forming step in the manufacturing process, and are formed using, for example, a polycrystalline silicon film by CVD technology. Further, in order to reduce the resistance value and improve the speed of information reading and writing operations, it may be formed of a high melting point metal film, a silicide film, or the like. As the high melting point metal film, for example, molybdenum is used.

Tungsten, titanium, and tantalum may be used, and silicides of these may be used as the silicide film.

Reference numeral 11' denotes an n-type semiconductor region, which is provided on the main surface of the semiconductor substrate 1 on both sides of the conductive layer 9. This semiconductor region 11 is used as a source region or a drain region, and is used as a MISFET. It is for configuring.

MIS, which serves as a switching element for DRAM memory cells
FETQ mainly uses a semiconductor substrate l.

Conductive layer 9. It is composed of an insulating film 8 and a pair of semiconductor regions ll.

Memory cell M includes information storage capacitive element C and MISFET
It is composed of Q.

Reference numeral 12 denotes an insulating film, which is provided to cover the conductive layers 9 and 10. This insulating film 12 is for electrically separating the conductive layers 9 and 10 from the bit lines provided above them. The insulating film 12 may be, for example, a phosphor silicate glass film that can be subjected to glass flow.

Reference numeral 13 denotes a connection hole, which is provided by removing the insulating films 8 and 12 above a predetermined semiconductor region ll.

This connection hole 13 is for electrically connecting the semiconductor region 11 and a bit line provided above the insulating film 12.

14 is a conductive layer, which connects the semiconductor region 1 through the connection hole 13.
1 and extending in the row direction above the insulating film 12. This conductive layer 14 is connected to the bit line B L
It is for configuring.

The conductive layer 14 is formed in the third conductive layer forming step in the manufacturing process, and is formed using, for example, an aluminum film using a vapor deposition technique.

Next, a specific manufacturing method of this example will be explained.

3 to 5 are sectional views of main parts of a DRAM memory cell in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention.

First, a P- type semiconductor substrate 1 is prepared.

Then, a pore 2 is formed in the main surface portion of the semiconductor substrate 1 in the information storage capacitive element formation region. This is formed using, for example, an anisotropic etching technique. Since the anisotropic etching technique is not completely directional, the bottom corner 2C of the pore 2
is formed to have a gentler shape than the acute-angled shape of the main surface of the semiconductor substrate l.

Thereafter, an insulating film 3 is formed over the main surface of the semiconductor substrate 1. This insulating film 3 is formed of, for example, a silicon oxide film using a thermal oxidation technique so that it can be formed on the upper main surface of the semiconductor substrate l along the pores 2. Furthermore, in order to improve the amount of charge storage in the information storage capacitor, the silicon oxide film and C
Silicon nitride film and other high dielectric constant insulating films using VD technology,
For example, it may be formed by combining tantalum oxide.

Then, as shown in FIG. 3, so as to fill the pores 2,
A conductive layer 4 is formed on the insulating film 3 in the area where the information storage capacitive element is formed.
form. This is formed, for example, by diffusing phosphorus into a polycrystalline silicon film using CVD technology.

After the process shown in FIG.
form. This insulating film 4A is formed using, for example, a silicon oxide film using a thermal oxidation technique. Then, in order to form a field insulating film, a heat treatment mask 15 is placed over the insulating film 3.4A, which will be a semiconductor element formation region. form. This mask 15 is formed using, for example, a silicon nitride film by CVD technology so as to be kept at a high temperature.

The mask 15 is formed so that the corners of the pore 2 other than the connecting portion between the information storage capacitive element and the switching element have a gentle shape, and the insulating film is formed to have a large thickness in that part. It is formed to cover a part of the upper part of the conductive layer 4.

Thereafter, heat treatment is performed using a mask 15 to form a field insulating film 5 as shown in FIG. In the step of forming this field insulating film 5.

Oxygen is introduced into the corners of the pores 2 in the portion overlapped with the field insulating film 5 by heat treatment. by this,
The sharp corners of the pores 2 are oxidized to form gentle corners 2A and 2B (see FIG. 1). Further, the insulating film 3 at the corner portions 2A and 2B is formed to have a thicker thickness than the other portions.

After the step shown in FIG. 4, the mask 15 is removed.

#l! of a predetermined upper part of the conductive layer 4! 1 edge film 4A is removed to form a connection hole 6.

Thereafter, a conductive plate 7 is formed so as to be electrically connected to the conductive layer 4 through the connection hole 6, and as shown in FIG. 5, an insulating film 7A covering the conductive plate 7 is formed.

After the process shown in FIG. 5, a normal DRAM manufacturing process is performed, and as shown in FIGS. 1 and 2, the insulating film 8.
A conductive layer 9, an IO1 semiconductor region 11, an insulating film 12, a connection hole 13, and a conductive layer 14 are formed.

Through these series of manufacturing steps, the DRAM of this embodiment is completed. Note that, after this, a treatment process such as a protective film may be performed.

[Effects] As explained above, according to the novel technical means disclosed in this application, the following effects can be obtained.

(1) By forming pores and forming a field insulating film so as to overlap the pores, oxygen is introduced in the heat treatment process of the field insulating film, so the pores in the overlapped area The corners of can be formed into a smooth shape.

(2) According to (1) above, the thickness of the insulating film formed at the corners of the smooth shape can be increased.

(3) According to (1) above, the corners of the pores in areas other than the connection between the capacitive element and the switching element can be formed in a smooth shape, reducing electric field concentration and increasing the dielectric strength of the insulating film. can be improved.

(4) According to (2) above, the insulating film formed at the corner of the pore in the part other than the connection part between the capacitive element and the switching element can be formed with a thicker film thickness than in other parts. Therefore, the dielectric strength voltage of the insulating film can be improved.

(5) According to (3) and (4) above, the dielectric breakdown voltage of the insulating film can be improved, so the electrical reliability of the semiconductor integrated circuit device can be improved.

As above, the invention made by the present inventor has been specifically explained with reference to the above embodiments, but the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist thereof. Of course it is possible.

1. For example, in the embodiment described above, the present invention is applied to a DRAM that uses a hole-put pit line method.
It may also be applied to AM.

Further, in the above embodiments, the present invention is applied to a DRAM, but the present invention is not limited thereto, and can be applied to a semiconductor integrated circuit device in which a semiconductor element is formed using pores. In the embodiment, an example in which the present invention is applied to a pore has been described, but the present invention may also be applied to a narrow groove.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the structure of an embodiment of the present invention.
FIG. 2 is a plan view of a main part of a RAM memory cell; FIG. 2 is a sectional view taken along the line II-II in FIG. 1; FIGS. 3 to 5 are for explaining a manufacturing method of an embodiment of the present invention FIG. 3 is a cross-sectional view of a main part of a DRAM memory cell in each manufacturing process. In the figure, ■...Semiconductor substrate, 2...Pore, 2A, 2B
, 2C... Corner, 3.4A, 7A, 8, 12... Insulating film, 4.9.10.14... Conductive layer, 5... Field insulating film, 6... Connection hole , 7... Conductive plate, 11... N1 type semiconductor region, 13... Connection hole,
15...Mask, C...Capacitive element for information storage, Q.
...MISFET Figure 1 Figure 2 Figure 3 Figure 5

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit device having a series circuit of a capacitive element formed using a pore or a narrow groove and a switching element, the capacitive element other than the connecting part between the capacitive element and the switching element is A semiconductor integrated circuit device characterized in that the corners of the holes or narrow grooves are formed in a smooth shape. 2. The capacitive element includes a semiconductor substrate, a pore or groove provided on the main surface of the semiconductor substrate, an insulating film provided along the pore or groove, and a conductive layer provided above the insulating film. A semiconductor integrated circuit device according to claim 1, characterized in that the semiconductor integrated circuit device is constructed by: 3. Claim 2, characterized in that the insulating film provided at the smooth-shaped corners of the pores or narrow grooves is formed to have a thicker film thickness than other parts. The semiconductor integrated circuit device described in . 4. The corner portions of the pores or narrow grooves are formed into smooth shapes in the step of forming an insulating film for isolation between semiconductor devices, which electrically isolates semiconductor devices. Each of the semiconductor integrated circuit devices described in Items 1 to 3. 5. Claims 1 to 4, characterized in that the pores or narrow grooves are formed before the step of forming an inter-element isolation insulating film that electrically isolates semiconductor elements.
Each semiconductor integrated circuit device described in .