JPH03230561A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To secure capacitor capacitance without difficulty in forming a pattern of a lower electrode even if a memory cell size has been reduced by forming a high melting point metal silicide layer having a plurality of protrusions which extend upward on a first conductive film constituting a capacitance means. CONSTITUTION:A semiconductor device includes a polysilicon film 7 which is connected to an impurity diffusion layer 6 and formed on an element separation oxide film 2 and an insulating film 5, a titanium silicide film 8b having a plurality of protrusions, a silicon nitride film 9 and a polysilicon film 10 formed on the film 9. Since the titanium silicide film 8b formed on the polysilicon film 7 thus has a plurality of protrusions, a surface area increases compared to a flat lower electrode. Therefore an area which can be utilized as a capacitor area increases, resulting in an increase in capacitor capacitance. Thus even if a memory cell size has been reduced due to integration of a DRAM, capacitor capacitance sufficient for satisfying needs for stable operation of the DRAM and reliability can be secured without difficulty in forming a pattern of the lower electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device and a method for manufacturing the same that are capable of random input/output of arbitrary storage information and are suitable for high integration. It relates to its manufacturing method.

[Prior Art] Conventionally, among semiconductor devices, DRAM (Dynamic
andom Access Mem.

ry) is known for boat fishing. The integration density of DRAM has quadrupled in the past three years, and it has already transitioned from IM to 4M. In general, a DRAM is composed of a memory cell array, which is a storage area that stores a large amount of storage information, and peripheral circuits necessary for input/output with the outside.

FIG. 3 is a cross-sectional view showing a memory cell of a conventional DRAM. Referring to FIG. 3, a memory cell includes a silicon substrate 1, an element isolation oxide film 2 for element isolation formed on the silicon substrate 1, and an element isolation oxide film 2 formed on the silicon substrate 1 adjacent to the element isolation oxide film 2. an impurity diffusion layer 6 formed on a silicon substrate; a gate electrode 4 formed on a region adjacent to the impurity diffusion layer 6 of the silicon substrate with a gate oxide film 3 interposed therebetween; An insulating film 5 for insulation, a capacitor lower electrode 17 connected to the impurity diffusion layer 6 and formed on the element isolation oxide film 2 and the insulating film 5, and a capacitor dielectric formed on the capacitor lower electrode 17 and its side surfaces. A capacitor upper electrode 20 is formed on the capacitor dielectric film 8 .

Furthermore, DRAM memory cells can be divided into several types depending on their capacitor structure for storing signal charges, and the one shown in FIG. 3 is a so-called stacked type memory cell. This type of memory cell consists of two layers of conductive films (capacitor lower electrode 17 and capacitor upper electrode 20) extending over the element isolation oxide film 2 and gate electrode 4, and a dielectric film (capacitor dielectric film) formed between them. A capacitor is constituted by the film 8). Therefore, when the memory cell size is reduced as DRAM becomes highly integrated, the capacitor area is also reduced at the same time.

[Problems to be Solved by the Invention] As described above, when memory cells are reduced in size due to higher integration of DRAMs, the area of capacitors is also reduced at the same time. However, DRAM as a storage area
Considering the stable operation and reliability of the memory cell, it is necessary to maintain the amount of charge stored in one bit of memory cell almost constant even if the memory cell size is reduced. One possible method for this purpose is to thin the dielectric film of the capacitor, but this method has the problem that the reliability of the dielectric film deteriorates as the dielectric film becomes thinner.

Therefore, as a conventional improvement method, a method can be considered to increase the surface area by thickening the lower electrode of the capacitor without thinning the dielectric film of the capacitor.

FIG. 4 is a sectional view showing this conventional improved stacked type memory cell. Referring to Figure 4, the third
In the memory cell shown in FIG. 4, the thickness of the capacitor lower electrode 27 is increased compared to the memory cell shown in the figure. As a result, capacitor dielectric film 8 and capacitor upper electrode 20 also become longer by the increased thickness of capacitor lower electrode 27, increasing the usable surface area of the capacitor as a whole and increasing capacitance. That is, since the lateral length of the capacitor constituted by the capacitor lower electrode 27, the capacitor dielectric film 8, and the capacitor upper electrode 20 is the same as before, the area that can be used as a capacitor means without increasing the planar area is increased. Can be increased.

However, this method of increasing the surface area by making the lower electrode of the capacitor thicker has the problem that it becomes difficult to form the lower electrode pattern at the high step part caused by increasing the thickness of the lower electrode. As the thickness of the electrode increases and the height difference increases, the etching time increases, resulting in the disadvantage that the degree of overetching due to variations in etching rate becomes more severe than in the past.When overetching becomes severe, the semiconductor device A new problem arises in that the reliability of the device itself decreases.

That is, in the past, when the memory cell size was reduced due to the integration of DRAMs, it was difficult to secure the capacitor capacity without encountering difficulties in patterning the lower electrode.

This invention was made to solve the above-mentioned problems, and even when the memory cell size is reduced, it is possible to secure capacitor capacity without experiencing difficulties in patterning the lower electrode. The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same.

[Means for Solving the Problems] The invention in the first claim includes an impurity region of a second conductivity type formed adjacent to an element isolation region of a semiconductor substrate of a first conductivity type, and an impurity region of the semiconductor substrate. A gate electrode formed on an adjacent region with a first insulating film interposed therebetween; A capacitor including a high melting point metal silicide layer having a plurality of extending protrusions, a second insulating film formed on the high melting point metal silicide layer, and a second conductive film formed on the second insulating film. means.

The invention in the second claim includes the steps of: forming a first conductive film to serve as a lower electrode of the capacitor on at least the impurity region; and forming a high melting point metal layer on the first conductive film. applying heat treatment to the first conductive film and the high melting point metal layer to form a high melting point metal silicide layer having a plurality of upwardly extending protrusions on the first conductive film; The method includes the steps of forming a second insulating film that becomes a dielectric film of the capacitor, and forming a second conductive film that becomes an upper electrode of the capacitor on the second insulating film.

[Operation] In the invention according to the first claim, the impurity region of the second conductivity type is formed adjacent to the element isolation region of the semiconductor substrate of the first conductivity type, and the gate electrode is formed in the region adjacent to the impurity region of the semiconductor substrate. A capacitive means is formed on the first insulating film through the first insulating film.
A first conductive film formed on at least an impurity region, a refractory metal silicide layer formed on at least the first conductive film and having a plurality of upwardly extending protrusions, and a refractory metal silicide layer formed on the refractory metal silicide layer. The second insulating film is formed by a second insulating film, and a second conductive film is formed on the second insulating film. In other words, since a high melting point metal silicide layer having a plurality of upwardly extending protrusions is formed on the first conductive film constituting the capacitor means, the area that can be used as the capacitor means is increased without increasing the planar area. There is also no need to increase the thickness of the first conductive film which becomes the lower electrode of the capacitive means.

In the invention according to the second claim, a first conductive film serving as a lower electrode of the capacitor means is formed on the impurity region, a high melting point metal layer is formed on the first conductive film, and a high melting point metal layer is formed on the first conductive film. A heat treatment is applied to the conductive film and the high melting point metal layer to form a high melting point metal silicide layer having a plurality of upwardly extending protrusions on the first conductive film, and a capacitive means is formed on at least the high melting point metal silicide layer. A second insulating film that becomes a dielectric film is formed, and a second conductive film that becomes an upper electrode of the capacitive means is formed on the second insulating film. The conductive film and the high melting point metal layer formed thereon are heat-treated to form a high melting point metal silicide layer having a plurality of upwardly extending protrusions on the first conductive film. The area usable as the capacitor means is increased without increasing the area, and there is no need to increase the thickness of the first conductive film serving as the lower electrode of the capacitor means.

[Embodiment of the Invention] FIG. 1 is a sectional view of a DRAM memory cell showing an embodiment of the invention. Referring to FIG. 1, the memory cell is
A silicon substrate 1, an element isolation oxide film 2 for element isolation formed on the silicon substrate 1, and an impurity diffusion layer 6 formed on the silicon substrate 1 adjacent to the element isolation oxide film 2.
, a gate electrode 4 formed on the silicon substrate 1 adjacent to the impurity diffusion layer 6 with a gate oxide film 3 interposed therebetween, and an insulating film 5 for insulation formed on the gate electrode 4 and on the side surfaces thereof. A polysilicon film 7 connected to the impurity diffusion layer 6 and formed on the element isolation oxide film 2 and the insulating film 5; a titanium silicide film 8b having a plurality of protrusions formed on the polysilicon film 7; A silicon nitride film 9 formed on film 8b and a polysilicon film 10 formed on silicon nitride film 9 are included.

As described above, since the titanium silicide film 8b formed on the polysilicon film 7 has a plurality of protrusions, the surface area is increased compared to a conventional planar lower electrode. Therefore, Porinlicon 7. The area that can be used as a capacitor area of the capacitor composed of titanium silicide film 8b, silicon nitride film 9, and polysilicon film 10 increases, and as a result, the capacitor capacity can be increased. In addition, in this structure, since the thickness of the polysilicon film 7 constituting the lower electrode of the capacitor is unchanged from that of the conventional one, it is difficult to form a pattern of the lower electrode at the high step portion that occurs when the thickness of the conventional lower electrode is increased. There is no difficulty. Therefore, in this embodiment, even if the memory cell size is reduced due to the integration of DRAM, there will be no difficulty in patterning the lower electrode (satisfying the requirements for stable operation and reliability of DRAM). It is possible to secure sufficient capacitor capacity for the following reasons.Furthermore, by adding only a few manufacturing steps, difficulties in the manufacturing method can be resolved.

28 to 2D are cross-sectional structural diagrams for explaining the manufacturing process of the DRAM memory cell shown in FIG. 1. The manufacturing process will be described with reference to FIGS. 2A to 2D. First, as shown in FIG. 2A, an element isolation oxide film 2. Impurity diffusion layer 6.
A gate oxide film 3. A gate electrode 4 and an insulating film 5 are formed. The details of the method for forming the access transistor and element isolation oxide film 2 of this DRAM are well known in the art and will therefore be omitted. Next, as shown in FIG. 2B, a polysilicon film 7 is deposited on the entire surface of the silicon substrate 1 by CVD.
form by law. Then, a titanium film 8a is sputter-deposited on the polysilicon film 7.

As shown in FIG. 2C, heat treatment is performed at 900° C. in a nitrogen atmosphere. As a result, a titanium silicide film 8b is formed, but an agglomeration phenomenon occurs in this titanium silicide film 8b, and its surface has a shape in which a plurality of protrusions are formed. Next, as shown in FIG. 2D, the portions other than those where the capacitor lower electrode will be formed are removed using photolithography and dry etching. Then, as shown in FIG. 1, a silicon nitride film 9 is formed on the titanium silicide film 8b, and then a polysilicon film 10 is formed on the silicon nitride film 9. Then, photolithography and dry etching are used to remove the portions other than those on which the polysilicon film that will become the capacitor upper electrode and the silicon nitride film 9 that will become the dielectric film will finally be formed. In addition,
In this embodiment, the silicon nitride film 9 is used as the dielectric film of the capacitor, but the present invention is not limited to this, and a thermal oxide film, a tantalum oxide film, or a composite film thereof may be used. Further, in this embodiment, titanium is used as the high melting point metal, but the present invention is not limited to this, and similar effects can be obtained by using other high melting point metals such as tungsten, molybdenum, and cobalt. Furthermore, although this embodiment has been described using a stacked type capacitor as an example, the present invention is not limited to this, and the present invention can be applied to a planar type or trench type capacitor as long as the portion corresponding to the lower electrode is a silicon substrate. The effect of this can be obtained.

[Effect of the invention] In the invention in the first claim, the first
By forming a refractory metal silicide layer having a plurality of upwardly extending protrusions on the conductive film, the area that can be used as the capacitor means is increased without increasing the area on the plane, and the lower part of the capacitor means is increased. Since there is no need to increase the thickness of the conductive film in Plan 1 that serves as an electrode, a semiconductor device that can secure capacitor capacity without experiencing difficulties in patterning a lower electrode even when the memory cell size is reduced. We were able to provide the following.

In the invention in the second claim, the first conductive film serving as the lower electrode of the capacitor means and the high melting point metal layer formed thereon are heat-treated to form a plurality of protrusions extending upward on the first conductive film. By forming a high-melting point metal silicide layer with a high melting point metal silicide layer, the area that can be used as a capacitor is increased without increasing the area on the plane, and it is necessary to increase the thickness of the first conductive film that becomes the lower electrode of the capacitor. Therefore, it has become possible to provide a method for manufacturing a semiconductor device that can ensure capacitor capacity without any difficulty in patterning the lower electrode even when the memory cell size is reduced.

[Brief explanation of drawings]

FIG. 1-FIG. 1 is a cross-sectional view of a DRAM memory cell showing an embodiment of the present invention, and FIGS. 28 to 2D are cross-sectional views for explaining the manufacturing process of the DRAM memory cell shown in FIG. 3 is a sectional view of a conventional stacked type memory cell, and FIG. 4 is a sectional view of a conventional improved stacked type memory cell. In the figure, 1 is a silicon substrate, 2 is an element isolation oxide film,
3 is a gate oxide film, 4 is a gate electrode, 5 is an insulating film, 6 is an impurity diffusion layer, 7 is a polysilicon film, 8b is a titanium silicide film, 9 is a silicon nitride film, and 10 is a polysilicon film. Note that the same symbols in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) An impurity region of a second conductivity type formed adjacent to an element isolation region of a semiconductor substrate of a first conductivity type and a region adjacent to the impurity region of the semiconductor substrate with a first insulating film interposed therebetween. a first conductive film formed on at least the impurity region; and a refractory metal silicide layer formed on at least the first conductive film and having a plurality of upwardly extending protrusions. A semiconductor device comprising capacitor means having a second insulating film formed on the high melting point metal silicide layer and a second conductive film formed on the second insulating film. (2) A second conductivity type impurity region is formed adjacent to the element isolation region of the first conductivity type semiconductor substrate, and a second conductivity type impurity region is formed on the semiconductor substrate adjacent to the impurity region via a first insulating film. A method of manufacturing a semiconductor device in which a gate electrode is formed, the method comprising: forming a first conductive film to serve as a lower electrode of a capacitor on at least the impurity region; and forming a high melting point metal on the first conductive film. forming a layer, and applying heat treatment to the first conductive film and the high melting point metal layer to form a high melting point metal silicide layer having a plurality of upwardly extending protrusions on the first conductive film. forming a second insulating film to serve as a dielectric film of the capacitive means on at least the high melting point metal silicide layer; and forming a second conductive film to serve as an upper electrode of the capacitive means on the second insulating film. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.