JPH02219264A - Dram cell and its manufacture - Google Patents
Dram cell and its manufactureInfo
- Publication number
- JPH02219264A JPH02219264A JP1039899A JP3989989A JPH02219264A JP H02219264 A JPH02219264 A JP H02219264A JP 1039899 A JP1039899 A JP 1039899A JP 3989989 A JP3989989 A JP 3989989A JP H02219264 A JPH02219264 A JP H02219264A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon oxide
- insulating
- insulating film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000003860 storage Methods 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 3
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 3
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 238000001947 vapour-phase growth Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 3
- 238000011065 in-situ storage Methods 0.000 claims 2
- 230000008021 deposition Effects 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 abstract description 10
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000003990 capacitor Substances 0.000 description 12
- 230000010354 integration Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体記憶装置に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor memory device.
従来の技術
高集積半導体メモリ用メモリセルとして１つのトランジ
スタと１つの容量部から構成されたいわゆる゛ １トラ
ンジスタ型″メモリセルは、構成要素が少なく、セル面
積の微小化が容易なため広く使われている。近年、半導
体メモリは、高集積化と大容量化が追求され、素子の微
細化が要請されている。１トランジスタ型メモリセルに
おいては、情報判定の容易さ、放射線への耐性を維持す
るために、メモリセル容量の減少は極力避けなければな
らない。そこで、当初のプレーナ型構造に比べ、比較的
大きな蓄積容量が得られるスタック形の蓄積キャパシタ
が提案されている。例えば第３図に示す構造では、隣接
セルのワード線の上部を含むフィールド酸化膜２の上部
領域が蓄積キャパシタに用いられるので、当初のプレー
ナ構造に比べ、蓄積容量が増大する。Conventional Technology As a memory cell for highly integrated semiconductor memory, the so-called "one-transistor type" memory cell, which is composed of one transistor and one capacitor, is widely used because it has few components and the cell area can be easily miniaturized. In recent years, semiconductor memory has been pursuing higher integration and larger capacity, and there has been a demand for smaller elements.One-transistor memory cells have the ability to easily determine information and maintain resistance to radiation. Therefore, a reduction in memory cell capacity must be avoided as much as possible.Therefore, a stacked storage capacitor has been proposed that can provide a relatively large storage capacity compared to the original planar structure.For example, as shown in Fig. In the structure shown, the storage capacitance is increased compared to the original planar structure, since the upper region of the field oxide 2, including the upper part of the word line of the adjacent cell, is used for the storage capacitor.
発明が解決しようとする課題
本発明が解決しようとする課題は、上記スタック形キャ
パシタにおける容量不足の問題である。Problems to be Solved by the Invention The problem to be solved by the present invention is the problem of insufficient capacity in the stacked capacitor.
課題を解決するための手段
本発明は、誘電体膜に熱酸化による酸化硅素膜又は、上
記酸化硅素膜上に窒化硅素膜を形成した２層膜又は、前
記２層膜表面の窒化硅素膜表面を酸化することにより形
成した、酸化硅素膜、窒化硅素膜、酸化硅素膜の３層膜
を用いることを特徴とするＤＲＡＭセルである。Means for Solving the Problems The present invention provides a dielectric film with a silicon oxide film formed by thermal oxidation, a two-layer film in which a silicon nitride film is formed on the silicon oxide film, or a silicon nitride film surface on the surface of the two-layer film. This DRAM cell is characterized by using a three-layer film of a silicon oxide film, a silicon nitride film, and a silicon oxide film, which are formed by oxidizing a silicon oxide film.
作用
即ち本発明に係るＤＲＡＭセルにおいては、電荷蓄積電
極の表面積を大幅に拡大させることが可能になり蓄積容
量の増大が図れる。さらに、電荷蓄積電極の表面積はエ
ツチング除去する第３の絶縁膜の厚さと、上記絶縁膜上
に延在する電荷蓄積電荷の面積によって決定するため蓄
積容量のばらつきは従来より大幅に縮小される。In other words, in the DRAM cell according to the present invention, the surface area of the charge storage electrode can be greatly expanded, and the storage capacity can be increased. Furthermore, since the surface area of the charge storage electrode is determined by the thickness of the third insulating film to be removed by etching and the area of the charge storage extending over the insulating film, variations in storage capacitance are significantly reduced compared to the conventional art.
実施例
以下本発明を、図示実施例により具体的に説明する。第
１図は本発明に係る蓄積キャパシタを有するＤＲＡＭセ
ルの一実施例を示す工程断面図である。第２図は本発明
に係る蓄積キャパシタを有するＤＲＡＭセルの他の実施
例を示す工程断面図である。なお第１図（ａ）以外はＳ
１基板内のｎ◆ソース、ｎ◆ドレイン及びフィールド酸
化膜は省略して図示する。最初に本発明の一実施例を第
１図を用いて説明する。まず第１図（ａ）に示すように
フィールド酸化膜２が形成されたＰ−Ｓ１基板１上に通
常の工程によりトランジスタを形成する。続いて上記基
板上全面にポリシリコン膜を堆積しドーピングした後第
１図（ｂ）に示す如くポリシリコンバッド８を形成する
。さらに第１図（Ｃ）に示す如く第１の絶縁膜９、例え
ばＮＳＣとＢＰＳＧを堆積しフローさせて平坦化した膜
を形成し、その上に第２の絶縁膜１０、例えば窒化硅素
膜を７０ｎｍ堆積する。さらにその上に第３の絶縁膜１
１例えば気相成長法による酸化硅素（例えばＰＳＧ）を
２００ｎｍ堆積する。その後フォトリソ工程によりコン
タクト孔Ｉ２をパターニングし、第１〜第３の絶縁膜９
．１０、ＩＩにコンタクト孔Ｉ２を開口する。上記コン
タクト孔１２内及び第３の絶縁膜ｌｌ上に電荷蓄積電極
を形成するための導電膜例えばｎ４ポリシリコンを堆積
し、フォトリソ工程及びエツチング工程により第１図（
ｅ）に示す如く電荷蓄積電極１３を形成する。EXAMPLES The present invention will be specifically explained below with reference to illustrated examples. FIG. 1 is a process sectional view showing an embodiment of a DRAM cell having a storage capacitor according to the present invention. FIG. 2 is a process sectional view showing another embodiment of a DRAM cell having a storage capacitor according to the present invention. Note that except for Fig. 1(a), S
The n◆source, n◆drain, and field oxide films in one substrate are omitted from illustration. First, one embodiment of the present invention will be described using FIG. 1. First, as shown in FIG. 1(a), a transistor is formed by a normal process on a P-S1 substrate 1 on which a field oxide film 2 is formed. Subsequently, a polysilicon film is deposited and doped on the entire surface of the substrate, and then a polysilicon pad 8 is formed as shown in FIG. 1(b). Further, as shown in FIG. 1C, a first insulating film 9, for example, NSC and BPSG, is deposited and flowed to form a flattened film, and a second insulating film 10, for example, a silicon nitride film is formed thereon. Deposit 70 nm. Furthermore, a third insulating film 1 is formed on it.
1. For example, silicon oxide (eg, PSG) is deposited to a thickness of 200 nm using a vapor phase growth method. After that, a contact hole I2 is patterned by a photolithography process, and the first to third insulating films 9 are formed.
．． 10, a contact hole I2 is opened in II. A conductive film, for example, N4 polysilicon, for forming a charge storage electrode is deposited in the contact hole 12 and on the third insulating film ll, and is etched by a photolithography process and an etching process as shown in FIG.
A charge storage electrode 13 is formed as shown in e).
次に、第２の絶縁膜１０（窒化硅素膜）に対して第３の
絶縁膜１１（ＰＳＧ）のエツチングレートが充分大きな
条件箱３の絶縁膜１１（ＰＳＧ）をエツチング除去する
。上記工程により露出した電荷蓄積電極１３の表面に誘
電体膜１４例えば５Ｉ０２．５ＩｓＮ４＋５Ｉ０２の３
層膜を形成しさらに第１図（ｇ）に示す如く誘電体膜１
４を介して電荷蓄積電極１３を履うようにｎ１ポリシリ
コンを堆積して対向電極１５を形成する。なお第２の絶
縁膜ｌＯに多結晶硅素膜を用いる場合、他の膜からの不
純物の拡散によりリークの原因になる恐れがあるため、
必要に応じて第２の絶縁膜ｌＯを除去する。上記実施例
に示すように、本発明に係る蓄積キャパシタにおいては
、集積度を下げずに従来のスタックドキャパシタよりも
大幅にキャパシタ面積を広くでき十分な容量を確保でき
る。Next, the insulating film 11 (PSG) in the condition box 3 is removed by etching, where the etching rate of the third insulating film 11 (PSG) is sufficiently larger than that of the second insulating film 10 (silicon nitride film). A dielectric film 14 is formed on the surface of the charge storage electrode 13 exposed by the above process, for example, 5I02.5IsN4+5I02.
A dielectric film 1 is formed as shown in FIG. 1(g).
A counter electrode 15 is formed by depositing n1 polysilicon so as to cover the charge storage electrode 13 via the n1 polysilicon layer. Note that when a polycrystalline silicon film is used as the second insulating film 1O, there is a risk of leakage due to diffusion of impurities from other films.
The second insulating film IO is removed if necessary. As shown in the embodiments described above, in the storage capacitor according to the present invention, the capacitor area can be made much larger than that of the conventional stacked capacitor, and a sufficient capacity can be secured without reducing the degree of integration.
次に、本発明に係るＤＲＡＭセルの製造法の他の実施例
を第２図で説明する。コンタクト孔形成までは、前述の
実施例に従い、続＜ｎ”ポリシリコンは第２図（ｅ）に
示す如くコンタクト孔が完全に埋め込まれない膜厚だけ
堆積し、ホ） ＩＪソ工程及びエツチング工程により電
荷蓄積電極１３を形成する。Next, another embodiment of the DRAM cell manufacturing method according to the present invention will be described with reference to FIG. Up to the formation of the contact hole, according to the above-mentioned embodiment, the polysilicon film is deposited to a thickness that does not completely fill the contact hole, as shown in FIG. 2(e), and e) IJ process and etching process. A charge storage electrode 13 is formed.
後の工程も第１の実施例に従って、第２図（ｆ）に示す
如く第３の絶縁膜（ＰＳＧ）１１をエツチング除去する
。In the subsequent steps, the third insulating film (PSG) 11 is removed by etching, as shown in FIG. 2(f), in accordance with the first embodiment.
そして第２図（ｇ）に示す如く誘電体膜１４を形成後ｎ
◆ポリシリコンを堆積して対向電極１５を形成する。After forming the dielectric film 14 as shown in FIG. 2(g),
◆Deposit polysilicon to form counter electrode 15.
上記実施例に示すように、本発明に係る蓄積キャパシタ
においては、前述の実施例よりもさらに大幅にキャパシ
タ面積を広くでき、十分な容量を確保できる。As shown in the embodiments described above, in the storage capacitor according to the present invention, the area of the capacitor can be made much larger than in the embodiments described above, and a sufficient capacity can be secured.
発明の詳細
な説明したように本発明によれば、蓄積容量が大きく蓄
積容量のばらつきが少ないＤＲＡＭセルを容易に高い歩
留りで形成できる。DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, a DRAM cell with a large storage capacity and little variation in storage capacity can be easily formed at a high yield.
第１図は、本発明に係るＤＲＡＭセルの製造方法の一実
施例の工程断面図、第２図は、本発明に係るＤＲＡＭセ
ルの製造方法の他の実施例の工程断面図、第３図は、ス
タックドキャパシタを具備する従来のＤＲＡＭセルの模
式断面図である。
８・・・・ポリシリコンバッド、９・・・・第１の絶縁
膜、１０・・・・第２の絶縁膜、１１・・・・第３の絶
縁膜、１２・・・・コンタクト孔、Ｉ３・・・・電荷蓄
積電極、Ｉ４・・・・誘電体膜、１５・・・・対向電極
。
代理人の氏名 弁理士 粟野重孝 はが１名粧1 is a process sectional view of one embodiment of the DRAM cell manufacturing method according to the present invention, FIG. 2 is a process sectional view of another embodiment of the DRAM cell manufacturing method according to the invention, and FIG. 1 is a schematic cross-sectional view of a conventional DRAM cell including a stacked capacitor. 8... Polysilicon pad, 9... First insulating film, 10... Second insulating film, 11... Third insulating film, 12... Contact hole, I3...Charge storage electrode, I4...Dielectric film, 15...Counter electrode. Name of agent: Patent attorney Shigetaka Awano (1 name)
Claims (7)
化硅素膜上に窒化硅素膜を形成した２層膜又は、前記２
層膜表面の窒化硅素膜表面を酸化することにより形成し
た、酸化硅素膜、窒化硅素膜、酸化硅素膜の３層膜を用
いることを特徴とするＤＲＡＭセル。(1) A silicon oxide film formed by thermal oxidation on the dielectric film, or a two-layer film in which a silicon nitride film is formed on the silicon oxide film, or
A DRAM cell characterized by using a three-layer film of a silicon oxide film, a silicon nitride film, and a silicon oxide film, which are formed by oxidizing the surface of a silicon nitride film on the surface of the layer film.
絶縁膜を形成し、上記第１の絶縁膜上に第２の絶縁膜を
形成し、上記第２の絶縁膜に比べてエッチング速度の充
分大きな第３の絶縁膜を上記第２の絶縁膜上に形成する
工程と、前記第１〜第３の絶縁膜上にホトリソ工程によ
りパターンを形成し、第１〜第３の絶縁膜にエッチング
によりコンタクト孔を形成する工程と、上記コンタクト
孔及び全面に第１の導電体膜を堆積し、ホトリソ工程及
びエッチングにより電荷蓄積電極を形成する工程と、前
記第３の絶縁膜をエッチングにより除去し、前記電荷蓄
積電極の露出表面に誘電体膜を形成する工程と、上記誘
電体膜を介し前記電荷蓄積電極を履うように第２・導電
体膜を堆積し対向電極を形成する工程とを含むことを特
徴とするＤＲＡＭセルの製造方法。(2) A first insulating film is formed on the semiconductor substrate on which the transistor is formed, a second insulating film is formed on the first insulating film, and the etching rate is lower than that of the second insulating film. forming a sufficiently large third insulating film on the second insulating film, forming a pattern on the first to third insulating films by a photolithography process, and etching the first to third insulating films; a step of forming a contact hole by depositing a first conductive film on the contact hole and the entire surface, forming a charge storage electrode by a photolithography step and etching, and removing the third insulating film by etching. , forming a dielectric film on the exposed surface of the charge storage electrode, and depositing a second conductive film to cover the charge storage electrode through the dielectric film to form a counter electrode. A method of manufacturing a DRAM cell, comprising:
ことを特徴とする特許請求の範囲第２項に記載のＤＲＡ
Ｍセルの製造方法。(3) The DRA according to claim 2, wherein the second insulating film is a silicon nitride film or a polycrystalline silicon film.
Method of manufacturing M cell.
後Ａｓイオンを注入し、さらに上記多結晶硅素膜上に第
２の多結晶硅素膜を形成後熱処理をすることにより形成
することを特徴とする特許請求の範囲第２項に記載のＤ
ＲＡＭセルの製造方法。(4) The first conductive film is formed by first forming a first polycrystalline silicon film, then implanting As ions, and then forming a second polycrystalline silicon film on the polycrystalline silicon film and then performing heat treatment. D according to claim 2, characterized in that
A method for manufacturing a RAM cell.
ｐｅｄ多結晶硅素膜と多結晶硅素膜を連続堆積した後熱
処理することにより形成することを特徴とする特許請求
の範囲第２項に記載のＤＲＡＭセルの製造方法。(5) In-situ Pdo of the first and second conductive films
3. The method of manufacturing a DRAM cell according to claim 2, wherein the DRAM cell is formed by successively depositing a ped polycrystalline silicon film and a polycrystalline silicon film and then subjecting the film to heat treatment.
ｐｅｄ多結晶硅素膜を堆積後熱処理することにより形成
することを特徴とする特許請求の範囲第２項に記載のＤ
ＲＡＭセルの製造方法。(6) In-situ Pdo of the first and second conductive films
D according to claim 2, characterized in that it is formed by heat-treating a ped polycrystalline silicon film after deposition.
A method for manufacturing a RAM cell.
よる酸化硅素膜と不純物を含む酸化硅素膜よりなる多層
膜とし、熱処理により不純物を含む酸化硅素膜をフロー
させて平坦化する工程を特徴とする特許請求の範囲第２
項記載のＤＲＡＭセルの製造方法。(7) A step of forming the first and third insulating films into multilayer films consisting of at least a silicon oxide film grown by vapor phase growth and a silicon oxide film containing impurities, and causing the silicon oxide film containing impurities to flow and planarize by heat treatment. Claim 2 characterized by
A method for manufacturing a DRAM cell as described in 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1039899A JPH02219264A (en) | 1989-02-20 | 1989-02-20 | Dram cell and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1039899A JPH02219264A (en) | 1989-02-20 | 1989-02-20 | Dram cell and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02219264A true JPH02219264A (en) | 1990-08-31 |
Family
ID=12565811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1039899A Pending JPH02219264A (en) | 1989-02-20 | 1989-02-20 | Dram cell and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02219264A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02254751A (en) * | 1989-03-29 | 1990-10-15 | Fujitsu Ltd | Semiconductor memory cell |
| US5166088A (en) * | 1990-07-03 | 1992-11-24 | Sharp Kabushiki Kaisha | Method of manufacturing semiconductor device contact vias in layers comprising silicon nitride and glass |
| JPH06140569A (en) * | 1991-11-16 | 1994-05-20 | Samsung Electron Co Ltd | Capacitor of semiconductor device and its manufacture as well as semiconductor device provided with said capacitor and its manufacture |
| JPH06196649A (en) * | 1992-12-08 | 1994-07-15 | Nec Corp | Manufacture of semiconductor device |
| DE19620185A1 (en) * | 1996-01-10 | 1997-07-24 | Lg Semicon Co Ltd | Production of capacitor for semiconductor device, e.g. 256M DRAM |
| US5840619A (en) * | 1994-02-23 | 1998-11-24 | Mitsubishi Denki Kabushiki Kaisha | Method of making a semiconductor device having a planarized surface |
| US5986300A (en) * | 1995-06-27 | 1999-11-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device and method of manufacturing the same |
| DE19624698C2 (en) * | 1995-06-27 | 2002-03-14 | Mitsubishi Electric Corp | Semiconductor memory device and method for producing a semiconductor memory device |
| US6384441B1 (en) * | 2000-03-31 | 2002-05-07 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
| US6756627B1 (en) * | 1997-03-14 | 2004-06-29 | Micron Technology, Inc. | Container capacitor |
-
1989
- 1989-02-20 JP JP1039899A patent/JPH02219264A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02254751A (en) * | 1989-03-29 | 1990-10-15 | Fujitsu Ltd | Semiconductor memory cell |
| US5166088A (en) * | 1990-07-03 | 1992-11-24 | Sharp Kabushiki Kaisha | Method of manufacturing semiconductor device contact vias in layers comprising silicon nitride and glass |
| JPH06140569A (en) * | 1991-11-16 | 1994-05-20 | Samsung Electron Co Ltd | Capacitor of semiconductor device and its manufacture as well as semiconductor device provided with said capacitor and its manufacture |
| JPH06196649A (en) * | 1992-12-08 | 1994-07-15 | Nec Corp | Manufacture of semiconductor device |
| US5840619A (en) * | 1994-02-23 | 1998-11-24 | Mitsubishi Denki Kabushiki Kaisha | Method of making a semiconductor device having a planarized surface |
| DE19624698C2 (en) * | 1995-06-27 | 2002-03-14 | Mitsubishi Electric Corp | Semiconductor memory device and method for producing a semiconductor memory device |
| US5986300A (en) * | 1995-06-27 | 1999-11-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device and method of manufacturing the same |
| US6146942A (en) * | 1995-06-27 | 2000-11-14 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor memory device |
| DE19620185C2 (en) * | 1996-01-10 | 1999-07-22 | Lg Semicon Co Ltd | Method of manufacturing a capacitor of a semiconductor device |
| DE19620185A1 (en) * | 1996-01-10 | 1997-07-24 | Lg Semicon Co Ltd | Production of capacitor for semiconductor device, e.g. 256M DRAM |
| US6756627B1 (en) * | 1997-03-14 | 2004-06-29 | Micron Technology, Inc. | Container capacitor |
| US6384441B1 (en) * | 2000-03-31 | 2002-05-07 | Fujitsu Limited | Semiconductor device and method of manufacturing the same |
| US6475858B2 (en) | 2000-03-31 | 2002-11-05 | Fujitsu Limited | Method of manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5350707A (en) | Method for making a capacitor having an electrode surface with a plurality of trenches formed therein | |
| JP3222944B2 (en) | Method for manufacturing capacitor of DRAM cell | |
| JP2785766B2 (en) | Method for manufacturing semiconductor device | |
| JPH0685187A (en) | Semiconductor storage device | |
| JP2741672B2 (en) | Method of manufacturing capacitor for stacked DRAM cell | |
| JPH08204145A (en) | Method of manufacturing semiconductor device | |
| JPH02219264A (en) | Dram cell and its manufacture | |
| US5104821A (en) | Method for fabricating stacked capacitors in a DRAM cell | |
| JPH04317358A (en) | Manufacture of semiconductor device | |
| JPH05347389A (en) | Manufacture of semiconductor memory | |
| JP3569168B2 (en) | Method for manufacturing semiconductor device | |
| JP2523981B2 (en) | Method for manufacturing semiconductor device | |
| JPH0321062A (en) | Semiconductor storage device | |
| JPH02260454A (en) | Manufacture of memory device | |
| US5879988A (en) | Capacitor of a DRAM cell and method of making same | |
| JPH03230561A (en) | Semiconductor device and manufacture thereof | |
| JP3120462B2 (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
| JP3425575B2 (en) | Method for manufacturing semiconductor device | |
| JP2950550B2 (en) | Method for manufacturing semiconductor memory device | |
| JP3048417B2 (en) | Method for manufacturing semiconductor device | |
| JP2836546B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH11261023A (en) | Semiconductor device and its manufacture | |
| JPH07202023A (en) | Semiconductor storage device and its manufacture | |
| JPH06302778A (en) | Semiconductor device and manufacture thereof | |
| JPH03148860A (en) | Semiconductor memory and manufacture thereof |