JP2836546B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a structure of a capacitor electrode of a semiconductor memory device and a method of forming the same.

[0002]

2. Description of the Related Art Among semiconductor memory devices, there is a DRAM capable of arbitrarily inputting and outputting stored information. Where D
The memory cell of the RAM, which includes one transfer transistor and one capacitor, is structurally simple, and is widely used as the most suitable for high integration of a semiconductor memory device.

In such a memory cell capacitor,
With further increase in the degree of integration of semiconductor memory devices, those having a three-dimensional structure have been developed and used. The three-dimensional structure of the capacitor is based on the following reasons. 2. Description of the Related Art With miniaturization and higher density of semiconductor elements, it is essential to reduce the area occupied by capacitors. However, in order to ensure stable operation and reliability of the DRAM, it is necessary to secure a certain or more capacitance value. Therefore, the lower capacitance electrode (storage electrode) of the capacitor
It is essential that the surface area of the capacitor electrode be increased within the reduced occupied area by changing from a planar structure to a three-dimensional structure.

The three-dimensional capacitor of the DRAM memory cell includes a stack type capacitor and a trench type capacitor. Each of these structures has advantages and disadvantages,
The stack type has high resistance to the incidence of alpha rays or noise from circuits and the like, and operates stably even when the capacitance value is relatively small. For this reason, 1 gigabit (1 Gbit), which is a design standard of a semiconductor element of about 0.15 μm.
b) Stack type capacitors are also considered to be effective in DRAMs.

As the stacked capacitor (hereinafter, referred to as a stacked capacitor), a storage capacitor having a cylindrical structure has been energetically studied, and various improvements have been made. Therefore, a recently proposed stacked capacitor having a cylinder structure will be described with reference to FIG. FIG.
FIG. 27 is a cross-sectional view of a memory cell region having a multiple cylinder structure in which storage electrodes are formed concentrically by the technique described in Japanese Patent Publication No. 67-67.

As shown in FIG. 7, a field oxide film 102 is formed in a predetermined region on a silicon substrate 101.
Then, the gate electrode 104 is interposed via the gate oxide film 103.
Is formed, and a first N ⁺ diffusion layer 105 and a second N ⁺ diffusion layer 106 are provided on the surface of the silicon substrate 101 on both sides thereof. Thus, a transfer transistor in the memory cell region is formed. Then, an interlayer insulating film 107 is formed so as to cover the field oxide film 102 and the transfer transistor.

[0007] Next, a contact hole is formed in the interlayer insulating film 107 on the second N ⁺ diffusion layer 106, the lower electrode film 1 which is electrically connected to the second N ⁺ diffusion layer 106 is the accumulation node
08 is provided. Then, a plurality of cylindrical electrode films are formed by being electrically connected to the lower electrode film 108. In this example, the first cylindrical electrode film 109 and the second
The cylindrical electrode film 110 and the third cylindrical electrode film 111 are provided, and the storage electrode 112 having a triple cylinder structure is formed.

Next, a capacitance insulating film 113 covering the surface of the storage electrode 112 is provided, and a plate electrode 114 as an upper capacitance electrode is formed. Thus, a memory cell having one transistor and one capacitor having a triple cylinder structure is formed.

[0009]

However, in a memory cell of a DRAM formed by such a conventional technique,
As the storage capacity increases to 256 megabits or 1 Gb and the memory cell size becomes finer, the following problems become apparent.

[0010] In the manufacturing process of the capacitor described in the prior art, particularly in a process such as cleaning after forming the storage electrode, the cylindrical electrode film forming the storage electrode is broken. For this reason, it is difficult to reduce the thickness of each cylindrical electrode film constituting the storage electrode in terms of securing its mechanical strength.

Alternatively, in order to make it possible to form a thin film while maintaining a low mechanical strength, it is necessary to develop a new plate electrode material having extremely good step coverage and low stress.
However, at present, development of such materials is difficult. For these reasons, there is a limit to the multiplexing of the cylinder electrodes formed in the area having a limited plane area.

As the storage capacity of the DRAM increases, the plane area of the memory cell decreases. However, the capacity of the capacitor for storing electric charges is maintained at a substantially constant value irrespective of an increase in the storage capacity in order to prevent soft errors due to alpha rays or to ensure signal strength at the time of reading. . For this reason, the height of the storage electrode formed by the conventional technique increases with the increase of the storage capacity. However, when the height of the storage electrode is increased in this manner, the step between the array portion and the peripheral circuit portion of the DRAM memory cell becomes large, and a defect such as a resolution failure in a photolithography process, a disconnection or a short circuit in a wiring formation process, or the like. Occurs and the yield is reduced.

An object of the present invention is to solve the above problems and to provide a semiconductor device having a fine capacitor structure and a method of manufacturing the same.

[0014]

According to the present invention, there is provided a semiconductor device having a memory cell including one transfer transistor and one capacitor, wherein the insulating film covers the transfer transistor. A layer is formed, a groove is formed that penetrates a predetermined region of the insulating film layer and reaches a diffusion layer that is a source or drain region of the transfer transistor, and a first cylindrical cylinder is formed on a sidewall in the groove. An electrode film is formed,
A second electrode film having a cylindrical shape is formed inside the first electrode film, and the first electrode is interposed via a capacitance insulating film formed on the surfaces of the first electrode film and the second electrode film. Membrane and second
A third electrode film is formed opposite to the first electrode film, and a fourth electrode film is formed on the insulating film layer and along an edge of the groove, and is electrically connected to the first electrode film. The third electrode film is formed so as to be opposed to the fourth electrode film via the capacitor insulating film, and a part of the first electrode film is electrically connected to the diffusion layer. Connected to form the capacitor, wherein the insulating film layer is formed in a two-layer structure of a lower insulating film layer and an upper insulating film layer of a different type from the lower insulating film layer, and reaches the diffusion layer. The diameter of the groove is set to be small in the lower insulating film layer close to the diffusion layer and to be larger in the upper insulating film layer, and the groove formed in the lower insulating film layer is filled with a conductive material. The first electrode film and the second electrode film are formed in grooves formed in the upper insulating film layer. It is characterized by being electrically connected to said conductor material is.

[0015]

[0016]

[0017]

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, the step of forming an insulating film layer covering the transfer transistor and the step of forming a first groove reaching a diffusion layer which is a source or drain region of the transfer transistor by the insulating step. Forming a film layer; filling the first groove with a conductive material; and covering the insulating film layer and the conductive material with a capacitor groove insulating film different from the insulating film layer. Depositing, forming a second groove reaching the surface of the conductive material in the insulating film for the capacity groove, and forming a second groove on the exposed conductive material, a side wall of the second groove, and the capacity groove. Depositing a first conductive film covering an upper portion of the insulating film for use, forming a spacer film on a side surface of the first conductive film adhered to a side wall of the second groove, The surface of the spacer film and the first conductive layer Depositing a second conductor film on the surface of the film, performing anisotropic dry etching on the second conductor film to form a second electrode film on the side wall of the spacer film, A step of patterning the first conductor film into a predetermined shape to form a first electrode film; and a step of etching and removing the spacer film.

Here, an insulating material is used in which the dry etching rate of the capacitance groove insulating film is higher than the dry etching rate of the insulating film layer.

As described above, in the present invention, the storage electrode of the capacitor is buried in the groove provided in the interlayer insulating film or the insulating film for the capacitor groove, and is formed so as to have a multi-cylinder electrode structure. For this reason, breakage of the storage electrode and the like do not occur in the manufacturing process of the capacitor described in the prior art, particularly in a process such as cleaning after forming the storage electrode. Then, the thickness of the electrode film constituting the storage electrode can be easily reduced.

The storage electrode of the capacitor is formed so as to be embedded in the flattened insulating film layer. Then, the step between the array portion and the peripheral circuit portion of the memory cell is eliminated, and the problem of the focus margin in the photolithography process is solved.

[0022]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a sectional view of a memory cell portion of a DRAM for explaining a first embodiment of the present invention.

As shown in FIG. 1, a field oxide film 2, which is an inactive region, is selectively formed on a silicon substrate 1, and an element active region surrounded by the field oxide film 2 is formed. Then, a MOS transistor including a gate oxide film 3, a gate electrode 4, a capacitance diffusion layer 5, a bit line diffusion layer 6, and the like is formed on the element active region. This MOS transistor becomes a transfer transistor of the memory cell. Further, a word line 4 ′ is formed on the field oxide film 2. This word line 4 'is connected to the gate electrode of the transfer transistor of the adjacent memory cell. Then, an interlayer insulating film 7 covering the gate electrode (word line) 4 and the word line 4 'is formed. Here, the thickness of the interlayer insulating film 7 is about 1 μm.

In a predetermined region of the interlayer insulating film 7, a capacitor contact hole 8, ie, a groove as shown in FIG. Here, the planar shape of the capacitor contact hole 8 may be circular or rectangular. An edge electrode film 9 is formed above the interlayer insulating film 7 and at the edge of the capacitor contact hole 8.

A first electrode film is formed to cover the capacitor contact hole 8 or the side wall of the edge electrode film 9, the upper portion of the edge electrode film 9, and the surface of the capacitor diffusion layer 5.
Here, the first electrode film 10 has a cylindrical shape and is electrically connected to the capacitance diffusion layer 5. Further, as shown in FIG. 1, a cylindrical second electrode film 11 is similarly formed inside the first electrode film 10.

Then, the edge electrode film 9 and the first electrode film 10
The capacitor insulating film 12 is formed so as to cover the second electrode film 11, and a plate electrode 13 covering the capacitor insulating film 12 is formed. Thus, the edge electrode film 9, the first electrode film 10, and the second electrode film 11 constitute a storage electrode, and the plate electrode 13 constitutes an upper capacitor electrode.

As described above, in the capacitor of the present invention,
The storage electrode of the capacitor includes a plurality of electrode films embedded in a capacitor contact hole provided in a predetermined region of the interlayer insulating film.

Next, a manufacturing method according to the first embodiment of the present invention will be described with reference to FIGS. 2 and 3 are sectional views in the order of the manufacturing steps.

As shown in FIG. 2A, a field oxide film 2 is formed in a predetermined region of a silicon substrate 1 having a P-type conductivity. Here, the field oxide film 2 is formed by a known trench element isolation method or a recess LOCOS method.

Next, a MOS transistor including a gate oxide film 3, a gate electrode 4, a capacitor diffusion layer 5, a bit line diffusion layer 6, and the like is formed in a region where no field oxide film is formed, that is, in an element active region. . And this MO
The S transistor becomes a transfer transistor of the memory cell. At the same time, a word line 4 'connected to the gate electrode of the transfer transistor of the adjacent memory cell is formed on the field oxide film 2. Here, the gate oxide film 3 is a silicon oxide film having a thickness of about 10 nm, and the gate electrode 4 is formed of a titanium polycide film having a thickness of about 200 nm. The capacitance diffusion layer 5 and the bit line diffusion layer 6 are N ⁺ type diffusion layers having a depth of about 0.1 μm.

Next, the interlayer insulating film 7 is made flat by a combination of deposition of a silicon oxide film by a known chemical vapor deposition (CVD) method and chemical mechanical polishing (CMP) of the silicon oxide film. It is formed. Here, the thickness of the interlayer insulating film 7 is set to 1 μm.

Next, an upper conductive film 9a is deposited on the surface of the interlayer insulating film 7. Here, the upper conductive film 9a
Is a polycrystalline silicon film having a thickness of 200 nm and containing a phosphorus impurity. This polycrystalline silicon film is formed by a low-pressure CVD method using a mixed gas of silane (SiH ₄ ) and phosphine (PH ₃ ) as a reaction gas.

Next, the conductor film 9a and the interlayer insulating film 7 above the predetermined region are sequentially etched by using the photolithography technique and the dry etching technique. Then, a capacitor contact hole 8 is formed.

Next, as shown in FIG. 2B, the first conductive film covering the side wall of the capacitive contact hole 8, the exposed surface of the capacitive diffusion layer 5 and the upper surface of the upper conductive film 9a. The body film 14 is formed. Here, the first conductor film 14 is
This is a polycrystalline silicon film having a thickness of 100 nm and containing a phosphorus impurity. The method of depositing the first conductive film 14 is the same as the method of forming the upper conductive film 9a described above.

Subsequently, a spacer insulating film 15 to be deposited on the first conductive film 14 is deposited. This spacer insulating film 15 is a silicon oxide film having a thickness of 100 nm.
The reaction gas is deposited by a low pressure CVD method using a mixed gas of silane and nitrous oxide (N ₂ O). This decompression C
The film forming temperature in the VD method is about 800 ° C., and the formed silicon oxide film has very good step coverage.

Next, this spacer insulating film 15 is subjected to anisotropic dry etching. Then, FIG.
As shown in FIG. 6, a spacer film 16 having a thickness of about 100 nm is formed along the side wall of the first conductive film 14 on the inner wall of the capacitor contact hole 8. Here, the reaction gas in this anisotropic dry etching is a mixed gas of CH ₂ F ₂ and CF ₄ , and the ratio of the etching rate of the silicon oxide film to the etching rate of the polycrystalline silicon film, that is, the selectivity is 30 to
It will be about 40. Therefore, the spacer film 16 can be formed without substantially etching the first conductor film 14 by the anisotropic dry etching.

Next, as shown in FIG. 3A, a second conductor film 17 covering the first conductor film 14 and the spacer film 16 is formed. Here, the second conductor film 17 is a polycrystalline silicon film containing a phosphorus impurity, and its thickness is set to 100 nm. This second conductor film 17
Is also deposited by the low pressure CVD method, under the same conditions as in the case of forming the first conductive film 14.

Next, the second conductive film 17 is subjected to anisotropic dry etching. Then, as shown in FIG. 3B, along the side wall of the spacer film 16, a film thickness of 10
A second electrode film 11 of about 0 nm is formed. here,
The reaction gas in this anisotropic dry etching is Cl ₂ and H
It is a mixed gas of Br, and the ratio of the etching rate of the polycrystalline silicon film to the etching rate of the silicon oxide film, that is, the selectivity is about 50. Therefore, the second electrode film 11 is formed without substantially etching the spacer film 16 even in the anisotropic dry etching.

However, in this case, the first conductor film 14 is formed below and in contact with the second conductor film 17.
Therefore, it is necessary to control the anisotropic dry etching so that the etching time does not exceed the set time. It should be noted that even when there is a large variation in the anisotropic dry etching, the first conductive film 1
Since the upper conductive film 9 a is further formed below the lower layer 4, the conductive film remains on the surface of the interlayer insulating film 7. Further, since the capacity diffusion layer 5 is formed in the surface region of the silicon substrate 1, even if a part of the first conductive film 14 in the upper layer is dry-etched, the capacity diffusion layer 5 and the first The conductive film 14 remains in an electrically connected state.

Next, the spacer film 1 is diluted in a dilute hydrofluoric acid chemical solution.
Only 6 is removed by etching. Next, the first conductor film 14 and the upper conductor film 9a are selectively finely processed by using a photolithography technique and a dry etching technique, and as shown in FIG. The electrode film 9 and the first electrode film 10 are formed.

As described above, the first electrode film partially buried in the capacitor contact hole provided in the interlayer insulating film 7,
The second electrode film is formed so as to be electrically connected to the capacitance diffusion layer.

Thereafter, as shown in FIG.
2 and the plate electrode 13 are formed to complete the capacitor of the present invention. Here, the capacitance insulating film 12 is a silicon nitride film having a thickness of about 6 nm. The plate electrode 13 is a polycrystalline silicon film having a thickness of about 300 nm and containing a phosphorus impurity.

As described above, the storage electrode of the present invention is formed so as to be partially buried in the contact hole or the groove provided in the interlayer insulating film and to have a multiple electrode structure. For this,
The above-mentioned problems such as breakage of the storage electrode in the process of manufacturing the capacitor structure are eliminated. Also, the step between the array portion and the peripheral circuit portion of the memory cell becomes very small. Further, the storage capacitance value is equivalent to that of the multiple cylinder structure described in the related art.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4A is a plan view of the memory cell, and only a word line and a storage electrode in an upper layer are shown for simplification of the drawing. Further, a region to be a storage electrode is hatched. FIG. 4 (b) is the same as FIG.
It is sectional drawing cut | disconnected by AB described in FIG.

As shown in FIG. 4A, in the second embodiment, a storage electrode is formed in a region located above the gate electrode 4 and the word line 4 '. That is, the first electrode film 10 and the second electrode film 1 whose planar shapes are rectangular
1 is formed. Here, this planar shape is set according to the dimensions of the memory cell.

As shown in FIG. 4B, similarly to the first embodiment, a field oxide film 2 is selectively formed on a silicon substrate 1, and an element active region surrounded by them is formed. . Then, a MOS transistor including a gate oxide film 3, a gate electrode 4, a capacitance diffusion layer 5, a bit line diffusion layer 6, and the like is formed on the element active region. This MOS transistor becomes a transfer transistor of the memory cell. Further, a word line 4 ′ is formed on the field oxide film 2. This word line 4 '
Is connected to the gate electrode of the transfer transistor of the adjacent memory cell. Then, an interlayer insulating film 7 covering the gate electrode (word line) 4 and the word line 4 'is formed. Here, the thickness of the interlayer insulating film 7 is 500 n.
m.

In a predetermined region of the interlayer insulating film 7, FIG.
A capacitor contact hole 8 as shown in FIG. 2B is formed through the capacitor diffusion layer 5. Here, the planar shape of the capacitor contact hole 8 is circular. A conductor material is buried in the capacity contact hole 8 to form a capacity contact hole plug 18.

Further, a capacitor groove insulating film 19 is formed on the interlayer insulating film 7. The capacity groove 20 is formed in the capacity groove insulating film 19.

The first electrode film 10 is formed on the side wall of the capacitor groove 20 and the upper portion thereof and the surface of the capacitor contact hole plug 18. Here, the first electrode film 10 is electrically connected to the capacitance diffusion layer 5 through the capacitance contact hole plug 18. Further, the first electrode film 10
The second electrode film 11 is formed inside the substrate.

Then, a capacitance insulating film 12 is formed so as to cover the first electrode film 10 and the second electrode film 11, and a plate electrode 13 which covers the capacitance insulating film 12 is formed. .

As described above, in the capacitor of the present invention,
The storage electrode of the capacitor includes a plurality of electrode films buried in the capacitance groove 20 provided in a predetermined region of the capacitance groove insulating film 19.

Next, a manufacturing method according to a second embodiment of the present invention will be described with reference to FIGS. 5 and 6 are sectional views in the order of the manufacturing steps.

As shown in FIG. 5A, a field oxide film 2 is formed in a predetermined region of a silicon substrate 1 in the same manner as described in the first embodiment. Next, a gate oxide film 3, a gate electrode 4, a capacitor diffusion layer 5,
A MOS transistor including the bit line diffusion layer 6 and the like is formed. Then, this MOS transistor becomes a transfer transistor of the memory cell. At the same time, a word line 4 'connected to the gate electrode of the transfer transistor of the adjacent memory cell is formed on the field oxide film 2. Here, the gate oxide film 3 is a silicon oxide film having a thickness of about 8 nm, and the gate electrode 4 is formed of a titanium polycide film having a thickness of about 150 nm. The capacitance diffusion layer 5 and the bit line diffusion layer 6 are N ⁺ type diffusion layers having a depth of about 0.1 μm.

Next, a silicon oxide film is deposited on the interlayer insulating film 7 by a known CVD method and the silicon oxide film is subjected to CMP.
It is formed so as to be flat in combination with the method. Here, the thickness of the interlayer insulating film 7 is set to be about 500 nm. Then, a capacitor contact hole 8 is formed by a known fine processing technique, and a capacitor contact hole plug 18 filling the capacitor contact hole 8 is formed. Here, the capacitor contact hole plug 18 is a conductor material made of polycrystalline silicon containing a phosphorus impurity.

Next, as shown in FIG. 5B, a 1 μm-thick insulating film 19 for a capacity groove is formed. Here, the capacitance groove insulating film 19 is a PSG film (a silicon oxide film containing phosphorus glass) deposited by a CVD method. And
A capacity groove 20 is formed in a predetermined region of the capacity groove insulating film 19. This formation is performed by a known fine processing technique. When processing the capacity groove 20 by dry etching, it is necessary to prevent the interlayer insulating film 7 from being etched. For this reason, the etching of the PSG film is made faster and that of the silicon oxide film is made slower. CHF ₃ , CF _4, and C are reactive gases for such dry etching.
A mixed gas of O is used.

Next, the side wall of the capacitance groove 20, the exposed surface of the capacitance contact hole plug 18, and the insulation film 1 for the capacitance groove
A first conductor film 14 covering the upper surface of the substrate 9 is formed.
Here, the first conductor film 14 is a polycrystalline silicon film having a thickness of 100 nm and containing no phosphorus impurity. The method of depositing the first conductor film 14 is the same as the above-described formation method. However, in this case, no phosphine gas is used as the reaction gas.

Subsequently, as in the case of the first embodiment, a spacer insulating film 15 to be deposited on the first conductive film 14 is deposited. This spacer insulating film 15 is a silicon oxide film having a thickness of 300 nm. Then, the spacer insulating film 15 is subjected to anisotropic dry etching to form a spacer film 16 having a thickness of about 300 nm as shown in FIG. Here, the conditions of the anisotropic dry etching are the same as those described above.

Next, as shown in FIG. 6A, a second conductor film 17 covering the first conductor film 14 and the spacer film 16 is formed. Here, the second conductor film 1
7 contains a phosphorus impurity. Subsequently, this second
The conductive film 17 is subjected to anisotropic dry etching, and a second electrode film 11 having a thickness of about 100 nm is formed along the side wall of the spacer film 16 as shown in FIG. You. Here, a mixed gas of Cl ₂ and HBr is used as a reaction gas for the anisotropic dry etching. In this case, the etching rate of the first conductor film 14 containing no phosphorus impurity depends on the second electrode film 17 containing the phosphorus impurity.
And the first conductive film 14 remains without being etched.

Next, only the spacer film 16 is removed by etching in a diluted hydrofluoric acid solution. Next, thermal diffusion is performed, and phosphorus impurities are introduced into the first conductive film 14 described above. Then, the first conductor film 14 is selectively etched by using the fine processing technique, and the first electrode film 10 is formed as shown in FIG. 6C.

As described above, the first electrode film 1 partially embedded in the capacity groove 20 provided in the capacity groove insulating film 19
0, the second electrode film 11 is formed so as to be connected to the capacitance contact hole plug 18 electrically connected to the capacitance diffusion layer 5.

Thereafter, as shown in FIG.
2 and the plate electrode 13 are formed to complete the capacitor of the present invention. Here, the capacitance insulating film 12 is a silicon nitride film having a thickness of about 5 nm. The plate electrode 13 is a polycrystalline silicon film having a thickness of about 300 nm and containing a phosphorus impurity.

In this embodiment, a BPSG film (a silicon oxide film containing boron glass and phosphorus glass) may be used as the insulating film for the capacity trench instead of the PSG film. Alternatively, the insulating material is not limited to these as long as the insulating material is higher than the etching rate of the interlayer insulating film.

As described above, the storage electrode of the present invention is buried in the capacitance groove provided in the insulation film for the capacitance groove, and is formed so as to have a multi-cylinder electrode structure. For this reason, the level difference between the array portion and the peripheral circuit portion of the memory cell becomes very small. In this case, the capacity groove 20 is formed in an arbitrary rectangular shape. For this reason, the planar dimensions of the capacitor electrode can be arbitrarily set and can be set according to the memory cell dimensions. Then, dense arrangement of a large number of storage electrodes in the memory cell portion is facilitated.

In the above embodiment, the case where the first electrode film or the second electrode film is formed of a polycrystalline silicon film containing a phosphorus impurity has been described. May be formed of the conductive film.
For example, it is formed of a refractory metal film such as a titanium nitride film or tungsten or a silicide film.

In the embodiment, the thickness of the electrode film is 1
Although it is described to be 00 nm, it can be similarly formed even with a film thickness of about 20 nm.

In the embodiment of the present invention, the case where the storage electrode film has a double cylinder structure has been described. However, it should be noted that a triple or quadruple cylinder may be used. .

[0067]

As described above, according to the present invention, the storage electrode of the capacitor is buried in the groove provided in the interlayer insulating film or the insulating film for the capacitor groove, and is formed so as to have a multi-cylinder electrode structure. .

For this reason, even if the storage capacity of a memory cell such as a DRAM is increased to 256 megabits or 1 Gb and the size of the memory cell is reduced, the manufacturing process of the capacitor described in the prior art, particularly, the formation of the storage electrode The problem such as breakage of the storage electrode in a cleaning step or the like after the cleaning does not occur. Then, it is easy to reduce the thickness of the electrode film constituting the storage electrode, and the miniaturization of the capacitor is promoted.

Further, the plane area of the memory cell decreases as the storage capacity of the DRAM increases. However, the capacity of the capacitor for storing electric charges is maintained at a substantially constant value irrespective of an increase in the storage capacity in order to prevent soft errors due to alpha rays or to ensure signal strength at the time of reading. . For this reason, the height of the storage electrode formed by the conventional technique increases with the increase of the storage capacity. However, even in this case, the level difference between the array portion and the peripheral circuit portion of the memory cell is small, and defects such as resolution failure in the photolithography process and disconnection or short circuit in the wiring formation process do not occur.

As described above, the present invention further promotes the realization of a highly integrated semiconductor device having a fine capacitor structure.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a memory cell section for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a first embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a sectional view of a first embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a plan view and a cross-sectional view of a memory cell unit according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a second embodiment of the present invention in the order of manufacturing steps.

FIG. 6 is a sectional view of a second embodiment of the present invention in the order of manufacturing steps.

FIG. 7 is a cross-sectional view of a memory cell for explaining a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1, 101 Silicon substrate 2, 102 Field oxide film 3, 103 Gate oxide film 4, 104 Gate electrode 4 'Word line 5 Diffusion layer for capacity 6 Diffusion layer for bit line 7, 107 Interlayer insulating film 8 Capacitance contact hole 9 Edge Electrode film 9a Upper conductor film 10 First electrode film 11 Second electrode film 12, 113 Capacitance insulation film 13, 114 Plate electrode 14 First conductor film 15 Spacer insulation film 16 Spacer film 17 Second Conductor film 18 Capacitance contact hole tag 19 Capacitance groove insulating film 20 Capacitance groove 105 First N ⁺ diffusion layer 106 Second N ⁺ diffusion layer 108 Lower electrode film 109 First cylindrical electrode film 110 Second cylindrical electrode Membrane 111 third cylindrical electrode membrane 112 storage electrode

Claims (3)

(57) [Claims] In a semiconductor device having a memory cell composed of one transfer transistor and one capacitor, an insulating film layer covering the transfer transistor is formed, and a predetermined region of the insulating film layer is formed. A groove that penetrates and reaches a diffusion layer that is a source or drain region of the transfer transistor is formed, a cylindrical first electrode film is formed on a side wall in the groove, and a first electrode film is formed inside the first electrode film. A second electrode film having a cylindrical shape is formed on the first electrode film and the second electrode film via a capacitance insulating film formed on the surfaces of the first electrode film and the second electrode film. An opposing third electrode film is formed, a fourth electrode film is formed on the insulating film layer along an edge of the groove, and is electrically connected to the first electrode film; The electrode film of the front Serial also to the fourth electrode layer is formed so as to face each other through the capacitor insulating film, wherein a portion of the first electrode layer is the diffusion layer electrically connected to and the capacitor formed And the insulating film layer is a lower insulating layer.
The film layer and the lower insulating film layer are different types of upper insulating film layers.
The diameter of the groove formed in the two-layer structure and reaching the diffusion layer is:
The lower insulating film layer close to the diffusion layer is small,
The upper insulating film layer is set to be large,
The groove formed in the insulating film layer of the layer is filled with a conductive material,
The first electrode is provided in a groove formed in the upper insulating film layer.
A film and a second electrode film are formed and electrically connected to the conductive material.
Wherein a being. 2. A process for forming an insulating film layer covering the transfer transistor, forming a first groove reaching the diffusion layer is a source or drain region of the transfer transistor on the insulating film layer, said first Filling a groove with a conductive material, depositing the insulating film layer and the conductive material to deposit a capacitor groove insulating film different from the insulating film layer, Forming a second groove reaching the surface of the conductive material in the film; and forming a first groove covering the exposed conductive material, a side wall of the second groove and an upper part of the insulating film for the capacity groove. Depositing a conductive film, forming a spacer film on a side surface of the first conductive film adhered to a side wall of the second groove, and forming a surface of the spacer film and the first conductive film. Applying a second conductive film on the surface of the body film Forming a second electrode film on a side wall of the spacer film by performing anisotropic dry etching on the second conductor film; and patterning the first conductor film into a predetermined shape to form a first electrode film. Forming an electrode film of
Removing the spacer film by etching. 3. The method of manufacturing a semiconductor device according to claim 2, wherein an insulating material is used in which a dry etching rate of said insulating film for said capacitor groove is higher than a dry etching rate of said insulating film layer.