JPH11345948A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure a sufficient stored capacity and to realize a high reliability even when suppressing the occurrence of steps by making the memory capacitor of a DRAM small, and suppressing the height low even if achieving the further minute configuration and high integration of a semiconductor element. SOLUTION: After a storage-node electrode 17 is uprightly provided in a storage-contact device 12, a high dielectric film such as a Ta2 O5 film 18 such as a super lattice (so-called Y-1) including PZT, SrBi2 , Ta2 O9 and SrBi2 Nb2 O9 is formed so as to cover the surface of the storage-node electrode 17. A cell- plate electrode 19 is formed so as to fill the inside of the storage contact 12 through a conductive ground film 23 covering the high dielectric film 18. A memory capacitor which performs the capacity coupling of the storage node 17 and a cell-plate electrode 19 in the storage contact 12 is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and is particularly suitable for application to a semiconductor memory device having a memory capacitor such as a DRAM.

[0002]

2. Description of the Related Art In recent years, miniaturization and high integration of semiconductor devices have been progressing. Accordingly, in a DRAM which is a typical semiconductor memory device, a lower electrode (storage node electrode) and an upper electrode (cell plate electrode) are made of a dielectric material in order to increase the effective memory cell capacity of the memory capacitor. A so-called stack type memory capacitor which is arranged to face through a film is widely used. In such a memory capacitor, the capacity of the memory cell is determined by the facing area of the storage node electrode and the cell plate electrode.

A technique for increasing the surface area of a storage node electrode of a memory capacitor is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-179.
As described in Japanese Patent Publication No. 68, a storage node electrode of a memory capacitor is formed so as to expand laterally above a storage contact hole, and a dielectric film is formed on a surface including the inside of the storage contact hole of the storage node electrode. A method of forming a cell plate electrode through the dielectric film so as to cover the storage node electrode even in the storage contact hole is known. According to this technique,
Since the facing area between the storage node electrode and the cell plate electrode is increased by utilizing the inside of the storage contact hole, a large capacity of the memory capacitor can be secured.

[0004]

However, in a stacked memory capacitor, as the miniaturization and the degree of integration of a semiconductor element further progress, the storage capacity required for the memory capacitor remains unchanged and the occupied area is increased. Will decrease. In this case, in order to increase the effective facing area between the storage node electrode and the cell plate electrode, the thickness of the storage node electrode must be increased. If the storage node electrode becomes thicker, one of the main causes is the height of the memory capacitor, causing a large step between the memory cell section and its peripheral circuit section. There is a problem in that poor resolution occurs.

In the method disclosed in Japanese Patent Application Laid-Open No. 9-17968, it is necessary to form the storage node electrode so as to greatly expand above the storage contact hole. Therefore, the problem of a step with the peripheral circuit cannot be avoided. . Therefore, it cannot be said that this method can sufficiently cope with miniaturization and high integration of semiconductor elements in the future, and further measures are required.

In view of the foregoing, an object of the present invention is to respond to recent demands for further miniaturization and higher integration of a semiconductor device while suppressing the occurrence of steps by reducing the size and height of a capacitor. Another object of the present invention is to provide a semiconductor device, a semiconductor memory device, and a method for manufacturing the same, which can secure a sufficient storage capacity.

[0007]

According to the present invention, there is provided a semiconductor memory device in which an access transistor having a gate and a pair of impurity diffusion layers and a memory in which a lower electrode and an upper electrode face and are capacitively coupled to each other via a capacitive insulating film. A semiconductor memory device including a capacitor, wherein the lower electrode is formed on the one of the impurity diffusion layers in an opening communicating with the one of the impurity diffusion layers by piercing an interlayer insulating film covering the access transistor. And a surface of the lower electrode is covered with the capacitive insulating film made of a high dielectric material, and faces the upper electrode via the capacitive insulating film in the opening.

In one embodiment of the semiconductor memory device of the present invention, the upper electrode faces the semiconductor substrate within the opening.

In one embodiment of the semiconductor memory device according to the present invention, the lower electrode is formed of a material selected from tungsten, tungsten nitride, platinum, titanium nitride, molybdenum nitride, tungsten carbide and ruthenium oxide. It is a thing.

In one embodiment of the semiconductor memory device according to the present invention, the capacitance insulating film is a film containing a ferroelectric material.

In one embodiment of the semiconductor memory device according to the present invention, the capacitor insulating film made of the high dielectric is made of Ta ₂
O ₅ , Ba _1-x Sr _x TiO ₃ , PZT, and SrBi
_It is formed using one material selected from superlattices (so-called Y-1) containing ₂ Ta ₂ O ₉ and SrBi ₂ Nb ₂ O ₉ .

In one embodiment of the semiconductor memory device according to the present invention, the upper electrode is formed using one material selected from tungsten and polycrystalline silicon.

In one embodiment of the semiconductor memory device of the present invention, at least a first conductive film underlying the lower electrode and the capacitive insulating film is formed between the upper electrode and the capacitive insulating film. A conductive second base film is formed between them.

In one embodiment of the semiconductor memory device according to the present invention, a conductive third base film that directly covers at least the semiconductor substrate is formed on the inner wall of the opening.

In one embodiment of the semiconductor memory device of the present invention, a nitride film directly covering at least the semiconductor substrate is formed on the inner wall of the opening, and the capacitor insulating film is formed on a surface of the nitride film. I have.

In one embodiment of the semiconductor memory device of the present invention, at least a conductive fourth underlayer is formed between the lower electrode and the semiconductor substrate.

A semiconductor memory device according to the present invention includes: a semiconductor region; an interlayer insulating film deposited on the semiconductor region and having an opening formed to expose a part of the surface of the semiconductor region; A first conductive film erected on the semiconductor region, a capacitor insulating film made of a high dielectric substance and covering the first conductive film in the opening, and a side of the capacitor insulating film and the opening. The first conductive film is covered with the gap between the wall surface and the opening through the capacitive insulating film through the capacitive insulating film, and is capacitively coupled to the first conductive film, and extends on the interlayer insulating film. And an existing second conductive film.

In one embodiment of the semiconductor memory device according to the present invention, the first conductive film is made of a material selected from tungsten, tungsten nitride, platinum, titanium nitride, molybdenum nitride, tungsten carbide and ruthenium oxide. It is formed as.

In one embodiment of the semiconductor memory device according to the present invention, the capacitance insulating film is a film containing a ferroelectric material.

In one embodiment of the semiconductor memory device of the present invention
In one embodiment, the capacitance insulating film is made of Ta._Two O _Five , Ba_1-xSr_x
TiO_Three , PZT, and SrBi_TwoTa_TwoO₉And SrB
i_TwoNb_TwoO₉(A so-called Y-1)
It is formed from one of the materials selected
You.

In one embodiment of the semiconductor memory device according to the present invention, the second conductive film is formed by using one material selected from tungsten and polycrystalline silicon.

In one embodiment of the semiconductor memory device according to the present invention, at least a first conductive underlayer film is provided between the lower electrode and the capacitor insulating film, and the conductive underlayer is formed between the upper electrode and the capacitor insulating film. A conductive second base film is formed between them.

In one embodiment of the semiconductor memory device according to the present invention, a conductive third base film that directly covers at least the semiconductor substrate is formed on the inner wall of the opening.

In one embodiment of the semiconductor memory device of the present invention, a nitride film that directly covers at least the semiconductor substrate is formed on an inner wall of the opening, and the capacitance insulating film is formed on a surface of the nitride film. I have.

According to the method of manufacturing a semiconductor memory device of the present invention, an access transistor having a gate and a pair of impurity diffusion layers, and a memory capacitor in which a lower electrode and an upper electrode face and are capacitively coupled to each other via a dielectric film. Forming a first insulating film covering the access transistor, wherein the first step comprises:
A second step of patterning the surface of the insulating film to form an opening exposing a part of the surface of the impurity diffusion layer of one of the access transistors; and a second step of covering only an inner wall surface of the opening. A third step of forming an insulating film, and the first step of burying the opening through the second insulating film.
A fourth step of forming a first conductive film on the first insulating film, and removing the first conductive film on the first insulating film so that the second insulating film is exposed; A fifth step of leaving the first conductive film in the hole, and forming a void between the first conductive film and the inner wall surface of the opening by removing the second insulating film; A sixth step of forming a lower electrode while leaving the first conductive film so as to be erected on the one of the impurity diffusion layers in the opening, and a step of forming a lower electrode so as to cover the surface of the lower electrode. A seventh step of forming a third insulating film made of a dielectric, and the first step of filling the void in the opening.
After forming a second conductive film on the first insulating film, the second conductive film is processed to cover the lower electrode via the third insulating film and extend on the first insulating film. An eighth step of forming an existing upper electrode.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, in the fifth step, the first conductive film is formed by a chemical mechanical polishing method until a part of the second insulating film is exposed. Is removed by polishing.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the first conductive film is made of tungsten,
It is formed using one material selected from tungsten nitride, platinum, titanium nitride, molybdenum nitride, tungsten carbide, and ruthenium oxide.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the capacitor insulating film is a film containing a ferroelectric material.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the third insulating film is made of Ta ₂ O ₅ , B
a _1-x Sr _x TiO ₃ , PZT, and SrBi ₂ Ta ₂
It is formed using one material selected from a superlattice (so-called Y-1) containing O ₉ and SrBi ₂ Nb ₂ O ₉ .

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the second conductive film is formed using one material selected from tungsten and polycrystalline silicon.

In one embodiment of the method of manufacturing a semiconductor memory device according to the present invention, after the second step and before the third step, the first insulating film and the material are formed on the inner wall of the opening. A ninth step of forming a fourth insulating film different from the first step, wherein, in the third step, the second insulating film is formed via the fourth insulating film; In the method, the second insulating film is removed together with the fourth insulating film.

In one embodiment of the method of manufacturing a semiconductor memory device according to the present invention, after the third step and before the fourth step,
A tenth step of forming a conductive first base film so as to cover at least a surface of the semiconductor substrate in the opening;
After the sixth step, before the seventh step, an eleventh step of forming a conductive second base film so as to cover the inner surface of the gap, and after the seventh step, And a twelfth step of forming a conductive third base film so as to cover the third insulating film before the eighth step.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, after the second step and before the third step, the first insulating film and the material are formed on the inner wall of the opening. A ninth step of forming a fourth insulating film different from the first step, wherein, in the third step, the second insulating film is formed via the fourth insulating film; In the above, only the fourth insulating film is left only on the inner wall of the opening.

One embodiment of the method for manufacturing a semiconductor memory device according to the present invention is as follows: after the third step and before the fourth step,
A thirteenth step of forming a conductive first base film so as to cover at least a surface of the semiconductor substrate in the opening;
After the seventh step and before the eighth step, the third
And a fourteenth step of forming a conductive second base film so as to cover the insulating film.

[0035]

In the semiconductor memory device according to the present invention, a lower electrode (first conductive film) is provided upright in an opening formed in an interlayer insulating film, and a high-dielectric-capacitance insulating material is provided so as to cover the lower electrode. A film is formed. Usually, the step of the memory cell portion from the peripheral circuit portion is mainly governed by the height of the lower electrode. However, in the present invention, the lower electrode is housed in the opening and does not exist above the opening. Therefore, a sufficient reduction in the level difference is achieved. Further, the capacitance of the capacitor depends on the area of the lower electrode and the upper electrode (second conductive film) facing each other via the capacitive insulating film, that is, the surface area of the lower electrode. Although its surface area is relatively small, the capacitance insulating film is made of, for example, Ta.
₂ O ₅ , BaSrTiO ₃ , PZT, SrBi ₂ Ta ₂
Since it is made of a high dielectric substance such as a superlattice (so-called Y-1) containing O ₉ and SrBi ₂ Nb ₂ O ₉ , a sufficient capacitance can be obtained.

That is, in the semiconductor memory device of the present invention, it is possible to secure a sufficient capacitance of the capacitor while greatly reducing the level difference between the memory cell portion and the peripheral circuit portion almost to the limit.

In the method of manufacturing a semiconductor memory device according to the present invention, a first conductive film serving as a lower electrode is formed so as to stand in an opening formed in a first insulating film serving as an interlayer insulating film. Then, a high-dielectric capacitance insulating film is formed so as to cover the lower electrode. Here, when the lower electrode is formed upright in the opening, the first conductive film on the first insulating film is removed by etching or the like, and the lower electrode made of the first conductive film is formed only in the opening. Since the electrodes are formed in a predetermined shape in a self-aligned manner, the patterning step is omitted.

Further, in the present invention, since the lower electrode is accommodated in the opening and is not formed above the opening, a sufficient step reduction can be achieved. Further, the capacitance of the capacitor depends on the area of the lower electrode facing the upper electrode made of the second conductive film, ie, the surface area of the lower electrode via the third insulating film serving as a capacitive insulating film. The third insulating film is made of, for example, Ta ₂ O ₅ , Ba _1-x Sr _x TiO ₃ , PZT, or SrBi ₂ Ta ₂ O, although its surface area is relatively small because it exists in the opening.
₉ and SrBi ₂ Nb ₂ O ₉ (so-called Y
Since it is made of a high dielectric substance as in -1), a sufficient capacitance can be obtained.

That is, in the present invention, not only the complicated patterning step is omitted but the process is shortened, but also the level difference between the memory cell section and the peripheral circuit section is substantially reduced to the limit, It becomes possible to manufacture a semiconductor memory device having a capacitor whose capacity is ensured.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of a semiconductor memory device and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings. In this embodiment, a so-called COB (Capacitor) in which an access transistor and a memory capacitor are provided as a semiconductor memory device, and the memory capacitor is formed substantially above a bit line.
An example of a DRAM having an Over Bitline structure will be described, and the configuration thereof will be described together with a manufacturing method. 1 to 7 are schematic sectional views showing a method for manufacturing a DRAM of this embodiment in the order of steps.

First, as shown in FIG.
A field oxide film 3 is formed as a device isolation structure on a silicon semiconductor substrate 1 of a mold by a so-called LOCOS method to define a device formation region 2. Instead of the field oxide film 3, a conductive film is buried in the insulating film by a field shield element isolation method, and a portion of the silicon semiconductor substrate immediately below is fixed at a predetermined potential by the conductive film to perform element isolation. May be formed. Further, it is possible to form a shallow trench type element isolation structure in which a trench is formed in the silicon semiconductor substrate 1 and an insulator is buried.

Next, the surface of the silicon semiconductor substrate 1 in the element formation region 2 which is separated and relatively defined by the field oxide film 3 is subjected to thermal oxidation to form a silicon oxide film. Is formed, and a silicon oxide film is sequentially formed on the polycrystalline silicon film.

Next, the silicon oxide film, the polycrystalline silicon film and the silicon oxide film are patterned by photolithography and subsequent dry etching, and the silicon oxide film, the polycrystalline silicon film and the silicon oxide film To form a gate oxide film 4, a gate electrode 5, and a cap insulating film 10 thereof.

Next, after the photoresist used for patterning is removed by incineration, a silicon oxide film is deposited and formed on the entire surface including the cap insulating film 10 by CVD, and the entire surface of the silicon oxide film is anisotropically formed. Etching is performed to form sidewalls 6 while leaving the silicon oxide film only on the side surfaces of the gate oxide film 4, the gate electrode 5, and the cap insulating film 10.

Then, using the cap insulating film 10 and the side walls 6 as masks, the acceleration energy of 30 to
150 keV, dose amount is 1 × 10 ¹⁴ to 1 × 10 ¹⁵
An impurity is introduced by ion implantation under the condition of about / cm ² to form a pair of impurity diffusion layers 7 serving as a source / drain, and an access transistor having the gate electrode 5 and the pair of impurity diffusion layers 7 is completed.

Then, as shown in FIG. 1B, CV is applied to the entire surface of the silicon semiconductor substrate 1 including the field oxide film 3.
Borophosphate silicate glass (BPSG) or the like is deposited and formed by the method D to form the interlayer insulating film 8.

Next, a bit line (not shown) electrically connected to one of the impurity diffusion layers 7 (to be a drain) in the interlayer insulating film 8.
Is patterned to form an interlayer insulating film 8 (and bit lines).
An interlayer insulating film 11 made of a silicon oxide film is deposited thereon by CVD to a thickness of about 50 nm. Subsequently, the interlayer insulating film 11 and the interlayer insulating film 8 are patterned by photolithography and subsequent dry etching to expose a part of the surface of the other impurity diffusion layer 7 (to be a source) of the access transistor. To form This storage contact 12
Is formed to a depth of about 0.5 μm to 1.0 μm.

Next, as shown in FIG. 1C, a silicon nitride film 13 having a thickness of about 10 nm is formed on the interlayer insulating film 11 including the inner wall surface of the storage contact 12 by the CVD method.
And a silicon oxide film 14 having a thickness of about 20 nm to 50 nm.
Are sequentially formed.

Next, as shown in FIG. 2, the silicon oxide film 14 and the silicon oxide film 13 are subjected to anisotropic dry etching until the surface of the interlayer insulating film 8 other than the inside of the storage contact 12 is exposed. A portion of the surface of the (source) is again exposed, and a sidewall 15 composed of both is formed while leaving the silicon nitride film 13 and the silicon oxide film 14 only on the side wall surface of the storage contact 12. The silicon oxide film 1
4 and a BPSG film is formed.
A sidewall made of a PSG film may be formed. As will be described later, in consideration of removing the sidewall 15, it may be better to form the sidewall from the BPSG film.

Next, as shown in FIG. 3, titanium nitride (Ti) is formed on the entire surface including the surface of the sidewall 15 in the storage contact 12 by sputtering or CVD.
An N) / titanium (Ti) two-layer structure film 21 (shown as a single layer for convenience in the illustrated example) is formed to a thickness of about 50 to 100 nm. Subsequently, a tungsten film 16 is formed to a thickness of about 500 nm by a CVD method so as to bury the storage contact 12 via the two-layer structure film 21. Here, instead of the tungsten film 16, it is preferable to form a conductive film using platinum, ruthenium oxide, TiN, or the like.

Next, as shown in FIG. 4, the tungsten film 16 is polished by a chemical mechanical polishing method (CMP method) until a part of the side wall 15 is exposed, and the tungsten film 16 is left only in the storage contact 12. At this time, the storage node electrode 17, which is the lower electrode of the memory capacitor connected to the impurity diffusion layer 7 serving as the source in the storage contact 12, is formed in a self-aligned manner without using patterning.

Subsequently, as shown in FIG. 5, a first cleaning using hydrofluoric acid is performed, followed by a second cleaning using hot phosphoric acid. Here, the silicon oxide film 14 constituting the sidewall 15 is removed from the inside of the storage contact 12 by leaving the silicon nitride film 13 by the first cleaning, and the remaining silicon nitride film 13 is removed by the subsequent second cleaning. A space 12 a is formed between the side wall surface of storage contact 12 and storage node electrode 17. In addition,
Instead of this method, the silicon oxide film 14 and the silicon nitride film 13 may be continuously removed by performing hydrofluoric acid vapor phase cleaning.

Next, as shown in FIG. 6, the entire surface including the surface in the gap 12a is formed by sputtering or CVD.
The iN film 22 is formed to a thickness of about 50 to 100 nm. Subsequently, the CVD method is used to cover the surface in the gap 12a, that is, the surface of the storage node electrode 17 via the TiN film 22 and the inner wall surface of the storage contact 12 via the TiN film 22 in the storage contact 12. A dielectric film (ferroelectric film), here, a Ta ₂ O ₅ film (tantalum oxide film) is deposited to a thickness of about 10 nm to 30 nm to form the capacitor insulating film 18. In this case, as the capacitor insulating film 18, an insulating film having a higher dielectric constant than an ONO film or the like conventionally used as a capacitor insulating film, for example, Ta is used.
_In addition to the ₂ O ₅ film, a Ba _1-x Sr _x TiO ₃ film or PZT
(Titanium lead zirconate), SrBi ₂ Ta ₂ O ₉ and Sr
It is also preferable to form a film using a superlattice containing Bi ₂ Nb ₂ O ₉ (so-called Y-1) or the like.

Next, as shown in FIG. 7, a TiN film 23 is formed to a thickness of about 50 to 100 nm on the entire surface so as to cover the capacitor insulating film 18 by a sputtering method or a CVD method.
Then, a tungsten film is formed on the interlayer insulating film 11 by CVD so as to cover the storage node electrode 17 in the storage contact 12 via the capacitor insulating film 18 and fill the void 12a in the storage contact 12. It is formed to have a thickness of about 200 nm to 500 nm. Here, for example, a polycrystalline silicon film is preferably formed instead of the tungsten film.

Next, photolithography and subsequent dry etching are performed on the tungsten film to form a cell plate electrode 19 having a predetermined shape, which is the upper electrode of the memory capacitor. The storage node electrode 17, the capacitor insulating film 18, and the cell plate electrode A memory capacitor having an electrode 19 and configured so that the storage node electrode 17 and the cell plate electrode 19 are capacitively coupled in the storage contact 12 is completed.

Thereafter, although not shown, further formation of an interlayer insulating film, formation of a contact hole and subsequent formation of a wiring layer, and formation of a peripheral circuit portion of a memory cell portion (this peripheral circuit portion is a memory cell portion And the like are often formed sequentially.), Etc., to complete the DRAM.

As described above, according to the embodiment of the present invention, the storage node electrode 17 is formed so as to stand in the storage contact 12 formed on the interlayer insulating film 8 and the planarization layer 11. A high-dielectric capacity insulating film 18 is formed so as to cover the node electrode 17. Here, when the storage node electrode 17 is formed upright in the storage contact 12, the tungsten film 16 on the planarization layer 11 is removed by etching or the like, and the storage node electrode 17 is formed only in the storage contact 12 in a predetermined shape. In this case, the patterning step is omitted.

According to the DRAM of this embodiment, the storage node electrode 17 is provided upright in the storage contact 12 formed on the interlayer insulating film 8 and the planarization layer 11 so as to cover the storage node electrode 17. A high dielectric capacity insulating film 18 is formed. Normally, the level difference between the memory cell portion and the peripheral circuit portion is mainly governed by the height of the storage node electrode. In this embodiment, the storage node electrode 17 is accommodated in the storage contact 12, and the storage contact 12 Since the storage node electrode does not exist above the gate electrode, the step is about 50 nm, which is the thickness of the storage node electrode 17 plus the cell plate electrode 19. In consideration of the fact that the conventional step is about 1 μm, a sufficient reduction in the step can be obtained according to the present embodiment. Furthermore, the capacitance of the memory capacitor depends on the area of the storage node electrode and the cell plate electrode facing each other via the capacitance insulating film, that is, the surface area of the storage node electrode. In this embodiment, the storage node electrode 17 is located inside the storage contact 12. The capacitance insulating film 18 is made of Ta ₂ O ₅ , Ba _1-x Sr _x TiO ₃ , PZT or SrB.
Since consisting i ₂ Ta ₂ O ₉ and SrBi ₂ Nb ₂ O ₉ and such high dielectric superlattice comprising (a so-called Y-1), sufficient capacity is obtained.

That is, in the present embodiment, not only a complicated patterning step can be omitted to shorten the process, but also the memory cell portion and the peripheral circuit portion can be greatly reduced in level to almost the limit, and It is possible to secure a sufficient capacity of the capacitor.

According to this DRAM, even if further miniaturization and higher integration are performed, a sufficient memory cell capacity is secured while suppressing the occurrence of steps by reducing the size and height of the memory capacitor. And high reliability can be realized.

(Modification) Here, a modification of the present embodiment will be described. In this modification, a DRAM is manufactured almost in the same manner as in the present embodiment, but differs in that there are some differences in several steps. Note that the same components as those of the DRAM of the present embodiment are denoted by the same reference numerals, and description thereof is omitted.

First, as in the case of this embodiment, FIGS.
After each step of FIG. 4, the tungsten film 16 is formed only in the storage contact 12,
A storage node electrode 17, which is a lower electrode of a memory capacitor connected to the impurity diffusion layer 7 serving as a source therein, is formed in a self-aligned manner without using patterning.

Subsequently, as shown in FIG. 8, cleaning using hydrofluoric acid is performed to remove the silicon oxide film 14 constituting the sidewall 15 from the storage contact 12 while leaving only the silicon nitride film 13. In this case, by adjusting the cleaning time, a desired result that only the silicon nitride film 13 remains in the storage contact 12 can be obtained.

Next, as shown in FIG. 9, the surface within the gap 12a, that is, the surface of the storage node electrode 17 and the inner wall surface of the storage contact 12 via the silicon nitride film 13 in the storage contact 12, are formed by the CVD method. A high dielectric film (ferroelectric film) such as Ta
₂ O ₅ film (tantalum oxide film) with a thickness of 10 nm to 3
The capacitor insulating film 18 is formed by being deposited to a thickness of about 0 nm. B
An interlayer insulating film 11 made of the interlayer insulating film 8 and the silicon oxide film of PSG film, it has poor adhesion to the the Ta ₂ O ₅ film, forming a the Ta ₂ O ₅ film through the base film 22 in this embodiment did. On the other hand, in this modification, since the silicon nitride film 13 remains on the inner wall surface of the storage contact 12, the formation of the base film 22 becomes unnecessary, and the number of steps is reduced.

Next, as shown in FIG. 10, a TiN film 2 is formed on the entire surface so as to cover the capacitance insulating film 18 by sputtering.
3 is formed to a thickness of about 50 to 100 nm. Then, C
By a VD method, a 200 nm-thick tungsten film is formed on the planarization layer 11 so as to cover the storage node electrode 17 in the storage contact 12 via the capacitor insulating film 18 and fill the void 12 a in the storage contact 12.
It is formed to about 500 nm. Here, for example, a polycrystalline silicon film is preferably formed instead of the tungsten film.

Subsequently, photolithography and subsequent dry etching are performed on the tungsten film to form a cell plate electrode 19 having a predetermined shape as an upper electrode of the memory capacitor, and the storage node electrode 17, the capacitor insulating film 18, and the cell A memory capacitor having a plate electrode 19 and configured so that the storage node electrode 17 and the cell plate electrode 19 are capacitively coupled in the storage contact 12 is completed.

Thereafter, although not shown, further formation of an interlayer insulating film, formation of a contact hole and subsequent formation of a wiring layer, formation of a peripheral circuit portion of a memory cell portion (this peripheral circuit portion is a memory cell portion And the like are often formed sequentially.), Etc., to complete the DRAM.

According to this modification, the storage node electrode 17 is formed in the storage contact 12 formed on the interlayer insulating film 8 and the planarization layer 11 as in the case of the present embodiment.
Are formed so as to stand, and the storage node electrode 1 is formed.
The capacitor insulating film 18 of a high dielectric is formed so as to cover.
Here, when the storage node electrode 17 is formed upright in the storage contact 12, the tungsten film 16 on the planarization layer 11 is removed by etching or the like, and the storage node electrode 17 is formed only in the storage contact 12.
Is formed in a predetermined shape in a self-aligned manner, so that the patterning step is omitted.

According to the DRAM of the modified example, the storage node electrode 17 is provided upright in the storage contact 12 formed on the interlayer insulating film 8 and the planarization layer 11, and the storage node electrode 17 is formed so as to cover the storage node electrode 17. A dielectric capacitance insulating film 18 is formed. Normally, the level difference between the memory cell portion and the peripheral circuit portion is mainly governed by the height of the storage node electrode. In this embodiment, the storage node electrode 17 is accommodated in the storage contact 12, and the storage contact 12 Since the storage node electrode does not exist above the gate electrode, the level difference is about 500 nm, which is the film thickness of the sum of the storage node electrode 17 and the cell plate electrode 19. In consideration of the fact that the conventional step is about 1 μm, a sufficient reduction in the step can be obtained according to the present embodiment. Furthermore, the capacitance of the memory capacitor depends on the area of the storage node electrode and the cell plate electrode facing each other via the capacitance insulating film, that is, the surface area of the storage node electrode. In this embodiment, the storage node electrode 17 is located inside the storage contact 12. Although the surface area is relatively small because of the existence of
a ₂ O ₅ , Ba _1-x Sr _x TiO ₃ , PZT, SrBi
Since consisting such high dielectric superlattices (so-called Y-1) containing a ₂ Ta ₂ O ₉ and SrBi ₂ Nb ₂ O _9, sufficient capacity is obtained.

That is, in the modification, not only the complicated patterning step can be omitted to shorten the process, but also the step of the memory cell portion from the peripheral circuit portion can be substantially reduced to the limit, while the memory capacitor portion can be reduced. Sufficient capacity can be secured.

According to this DRAM, even if further miniaturization and higher integration are performed, a sufficient memory cell capacity is secured while suppressing the occurrence of steps by reducing the size and height of the memory capacitor. And high reliability can be realized.

In this embodiment and its modifications, C
Although the DRAM having the OB structure has been described, the present invention is not limited to this. For example, a so-called CUB (Capa) in which a memory capacitor is formed substantially below a bit line.
It is also applicable to DRAMs having a citor under bitline) structure.

[0073]

According to the present invention, in response to recent demands for further miniaturization and higher integration of semiconductor devices, the size of the capacitor is reduced and the height is reduced to suppress the occurrence of steps. In addition, it is possible to secure a sufficient storage capacity and realize high reliability.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

FIG. 2 is a continuation of FIG. 1 showing D in an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing a RAM in the order of steps.

FIG. 3 is a continuation of FIG. 2 showing D in the embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing a RAM in the order of steps.

FIG. 4 is a continuation of FIG. 3 showing D in the embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing a RAM in the order of steps.

FIG. 5 is a continuation of FIG. 4 showing D in the embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing a RAM in the order of steps.

FIG. 6 is a continuation of FIG. 5 showing D in the embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing a RAM in the order of steps.

FIG. 7 is a continuation of FIG. 6 showing D in the embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view showing a method of manufacturing a RAM in the order of steps.

FIG. 8 is a schematic sectional view showing main steps of a modification of the DRAM manufacturing method according to the embodiment of the present invention.

FIG. 9 is a continuation of FIG. 8 showing D in the embodiment of the present invention;
FIG. 13 is a schematic cross-sectional view showing main steps of a modification of the method of manufacturing a RAM.

FIG. 10 is a schematic cross-sectional view showing a main step of a modification of the method of manufacturing the DRAM according to the embodiment of the present invention, following FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Element formation area 3 Field oxide film 4 Gate oxide film 5 Gate electrode 6, 15 Side wall 7 Impurity diffusion layer 8 Interlayer insulating film 11 Flattening film 12 Storage contact 13 Silicon nitride film 14 Silicon oxide film 16 Tungsten film Reference Signs List 17 storage node electrode 18 capacitance insulating film 19 cell plate electrode 21 two-layer structure film of TiN / Ti 22, 23 TiN film

Claims (28)

[Claims] 1. A semiconductor memory device comprising: an access transistor having a gate and a pair of impurity diffusion layers; and a memory capacitor in which a lower electrode and an upper electrode are capacitively coupled to each other via a capacitive insulating film. The lower electrode is erected on the one impurity diffusion layer in an opening communicating with the one impurity diffusion layer by piercing an interlayer insulating film covering the access transistor, and the surface of the lower electrode is made of a high dielectric material. Wherein the semiconductor device is covered with the capacitor insulating film made of, and faces the upper electrode via the capacitor insulating film in the opening. 2. The semiconductor memory device according to claim 1, wherein said upper electrode faces said semiconductor substrate within said opening. 3. The method according to claim 1, wherein the lower electrode is made of one material selected from the group consisting of tungsten, tungsten nitride, platinum, titanium nitride, molybdenum nitride, tungsten carbide, and ruthenium oxide. 3. The semiconductor memory device according to 1 or 2. 4. The semiconductor memory device according to claim 1, wherein said capacitor insulating film is a film containing a ferroelectric material. 5. The capacitor insulating film is formed of Ta ₂ O ₅ , Ba
_1-x Sr _x TiO ₃ , PZT, and SrBi ₂ Ta ₂ O
₉ and SrBi ₂ Nb ₂ O ₉ and the semiconductor memory according to any one of claims 1 to 4, characterized in that the one kind selected from the superlattice is one formed as a material containing apparatus. 6. The method according to claim 1, wherein the upper electrode is formed using one of tungsten and polycrystalline silicon as a material. Semiconductor storage device. 7. At least a conductive first base film between the lower electrode and the capacitor insulating film, and a conductive second base film between the upper electrode and the capacitor insulating film. The semiconductor memory device according to claim 1, wherein each of the semiconductor memory devices is formed. 8. The semiconductor memory device according to claim 7, wherein a conductive third base film that directly covers at least the semiconductor substrate is formed on an inner wall of the opening. 9. The semiconductor device according to claim 7, wherein a nitride film directly covering at least the semiconductor substrate is formed on an inner wall of the opening, and the capacitor insulating film is formed on a surface of the nitride film. Semiconductor storage device. 10. The semiconductor memory device according to claim 7, wherein a conductive fourth underlayer is formed at least between said lower electrode and said semiconductor substrate. 11. A semiconductor region, an interlayer insulating film deposited on the semiconductor region and having an opening formed to expose a part of the surface of the semiconductor region, and standing on the semiconductor region within the opening. A first conductive film provided; a capacitive insulating film made of a high-dielectric material and covering the first conductive film in the opening; and a gap between the capacitive insulating film and a side wall surface of the opening. To cover the first conductive film in the opening through the capacitive insulating film via the capacitive insulating film, and capacitively couple with the first conductive film, and extend on the interlayer insulating film. And a film. 12. The first conductive film is made of tungsten,
The semiconductor memory device according to claim 11, wherein the semiconductor memory device is formed using one material selected from tungsten nitride, platinum, titanium nitride, molybdenum nitride, tungsten carbide, and ruthenium oxide. 13. The semiconductor memory device according to claim 11, wherein said capacitor insulating film is a film containing a ferroelectric material. 14. The capacitor insulating film is made of Ta ₂ O ₅ , Ba
_1-x Sr _x TiO ₃ , PZT, and SrBi ₂ Ta ₂ O
14. The semiconductor memory according to claim 11, wherein the semiconductor memory is formed using one material selected from a superlattice containing ₉ and SrBi ₂ Nb ₂ O _9. apparatus. 15. The semiconductor device according to claim 11, wherein the second conductive film is formed using one material selected from tungsten and polycrystalline silicon.
5. The semiconductor memory device according to any one of 4. 16. At least a conductive first base film between the lower electrode and the capacitor insulating film, and a conductive second base film between the upper electrode and the capacitor insulating film. 16. Each of them is formed.
7. The semiconductor memory device according to claim 1. 17. The semiconductor memory device according to claim 16, wherein a conductive third base film directly covering at least the semiconductor substrate is formed on an inner wall of the opening. 18. The semiconductor device according to claim 16, wherein a nitride film directly covering at least the semiconductor substrate is formed on an inner wall of the opening, and the capacitor insulating film is formed on a surface of the nitride film. Semiconductor storage device. 19. A method for manufacturing a semiconductor memory device, comprising: an access transistor having a gate and a pair of impurity diffusion layers; and a memory capacitor in which a lower electrode and an upper electrode are capacitively opposed to each other via a dielectric film. A first step of forming a first insulating film covering the access transistor; and patterning the first insulating film to expose a part of the surface of the impurity diffusion layer of one of the access transistors. A second step of forming an opening, a third step of forming a second insulating film covering only an inner wall surface of the opening, and filling the opening through the second insulating film. Forming a first conductive film on the first insulating film, and removing the first conductive film on the first insulating film so that the second insulating film is exposed. And the first hole in the opening. A fifth step of leaving a conductive film, and forming a gap between the first conductive film and the inner wall surface of the opening by removing the second insulating film; A sixth step of forming a lower electrode while leaving the first conductive film so as to be erected on the impurity diffusion layer, and a third step made of a high-dielectric material covering a surface of the lower electrode. A seventh step of forming an insulating film, and after forming a second conductive film on the first insulating film so as to fill the gap in the opening, processing the second conductive film An eighth step of forming an upper electrode extending over the first insulating film while covering the lower electrode with the third insulating film interposed therebetween. . 20. The method according to claim 1, wherein in the fifth step, the first conductive film is polished and removed by a chemical mechanical polishing method until a part of the second insulating film is exposed.
10. The method for manufacturing a semiconductor memory device according to item 9. 21. The first conductive film is made of tungsten,
21. The method for manufacturing a semiconductor memory device according to claim 19, wherein the semiconductor memory device is formed using one material selected from tungsten nitride, platinum, titanium nitride, molybdenum nitride, tungsten carbide, and ruthenium oxide. . 22. The method according to claim 19, wherein the capacitive insulating film is a film containing a ferroelectric material. 23. The third insulating film is formed of Ta_Two O_Five , B
a_1-xSr_xTiO _Three , PZT, and SrBi_TwoTa_Two
O₉And SrBi_TwoNb_TwoO₉From the superlattice containing
That it is formed from one selected material
23. A half as claimed in any one of claims 19 to 22, characterized in that
A method for manufacturing a conductor storage device. 24. The method according to claim 19, wherein the second conductive film is formed by using one material selected from tungsten and polycrystalline silicon.
3. The method of manufacturing a semiconductor memory device according to claim 3. 25. A ninth step of forming a fourth insulating film of a different material from the first insulating film on the inner wall of the opening after the second step and before the third step. In the third step, the second insulating film is formed via the fourth insulating film, and in the sixth step, the second insulating film is formed together with the fourth insulating film. 25. The method for manufacturing a semiconductor memory device according to claim 19, wherein the film is removed. 26. A method according to claim 26, further comprising: forming a conductive first underlayer so as to cover at least a surface of the semiconductor substrate in the opening before the fourth step after the third step. An eleventh step of, after the sixth step and before the seventh step, forming an electrically conductive second base film so as to cover an inner surface of the gap; and After the step and before the eighth step, the third
A twelfth step of forming a conductive third base film so as to cover said insulating film.
6. The method for manufacturing a semiconductor memory device according to item 5. 27. A ninth step of forming a fourth insulating film made of a different material from the first insulating film on the inner wall of the opening after the second step and before the third step. In the third step, the second insulating film is formed with the fourth insulating film interposed therebetween, and in the sixth step, only the fourth insulating film is covered with the opening. 25. The method of manufacturing a semiconductor memory device according to claim 19, wherein the semiconductor memory device is left only on the inner wall. 28. After the third step and before the fourth step, a thirteenth conductive layer is formed to cover at least the surface of the semiconductor substrate in the opening. And after the seventh step and before the eighth step, the third step
Forming a conductive second base film so as to cover said insulating film.
8. The method for manufacturing a semiconductor memory device according to item 7.